3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
8 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_GCOV_PROFILE_ALL
12 select ARCH_HAS_SG_CHAIN
13 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
14 select ARCH_USE_CMPXCHG_LOCKREF
15 select ARCH_SUPPORTS_ATOMIC_RMW
16 select ARCH_SUPPORTS_NUMA_BALANCING
17 select ARCH_WANT_OPTIONAL_GPIOLIB
18 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
19 select ARCH_WANT_FRAME_POINTERS
20 select ARCH_HAS_UBSAN_SANITIZE_ALL
24 select AUDIT_ARCH_COMPAT_GENERIC
25 select ARM_GIC_V2M if PCI_MSI
27 select ARM_GIC_V3_ITS if PCI_MSI
29 select BUILDTIME_EXTABLE_SORT
30 select CLONE_BACKWARDS
32 select CPU_PM if (SUSPEND || CPU_IDLE)
33 select DCACHE_WORD_ACCESS
36 select GENERIC_ALLOCATOR
37 select GENERIC_CLOCKEVENTS
38 select GENERIC_CLOCKEVENTS_BROADCAST
39 select GENERIC_CPU_AUTOPROBE
40 select GENERIC_EARLY_IOREMAP
41 select GENERIC_IDLE_POLL_SETUP
42 select GENERIC_IRQ_PROBE
43 select GENERIC_IRQ_SHOW
44 select GENERIC_IRQ_SHOW_LEVEL
45 select GENERIC_PCI_IOMAP
46 select GENERIC_SCHED_CLOCK
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_STRNCPY_FROM_USER
49 select GENERIC_STRNLEN_USER
50 select GENERIC_TIME_VSYSCALL
51 select HANDLE_DOMAIN_IRQ
52 select HARDIRQS_SW_RESEND
53 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
54 select HAVE_ARCH_AUDITSYSCALL
55 select HAVE_ARCH_BITREVERSE
56 select HAVE_ARCH_HUGE_VMAP
57 select HAVE_ARCH_JUMP_LABEL
58 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
60 select HAVE_ARCH_MMAP_RND_BITS
61 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
62 select HAVE_ARCH_SECCOMP_FILTER
63 select HAVE_ARCH_TRACEHOOK
64 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
67 select HAVE_C_RECORDMCOUNT
68 select HAVE_CC_STACKPROTECTOR
69 select HAVE_CMPXCHG_DOUBLE
70 select HAVE_CMPXCHG_LOCAL
71 select HAVE_CONTEXT_TRACKING
72 select HAVE_DEBUG_BUGVERBOSE
73 select HAVE_DEBUG_KMEMLEAK
74 select HAVE_DMA_API_DEBUG
75 select HAVE_DMA_CONTIGUOUS
76 select HAVE_DYNAMIC_FTRACE
77 select HAVE_EFFICIENT_UNALIGNED_ACCESS
78 select HAVE_FTRACE_MCOUNT_RECORD
79 select HAVE_FUNCTION_TRACER
80 select HAVE_FUNCTION_GRAPH_TRACER
81 select HAVE_GCC_PLUGINS
82 select HAVE_GENERIC_DMA_COHERENT
83 select HAVE_HW_BREAKPOINT if PERF_EVENTS
84 select HAVE_IRQ_TIME_ACCOUNTING
86 select HAVE_MEMBLOCK_NODE_MAP if NUMA
87 select HAVE_PATA_PLATFORM
88 select HAVE_PERF_EVENTS
90 select HAVE_PERF_USER_STACK_DUMP
91 select HAVE_REGS_AND_STACK_ACCESS_API
92 select HAVE_RCU_TABLE_FREE
93 select HAVE_SYSCALL_TRACEPOINTS
95 select HAVE_KRETPROBES if HAVE_KPROBES
96 select IOMMU_DMA if IOMMU_SUPPORT
98 select IRQ_FORCED_THREADING
99 select MODULES_USE_ELF_RELA
102 select OF_EARLY_FLATTREE
103 select OF_NUMA if NUMA && OF
104 select OF_RESERVED_MEM
105 select PERF_USE_VMALLOC
109 select SYSCTL_EXCEPTION_TRACE
111 ARM 64-bit (AArch64) Linux support.
116 config ARCH_PHYS_ADDR_T_64BIT
122 config ARM64_PAGE_SHIFT
124 default 16 if ARM64_64K_PAGES
125 default 14 if ARM64_16K_PAGES
128 config ARM64_CONT_SHIFT
130 default 5 if ARM64_64K_PAGES
131 default 7 if ARM64_16K_PAGES
134 config ARCH_MMAP_RND_BITS_MIN
135 default 14 if ARM64_64K_PAGES
136 default 16 if ARM64_16K_PAGES
139 # max bits determined by the following formula:
140 # VA_BITS - PAGE_SHIFT - 3
141 config ARCH_MMAP_RND_BITS_MAX
142 default 19 if ARM64_VA_BITS=36
143 default 24 if ARM64_VA_BITS=39
144 default 27 if ARM64_VA_BITS=42
145 default 30 if ARM64_VA_BITS=47
146 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
147 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
148 default 33 if ARM64_VA_BITS=48
149 default 14 if ARM64_64K_PAGES
150 default 16 if ARM64_16K_PAGES
153 config ARCH_MMAP_RND_COMPAT_BITS_MIN
154 default 7 if ARM64_64K_PAGES
155 default 9 if ARM64_16K_PAGES
158 config ARCH_MMAP_RND_COMPAT_BITS_MAX
164 config STACKTRACE_SUPPORT
167 config ILLEGAL_POINTER_VALUE
169 default 0xdead000000000000
171 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
177 config RWSEM_XCHGADD_ALGORITHM
184 config GENERIC_BUG_RELATIVE_POINTERS
186 depends on GENERIC_BUG
188 config GENERIC_HWEIGHT
194 config GENERIC_CALIBRATE_DELAY
200 config HAVE_GENERIC_RCU_GUP
203 config ARCH_DMA_ADDR_T_64BIT
206 config NEED_DMA_MAP_STATE
209 config NEED_SG_DMA_LENGTH
221 config KERNEL_MODE_NEON
224 config FIX_EARLYCON_MEM
227 config PGTABLE_LEVELS
229 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
230 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
231 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
232 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
233 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
234 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
236 source "init/Kconfig"
238 source "kernel/Kconfig.freezer"
240 source "arch/arm64/Kconfig.platforms"
247 This feature enables support for PCI bus system. If you say Y
248 here, the kernel will include drivers and infrastructure code
249 to support PCI bus devices.
254 config PCI_DOMAINS_GENERIC
260 source "drivers/pci/Kconfig"
264 menu "Kernel Features"
266 menu "ARM errata workarounds via the alternatives framework"
268 config ARM64_ERRATUM_826319
269 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
272 This option adds an alternative code sequence to work around ARM
273 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
274 AXI master interface and an L2 cache.
276 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
277 and is unable to accept a certain write via this interface, it will
278 not progress on read data presented on the read data channel and the
281 The workaround promotes data cache clean instructions to
282 data cache clean-and-invalidate.
283 Please note that this does not necessarily enable the workaround,
284 as it depends on the alternative framework, which will only patch
285 the kernel if an affected CPU is detected.
289 config ARM64_ERRATUM_827319
290 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
293 This option adds an alternative code sequence to work around ARM
294 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
295 master interface and an L2 cache.
297 Under certain conditions this erratum can cause a clean line eviction
298 to occur at the same time as another transaction to the same address
299 on the AMBA 5 CHI interface, which can cause data corruption if the
300 interconnect reorders the two transactions.
302 The workaround promotes data cache clean instructions to
303 data cache clean-and-invalidate.
304 Please note that this does not necessarily enable the workaround,
305 as it depends on the alternative framework, which will only patch
306 the kernel if an affected CPU is detected.
310 config ARM64_ERRATUM_824069
311 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
314 This option adds an alternative code sequence to work around ARM
315 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
316 to a coherent interconnect.
318 If a Cortex-A53 processor is executing a store or prefetch for
319 write instruction at the same time as a processor in another
320 cluster is executing a cache maintenance operation to the same
321 address, then this erratum might cause a clean cache line to be
322 incorrectly marked as dirty.
324 The workaround promotes data cache clean instructions to
325 data cache clean-and-invalidate.
326 Please note that this option does not necessarily enable the
327 workaround, as it depends on the alternative framework, which will
328 only patch the kernel if an affected CPU is detected.
332 config ARM64_ERRATUM_819472
333 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
336 This option adds an alternative code sequence to work around ARM
337 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
338 present when it is connected to a coherent interconnect.
340 If the processor is executing a load and store exclusive sequence at
341 the same time as a processor in another cluster is executing a cache
342 maintenance operation to the same address, then this erratum might
343 cause data corruption.
345 The workaround promotes data cache clean instructions to
346 data cache clean-and-invalidate.
347 Please note that this does not necessarily enable the workaround,
348 as it depends on the alternative framework, which will only patch
349 the kernel if an affected CPU is detected.
353 config ARM64_ERRATUM_832075
354 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
357 This option adds an alternative code sequence to work around ARM
358 erratum 832075 on Cortex-A57 parts up to r1p2.
360 Affected Cortex-A57 parts might deadlock when exclusive load/store
361 instructions to Write-Back memory are mixed with Device loads.
363 The workaround is to promote device loads to use Load-Acquire
365 Please note that this does not necessarily enable the workaround,
366 as it depends on the alternative framework, which will only patch
367 the kernel if an affected CPU is detected.
371 config ARM64_ERRATUM_834220
372 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
376 This option adds an alternative code sequence to work around ARM
377 erratum 834220 on Cortex-A57 parts up to r1p2.
379 Affected Cortex-A57 parts might report a Stage 2 translation
380 fault as the result of a Stage 1 fault for load crossing a
381 page boundary when there is a permission or device memory
382 alignment fault at Stage 1 and a translation fault at Stage 2.
384 The workaround is to verify that the Stage 1 translation
385 doesn't generate a fault before handling the Stage 2 fault.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_845719
393 bool "Cortex-A53: 845719: a load might read incorrect data"
397 This option adds an alternative code sequence to work around ARM
398 erratum 845719 on Cortex-A53 parts up to r0p4.
400 When running a compat (AArch32) userspace on an affected Cortex-A53
401 part, a load at EL0 from a virtual address that matches the bottom 32
402 bits of the virtual address used by a recent load at (AArch64) EL1
403 might return incorrect data.
405 The workaround is to write the contextidr_el1 register on exception
406 return to a 32-bit task.
407 Please note that this does not necessarily enable the workaround,
408 as it depends on the alternative framework, which will only patch
409 the kernel if an affected CPU is detected.
413 config ARM64_ERRATUM_843419
414 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
417 select ARM64_MODULE_CMODEL_LARGE
419 This option builds kernel modules using the large memory model in
420 order to avoid the use of the ADRP instruction, which can cause
421 a subsequent memory access to use an incorrect address on Cortex-A53
424 Note that the kernel itself must be linked with a version of ld
425 which fixes potentially affected ADRP instructions through the
430 config CAVIUM_ERRATUM_22375
431 bool "Cavium erratum 22375, 24313"
434 Enable workaround for erratum 22375, 24313.
436 This implements two gicv3-its errata workarounds for ThunderX. Both
437 with small impact affecting only ITS table allocation.
439 erratum 22375: only alloc 8MB table size
440 erratum 24313: ignore memory access type
442 The fixes are in ITS initialization and basically ignore memory access
443 type and table size provided by the TYPER and BASER registers.
447 config CAVIUM_ERRATUM_23144
448 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
452 ITS SYNC command hang for cross node io and collections/cpu mapping.
456 config CAVIUM_ERRATUM_23154
457 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
460 The gicv3 of ThunderX requires a modified version for
461 reading the IAR status to ensure data synchronization
462 (access to icc_iar1_el1 is not sync'ed before and after).
466 config CAVIUM_ERRATUM_27456
467 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
470 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
471 instructions may cause the icache to become corrupted if it
472 contains data for a non-current ASID. The fix is to
473 invalidate the icache when changing the mm context.
482 default ARM64_4K_PAGES
484 Page size (translation granule) configuration.
486 config ARM64_4K_PAGES
489 This feature enables 4KB pages support.
491 config ARM64_16K_PAGES
494 The system will use 16KB pages support. AArch32 emulation
495 requires applications compiled with 16K (or a multiple of 16K)
498 config ARM64_64K_PAGES
501 This feature enables 64KB pages support (4KB by default)
502 allowing only two levels of page tables and faster TLB
503 look-up. AArch32 emulation requires applications compiled
504 with 64K aligned segments.
509 prompt "Virtual address space size"
510 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
511 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
512 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
514 Allows choosing one of multiple possible virtual address
515 space sizes. The level of translation table is determined by
516 a combination of page size and virtual address space size.
518 config ARM64_VA_BITS_36
519 bool "36-bit" if EXPERT
520 depends on ARM64_16K_PAGES
522 config ARM64_VA_BITS_39
524 depends on ARM64_4K_PAGES
526 config ARM64_VA_BITS_42
528 depends on ARM64_64K_PAGES
530 config ARM64_VA_BITS_47
532 depends on ARM64_16K_PAGES
534 config ARM64_VA_BITS_48
541 default 36 if ARM64_VA_BITS_36
542 default 39 if ARM64_VA_BITS_39
543 default 42 if ARM64_VA_BITS_42
544 default 47 if ARM64_VA_BITS_47
545 default 48 if ARM64_VA_BITS_48
547 config CPU_BIG_ENDIAN
548 bool "Build big-endian kernel"
550 Say Y if you plan on running a kernel in big-endian mode.
553 bool "Multi-core scheduler support"
555 Multi-core scheduler support improves the CPU scheduler's decision
556 making when dealing with multi-core CPU chips at a cost of slightly
557 increased overhead in some places. If unsure say N here.
560 bool "SMT scheduler support"
562 Improves the CPU scheduler's decision making when dealing with
563 MultiThreading at a cost of slightly increased overhead in some
564 places. If unsure say N here.
567 int "Maximum number of CPUs (2-4096)"
569 # These have to remain sorted largest to smallest
573 bool "Support for hot-pluggable CPUs"
574 select GENERIC_IRQ_MIGRATION
576 Say Y here to experiment with turning CPUs off and on. CPUs
577 can be controlled through /sys/devices/system/cpu.
579 # Common NUMA Features
581 bool "Numa Memory Allocation and Scheduler Support"
584 Enable NUMA (Non Uniform Memory Access) support.
586 The kernel will try to allocate memory used by a CPU on the
587 local memory of the CPU and add some more
588 NUMA awareness to the kernel.
591 int "Maximum NUMA Nodes (as a power of 2)"
594 depends on NEED_MULTIPLE_NODES
596 Specify the maximum number of NUMA Nodes available on the target
597 system. Increases memory reserved to accommodate various tables.
599 config USE_PERCPU_NUMA_NODE_ID
603 source kernel/Kconfig.preempt
604 source kernel/Kconfig.hz
606 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
607 depends on !HIBERNATION
610 config ARCH_HAS_HOLES_MEMORYMODEL
611 def_bool y if SPARSEMEM
613 config ARCH_SPARSEMEM_ENABLE
615 select SPARSEMEM_VMEMMAP_ENABLE
617 config ARCH_SPARSEMEM_DEFAULT
618 def_bool ARCH_SPARSEMEM_ENABLE
620 config ARCH_SELECT_MEMORY_MODEL
621 def_bool ARCH_SPARSEMEM_ENABLE
623 config HAVE_ARCH_PFN_VALID
624 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
626 config HW_PERF_EVENTS
630 config SYS_SUPPORTS_HUGETLBFS
633 config ARCH_WANT_HUGE_PMD_SHARE
634 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
636 config ARCH_HAS_CACHE_LINE_SIZE
642 bool "Enable seccomp to safely compute untrusted bytecode"
644 This kernel feature is useful for number crunching applications
645 that may need to compute untrusted bytecode during their
646 execution. By using pipes or other transports made available to
647 the process as file descriptors supporting the read/write
648 syscalls, it's possible to isolate those applications in
649 their own address space using seccomp. Once seccomp is
650 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
651 and the task is only allowed to execute a few safe syscalls
652 defined by each seccomp mode.
655 bool "Enable paravirtualization code"
657 This changes the kernel so it can modify itself when it is run
658 under a hypervisor, potentially improving performance significantly
659 over full virtualization.
661 config PARAVIRT_TIME_ACCOUNTING
662 bool "Paravirtual steal time accounting"
666 Select this option to enable fine granularity task steal time
667 accounting. Time spent executing other tasks in parallel with
668 the current vCPU is discounted from the vCPU power. To account for
669 that, there can be a small performance impact.
671 If in doubt, say N here.
674 depends on PM_SLEEP_SMP
676 bool "kexec system call"
678 kexec is a system call that implements the ability to shutdown your
679 current kernel, and to start another kernel. It is like a reboot
680 but it is independent of the system firmware. And like a reboot
681 you can start any kernel with it, not just Linux.
688 bool "Xen guest support on ARM64"
689 depends on ARM64 && OF
693 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
695 config FORCE_MAX_ZONEORDER
697 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
698 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
701 The kernel memory allocator divides physically contiguous memory
702 blocks into "zones", where each zone is a power of two number of
703 pages. This option selects the largest power of two that the kernel
704 keeps in the memory allocator. If you need to allocate very large
705 blocks of physically contiguous memory, then you may need to
708 This config option is actually maximum order plus one. For example,
709 a value of 11 means that the largest free memory block is 2^10 pages.
711 We make sure that we can allocate upto a HugePage size for each configuration.
713 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
715 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
716 4M allocations matching the default size used by generic code.
718 menuconfig ARMV8_DEPRECATED
719 bool "Emulate deprecated/obsolete ARMv8 instructions"
722 Legacy software support may require certain instructions
723 that have been deprecated or obsoleted in the architecture.
725 Enable this config to enable selective emulation of these
733 bool "Emulate SWP/SWPB instructions"
735 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
736 they are always undefined. Say Y here to enable software
737 emulation of these instructions for userspace using LDXR/STXR.
739 In some older versions of glibc [<=2.8] SWP is used during futex
740 trylock() operations with the assumption that the code will not
741 be preempted. This invalid assumption may be more likely to fail
742 with SWP emulation enabled, leading to deadlock of the user
745 NOTE: when accessing uncached shared regions, LDXR/STXR rely
746 on an external transaction monitoring block called a global
747 monitor to maintain update atomicity. If your system does not
748 implement a global monitor, this option can cause programs that
749 perform SWP operations to uncached memory to deadlock.
753 config CP15_BARRIER_EMULATION
754 bool "Emulate CP15 Barrier instructions"
756 The CP15 barrier instructions - CP15ISB, CP15DSB, and
757 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
758 strongly recommended to use the ISB, DSB, and DMB
759 instructions instead.
761 Say Y here to enable software emulation of these
762 instructions for AArch32 userspace code. When this option is
763 enabled, CP15 barrier usage is traced which can help
764 identify software that needs updating.
768 config SETEND_EMULATION
769 bool "Emulate SETEND instruction"
771 The SETEND instruction alters the data-endianness of the
772 AArch32 EL0, and is deprecated in ARMv8.
774 Say Y here to enable software emulation of the instruction
775 for AArch32 userspace code.
777 Note: All the cpus on the system must have mixed endian support at EL0
778 for this feature to be enabled. If a new CPU - which doesn't support mixed
779 endian - is hotplugged in after this feature has been enabled, there could
780 be unexpected results in the applications.
785 menu "ARMv8.1 architectural features"
787 config ARM64_HW_AFDBM
788 bool "Support for hardware updates of the Access and Dirty page flags"
791 The ARMv8.1 architecture extensions introduce support for
792 hardware updates of the access and dirty information in page
793 table entries. When enabled in TCR_EL1 (HA and HD bits) on
794 capable processors, accesses to pages with PTE_AF cleared will
795 set this bit instead of raising an access flag fault.
796 Similarly, writes to read-only pages with the DBM bit set will
797 clear the read-only bit (AP[2]) instead of raising a
800 Kernels built with this configuration option enabled continue
801 to work on pre-ARMv8.1 hardware and the performance impact is
802 minimal. If unsure, say Y.
805 bool "Enable support for Privileged Access Never (PAN)"
808 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
809 prevents the kernel or hypervisor from accessing user-space (EL0)
812 Choosing this option will cause any unprotected (not using
813 copy_to_user et al) memory access to fail with a permission fault.
815 The feature is detected at runtime, and will remain as a 'nop'
816 instruction if the cpu does not implement the feature.
818 config ARM64_LSE_ATOMICS
819 bool "Atomic instructions"
821 As part of the Large System Extensions, ARMv8.1 introduces new
822 atomic instructions that are designed specifically to scale in
825 Say Y here to make use of these instructions for the in-kernel
826 atomic routines. This incurs a small overhead on CPUs that do
827 not support these instructions and requires the kernel to be
828 built with binutils >= 2.25.
831 bool "Enable support for Virtualization Host Extensions (VHE)"
834 Virtualization Host Extensions (VHE) allow the kernel to run
835 directly at EL2 (instead of EL1) on processors that support
836 it. This leads to better performance for KVM, as they reduce
837 the cost of the world switch.
839 Selecting this option allows the VHE feature to be detected
840 at runtime, and does not affect processors that do not
841 implement this feature.
845 menu "ARMv8.2 architectural features"
848 bool "Enable support for User Access Override (UAO)"
851 User Access Override (UAO; part of the ARMv8.2 Extensions)
852 causes the 'unprivileged' variant of the load/store instructions to
853 be overriden to be privileged.
855 This option changes get_user() and friends to use the 'unprivileged'
856 variant of the load/store instructions. This ensures that user-space
857 really did have access to the supplied memory. When addr_limit is
858 set to kernel memory the UAO bit will be set, allowing privileged
859 access to kernel memory.
861 Choosing this option will cause copy_to_user() et al to use user-space
864 The feature is detected at runtime, the kernel will use the
865 regular load/store instructions if the cpu does not implement the
870 config ARM64_MODULE_CMODEL_LARGE
873 config ARM64_MODULE_PLTS
875 select ARM64_MODULE_CMODEL_LARGE
876 select HAVE_MOD_ARCH_SPECIFIC
881 This builds the kernel as a Position Independent Executable (PIE),
882 which retains all relocation metadata required to relocate the
883 kernel binary at runtime to a different virtual address than the
884 address it was linked at.
885 Since AArch64 uses the RELA relocation format, this requires a
886 relocation pass at runtime even if the kernel is loaded at the
887 same address it was linked at.
889 config RANDOMIZE_BASE
890 bool "Randomize the address of the kernel image"
891 select ARM64_MODULE_PLTS if MODULES
894 Randomizes the virtual address at which the kernel image is
895 loaded, as a security feature that deters exploit attempts
896 relying on knowledge of the location of kernel internals.
898 It is the bootloader's job to provide entropy, by passing a
899 random u64 value in /chosen/kaslr-seed at kernel entry.
901 When booting via the UEFI stub, it will invoke the firmware's
902 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
903 to the kernel proper. In addition, it will randomise the physical
904 location of the kernel Image as well.
908 config RANDOMIZE_MODULE_REGION_FULL
909 bool "Randomize the module region independently from the core kernel"
910 depends on RANDOMIZE_BASE
913 Randomizes the location of the module region without considering the
914 location of the core kernel. This way, it is impossible for modules
915 to leak information about the location of core kernel data structures
916 but it does imply that function calls between modules and the core
917 kernel will need to be resolved via veneers in the module PLT.
919 When this option is not set, the module region will be randomized over
920 a limited range that contains the [_stext, _etext] interval of the
921 core kernel, so branch relocations are always in range.
927 config ARM64_ACPI_PARKING_PROTOCOL
928 bool "Enable support for the ARM64 ACPI parking protocol"
931 Enable support for the ARM64 ACPI parking protocol. If disabled
932 the kernel will not allow booting through the ARM64 ACPI parking
933 protocol even if the corresponding data is present in the ACPI
937 string "Default kernel command string"
940 Provide a set of default command-line options at build time by
941 entering them here. As a minimum, you should specify the the
942 root device (e.g. root=/dev/nfs).
945 bool "Always use the default kernel command string"
947 Always use the default kernel command string, even if the boot
948 loader passes other arguments to the kernel.
949 This is useful if you cannot or don't want to change the
950 command-line options your boot loader passes to the kernel.
956 bool "UEFI runtime support"
957 depends on OF && !CPU_BIG_ENDIAN
960 select EFI_PARAMS_FROM_FDT
961 select EFI_RUNTIME_WRAPPERS
966 This option provides support for runtime services provided
967 by UEFI firmware (such as non-volatile variables, realtime
968 clock, and platform reset). A UEFI stub is also provided to
969 allow the kernel to be booted as an EFI application. This
970 is only useful on systems that have UEFI firmware.
973 bool "Enable support for SMBIOS (DMI) tables"
977 This enables SMBIOS/DMI feature for systems.
979 This option is only useful on systems that have UEFI firmware.
980 However, even with this option, the resultant kernel should
981 continue to boot on existing non-UEFI platforms.
985 menu "Userspace binary formats"
987 source "fs/Kconfig.binfmt"
990 bool "Kernel support for 32-bit EL0"
991 depends on ARM64_4K_PAGES || EXPERT
992 select COMPAT_BINFMT_ELF
994 select OLD_SIGSUSPEND3
995 select COMPAT_OLD_SIGACTION
997 This option enables support for a 32-bit EL0 running under a 64-bit
998 kernel at EL1. AArch32-specific components such as system calls,
999 the user helper functions, VFP support and the ptrace interface are
1000 handled appropriately by the kernel.
1002 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1003 that you will only be able to execute AArch32 binaries that were compiled
1004 with page size aligned segments.
1006 If you want to execute 32-bit userspace applications, say Y.
1008 config SYSVIPC_COMPAT
1010 depends on COMPAT && SYSVIPC
1014 menu "Power management options"
1016 source "kernel/power/Kconfig"
1018 config ARCH_HIBERNATION_POSSIBLE
1022 config ARCH_HIBERNATION_HEADER
1024 depends on HIBERNATION
1026 config ARCH_SUSPEND_POSSIBLE
1031 menu "CPU Power Management"
1033 source "drivers/cpuidle/Kconfig"
1035 source "drivers/cpufreq/Kconfig"
1039 source "net/Kconfig"
1041 source "drivers/Kconfig"
1043 source "drivers/firmware/Kconfig"
1045 source "drivers/acpi/Kconfig"
1049 source "arch/arm64/kvm/Kconfig"
1051 source "arch/arm64/Kconfig.debug"
1053 source "security/Kconfig"
1055 source "crypto/Kconfig"
1057 source "arch/arm64/crypto/Kconfig"
1060 source "lib/Kconfig"