3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ACPI_SPCR_TABLE if ACPI
8 select ARCH_CLOCKSOURCE_DATA
9 select ARCH_HAS_DEBUG_VIRTUAL
10 select ARCH_HAS_DEVMEM_IS_ALLOWED
11 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
12 select ARCH_HAS_ELF_RANDOMIZE
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_HAS_GIGANTIC_PAGE
16 select ARCH_HAS_SET_MEMORY
17 select ARCH_HAS_SG_CHAIN
18 select ARCH_HAS_STRICT_KERNEL_RWX
19 select ARCH_HAS_STRICT_MODULE_RWX
20 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
21 select ARCH_USE_CMPXCHG_LOCKREF
22 select ARCH_SUPPORTS_ATOMIC_RMW
23 select ARCH_SUPPORTS_NUMA_BALANCING
24 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
25 select ARCH_WANT_FRAME_POINTERS
26 select ARCH_HAS_UBSAN_SANITIZE_ALL
30 select AUDIT_ARCH_COMPAT_GENERIC
31 select ARM_GIC_V2M if PCI
33 select ARM_GIC_V3_ITS if PCI
35 select BUILDTIME_EXTABLE_SORT
36 select CLONE_BACKWARDS
38 select CPU_PM if (SUSPEND || CPU_IDLE)
39 select DCACHE_WORD_ACCESS
42 select GENERIC_ALLOCATOR
43 select GENERIC_CLOCKEVENTS
44 select GENERIC_CLOCKEVENTS_BROADCAST
45 select GENERIC_CPU_AUTOPROBE
46 select GENERIC_EARLY_IOREMAP
47 select GENERIC_IDLE_POLL_SETUP
48 select GENERIC_IRQ_PROBE
49 select GENERIC_IRQ_SHOW
50 select GENERIC_IRQ_SHOW_LEVEL
51 select GENERIC_PCI_IOMAP
52 select GENERIC_SCHED_CLOCK
53 select GENERIC_SMP_IDLE_THREAD
54 select GENERIC_STRNCPY_FROM_USER
55 select GENERIC_STRNLEN_USER
56 select GENERIC_TIME_VSYSCALL
57 select HANDLE_DOMAIN_IRQ
58 select HARDIRQS_SW_RESEND
59 select HAVE_ACPI_APEI if (ACPI && EFI)
60 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
61 select HAVE_ARCH_AUDITSYSCALL
62 select HAVE_ARCH_BITREVERSE
63 select HAVE_ARCH_HARDENED_USERCOPY
64 select HAVE_ARCH_HUGE_VMAP
65 select HAVE_ARCH_JUMP_LABEL
66 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
68 select HAVE_ARCH_MMAP_RND_BITS
69 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
70 select HAVE_ARCH_SECCOMP_FILTER
71 select HAVE_ARCH_TRACEHOOK
72 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
75 select HAVE_C_RECORDMCOUNT
76 select HAVE_CC_STACKPROTECTOR
77 select HAVE_CMPXCHG_DOUBLE
78 select HAVE_CMPXCHG_LOCAL
79 select HAVE_CONTEXT_TRACKING
80 select HAVE_DEBUG_BUGVERBOSE
81 select HAVE_DEBUG_KMEMLEAK
82 select HAVE_DMA_API_DEBUG
83 select HAVE_DMA_CONTIGUOUS
84 select HAVE_DYNAMIC_FTRACE
85 select HAVE_EFFICIENT_UNALIGNED_ACCESS
86 select HAVE_FTRACE_MCOUNT_RECORD
87 select HAVE_FUNCTION_TRACER
88 select HAVE_FUNCTION_GRAPH_TRACER
89 select HAVE_GCC_PLUGINS
90 select HAVE_GENERIC_DMA_COHERENT
91 select HAVE_HW_BREAKPOINT if PERF_EVENTS
92 select HAVE_IRQ_TIME_ACCOUNTING
94 select HAVE_MEMBLOCK_NODE_MAP if NUMA
95 select HAVE_PATA_PLATFORM
96 select HAVE_PERF_EVENTS
98 select HAVE_PERF_USER_STACK_DUMP
99 select HAVE_REGS_AND_STACK_ACCESS_API
100 select HAVE_RCU_TABLE_FREE
101 select HAVE_SYSCALL_TRACEPOINTS
103 select HAVE_KRETPROBES
104 select IOMMU_DMA if IOMMU_SUPPORT
106 select IRQ_FORCED_THREADING
107 select MODULES_USE_ELF_RELA
110 select OF_EARLY_FLATTREE
111 select OF_RESERVED_MEM
112 select PCI_ECAM if ACPI
116 select SYSCTL_EXCEPTION_TRACE
117 select THREAD_INFO_IN_TASK
118 select ARCH_HAS_RAW_COPY_USER
120 ARM 64-bit (AArch64) Linux support.
125 config ARCH_PHYS_ADDR_T_64BIT
131 config ARM64_PAGE_SHIFT
133 default 16 if ARM64_64K_PAGES
134 default 14 if ARM64_16K_PAGES
137 config ARM64_CONT_SHIFT
139 default 5 if ARM64_64K_PAGES
140 default 7 if ARM64_16K_PAGES
143 config ARCH_MMAP_RND_BITS_MIN
144 default 14 if ARM64_64K_PAGES
145 default 16 if ARM64_16K_PAGES
148 # max bits determined by the following formula:
149 # VA_BITS - PAGE_SHIFT - 3
150 config ARCH_MMAP_RND_BITS_MAX
151 default 19 if ARM64_VA_BITS=36
152 default 24 if ARM64_VA_BITS=39
153 default 27 if ARM64_VA_BITS=42
154 default 30 if ARM64_VA_BITS=47
155 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
156 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
157 default 33 if ARM64_VA_BITS=48
158 default 14 if ARM64_64K_PAGES
159 default 16 if ARM64_16K_PAGES
162 config ARCH_MMAP_RND_COMPAT_BITS_MIN
163 default 7 if ARM64_64K_PAGES
164 default 9 if ARM64_16K_PAGES
167 config ARCH_MMAP_RND_COMPAT_BITS_MAX
173 config STACKTRACE_SUPPORT
176 config ILLEGAL_POINTER_VALUE
178 default 0xdead000000000000
180 config LOCKDEP_SUPPORT
183 config TRACE_IRQFLAGS_SUPPORT
186 config RWSEM_XCHGADD_ALGORITHM
193 config GENERIC_BUG_RELATIVE_POINTERS
195 depends on GENERIC_BUG
197 config GENERIC_HWEIGHT
203 config GENERIC_CALIBRATE_DELAY
209 config HAVE_GENERIC_RCU_GUP
212 config ARCH_DMA_ADDR_T_64BIT
215 config NEED_DMA_MAP_STATE
218 config NEED_SG_DMA_LENGTH
230 config KERNEL_MODE_NEON
233 config FIX_EARLYCON_MEM
236 config PGTABLE_LEVELS
238 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
239 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
240 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
241 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
242 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
243 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
245 config ARCH_SUPPORTS_UPROBES
248 source "init/Kconfig"
250 source "kernel/Kconfig.freezer"
252 source "arch/arm64/Kconfig.platforms"
259 This feature enables support for PCI bus system. If you say Y
260 here, the kernel will include drivers and infrastructure code
261 to support PCI bus devices.
266 config PCI_DOMAINS_GENERIC
272 source "drivers/pci/Kconfig"
276 menu "Kernel Features"
278 menu "ARM errata workarounds via the alternatives framework"
280 config ARM64_ERRATUM_826319
281 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
284 This option adds an alternative code sequence to work around ARM
285 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
286 AXI master interface and an L2 cache.
288 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
289 and is unable to accept a certain write via this interface, it will
290 not progress on read data presented on the read data channel and the
293 The workaround promotes data cache clean instructions to
294 data cache clean-and-invalidate.
295 Please note that this does not necessarily enable the workaround,
296 as it depends on the alternative framework, which will only patch
297 the kernel if an affected CPU is detected.
301 config ARM64_ERRATUM_827319
302 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
305 This option adds an alternative code sequence to work around ARM
306 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
307 master interface and an L2 cache.
309 Under certain conditions this erratum can cause a clean line eviction
310 to occur at the same time as another transaction to the same address
311 on the AMBA 5 CHI interface, which can cause data corruption if the
312 interconnect reorders the two transactions.
314 The workaround promotes data cache clean instructions to
315 data cache clean-and-invalidate.
316 Please note that this does not necessarily enable the workaround,
317 as it depends on the alternative framework, which will only patch
318 the kernel if an affected CPU is detected.
322 config ARM64_ERRATUM_824069
323 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
326 This option adds an alternative code sequence to work around ARM
327 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
328 to a coherent interconnect.
330 If a Cortex-A53 processor is executing a store or prefetch for
331 write instruction at the same time as a processor in another
332 cluster is executing a cache maintenance operation to the same
333 address, then this erratum might cause a clean cache line to be
334 incorrectly marked as dirty.
336 The workaround promotes data cache clean instructions to
337 data cache clean-and-invalidate.
338 Please note that this option does not necessarily enable the
339 workaround, as it depends on the alternative framework, which will
340 only patch the kernel if an affected CPU is detected.
344 config ARM64_ERRATUM_819472
345 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
348 This option adds an alternative code sequence to work around ARM
349 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
350 present when it is connected to a coherent interconnect.
352 If the processor is executing a load and store exclusive sequence at
353 the same time as a processor in another cluster is executing a cache
354 maintenance operation to the same address, then this erratum might
355 cause data corruption.
357 The workaround promotes data cache clean instructions to
358 data cache clean-and-invalidate.
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
365 config ARM64_ERRATUM_832075
366 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
369 This option adds an alternative code sequence to work around ARM
370 erratum 832075 on Cortex-A57 parts up to r1p2.
372 Affected Cortex-A57 parts might deadlock when exclusive load/store
373 instructions to Write-Back memory are mixed with Device loads.
375 The workaround is to promote device loads to use Load-Acquire
377 Please note that this does not necessarily enable the workaround,
378 as it depends on the alternative framework, which will only patch
379 the kernel if an affected CPU is detected.
383 config ARM64_ERRATUM_834220
384 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
388 This option adds an alternative code sequence to work around ARM
389 erratum 834220 on Cortex-A57 parts up to r1p2.
391 Affected Cortex-A57 parts might report a Stage 2 translation
392 fault as the result of a Stage 1 fault for load crossing a
393 page boundary when there is a permission or device memory
394 alignment fault at Stage 1 and a translation fault at Stage 2.
396 The workaround is to verify that the Stage 1 translation
397 doesn't generate a fault before handling the Stage 2 fault.
398 Please note that this does not necessarily enable the workaround,
399 as it depends on the alternative framework, which will only patch
400 the kernel if an affected CPU is detected.
404 config ARM64_ERRATUM_845719
405 bool "Cortex-A53: 845719: a load might read incorrect data"
409 This option adds an alternative code sequence to work around ARM
410 erratum 845719 on Cortex-A53 parts up to r0p4.
412 When running a compat (AArch32) userspace on an affected Cortex-A53
413 part, a load at EL0 from a virtual address that matches the bottom 32
414 bits of the virtual address used by a recent load at (AArch64) EL1
415 might return incorrect data.
417 The workaround is to write the contextidr_el1 register on exception
418 return to a 32-bit task.
419 Please note that this does not necessarily enable the workaround,
420 as it depends on the alternative framework, which will only patch
421 the kernel if an affected CPU is detected.
425 config ARM64_ERRATUM_843419
426 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
428 select ARM64_MODULE_CMODEL_LARGE if MODULES
430 This option links the kernel with '--fix-cortex-a53-843419' and
431 builds modules using the large memory model in order to avoid the use
432 of the ADRP instruction, which can cause a subsequent memory access
433 to use an incorrect address on Cortex-A53 parts up to r0p4.
437 config CAVIUM_ERRATUM_22375
438 bool "Cavium erratum 22375, 24313"
441 Enable workaround for erratum 22375, 24313.
443 This implements two gicv3-its errata workarounds for ThunderX. Both
444 with small impact affecting only ITS table allocation.
446 erratum 22375: only alloc 8MB table size
447 erratum 24313: ignore memory access type
449 The fixes are in ITS initialization and basically ignore memory access
450 type and table size provided by the TYPER and BASER registers.
454 config CAVIUM_ERRATUM_23144
455 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
459 ITS SYNC command hang for cross node io and collections/cpu mapping.
463 config CAVIUM_ERRATUM_23154
464 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
467 The gicv3 of ThunderX requires a modified version for
468 reading the IAR status to ensure data synchronization
469 (access to icc_iar1_el1 is not sync'ed before and after).
473 config CAVIUM_ERRATUM_27456
474 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
477 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
478 instructions may cause the icache to become corrupted if it
479 contains data for a non-current ASID. The fix is to
480 invalidate the icache when changing the mm context.
484 config QCOM_FALKOR_ERRATUM_1003
485 bool "Falkor E1003: Incorrect translation due to ASID change"
487 select ARM64_PAN if ARM64_SW_TTBR0_PAN
489 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
490 and BADDR are changed together in TTBRx_EL1. The workaround for this
491 issue is to use a reserved ASID in cpu_do_switch_mm() before
492 switching to the new ASID. Saying Y here selects ARM64_PAN if
493 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
494 maintaining the E1003 workaround in the software PAN emulation code
495 would be an unnecessary complication. The affected Falkor v1 CPU
496 implements ARMv8.1 hardware PAN support and using hardware PAN
497 support versus software PAN emulation is mutually exclusive at
502 config QCOM_FALKOR_ERRATUM_1009
503 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
506 On Falkor v1, the CPU may prematurely complete a DSB following a
507 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
508 one more time to fix the issue.
512 config QCOM_QDF2400_ERRATUM_0065
513 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
516 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
517 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
518 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
527 default ARM64_4K_PAGES
529 Page size (translation granule) configuration.
531 config ARM64_4K_PAGES
534 This feature enables 4KB pages support.
536 config ARM64_16K_PAGES
539 The system will use 16KB pages support. AArch32 emulation
540 requires applications compiled with 16K (or a multiple of 16K)
543 config ARM64_64K_PAGES
546 This feature enables 64KB pages support (4KB by default)
547 allowing only two levels of page tables and faster TLB
548 look-up. AArch32 emulation requires applications compiled
549 with 64K aligned segments.
554 prompt "Virtual address space size"
555 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
556 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
557 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
559 Allows choosing one of multiple possible virtual address
560 space sizes. The level of translation table is determined by
561 a combination of page size and virtual address space size.
563 config ARM64_VA_BITS_36
564 bool "36-bit" if EXPERT
565 depends on ARM64_16K_PAGES
567 config ARM64_VA_BITS_39
569 depends on ARM64_4K_PAGES
571 config ARM64_VA_BITS_42
573 depends on ARM64_64K_PAGES
575 config ARM64_VA_BITS_47
577 depends on ARM64_16K_PAGES
579 config ARM64_VA_BITS_48
586 default 36 if ARM64_VA_BITS_36
587 default 39 if ARM64_VA_BITS_39
588 default 42 if ARM64_VA_BITS_42
589 default 47 if ARM64_VA_BITS_47
590 default 48 if ARM64_VA_BITS_48
592 config CPU_BIG_ENDIAN
593 bool "Build big-endian kernel"
595 Say Y if you plan on running a kernel in big-endian mode.
598 bool "Multi-core scheduler support"
600 Multi-core scheduler support improves the CPU scheduler's decision
601 making when dealing with multi-core CPU chips at a cost of slightly
602 increased overhead in some places. If unsure say N here.
605 bool "SMT scheduler support"
607 Improves the CPU scheduler's decision making when dealing with
608 MultiThreading at a cost of slightly increased overhead in some
609 places. If unsure say N here.
612 int "Maximum number of CPUs (2-4096)"
614 # These have to remain sorted largest to smallest
618 bool "Support for hot-pluggable CPUs"
619 select GENERIC_IRQ_MIGRATION
621 Say Y here to experiment with turning CPUs off and on. CPUs
622 can be controlled through /sys/devices/system/cpu.
624 # Common NUMA Features
626 bool "Numa Memory Allocation and Scheduler Support"
627 select ACPI_NUMA if ACPI
630 Enable NUMA (Non Uniform Memory Access) support.
632 The kernel will try to allocate memory used by a CPU on the
633 local memory of the CPU and add some more
634 NUMA awareness to the kernel.
637 int "Maximum NUMA Nodes (as a power of 2)"
640 depends on NEED_MULTIPLE_NODES
642 Specify the maximum number of NUMA Nodes available on the target
643 system. Increases memory reserved to accommodate various tables.
645 config USE_PERCPU_NUMA_NODE_ID
649 config HAVE_SETUP_PER_CPU_AREA
653 config NEED_PER_CPU_EMBED_FIRST_CHUNK
661 source kernel/Kconfig.preempt
662 source kernel/Kconfig.hz
664 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
667 config ARCH_HAS_HOLES_MEMORYMODEL
668 def_bool y if SPARSEMEM
670 config ARCH_SPARSEMEM_ENABLE
672 select SPARSEMEM_VMEMMAP_ENABLE
674 config ARCH_SPARSEMEM_DEFAULT
675 def_bool ARCH_SPARSEMEM_ENABLE
677 config ARCH_SELECT_MEMORY_MODEL
678 def_bool ARCH_SPARSEMEM_ENABLE
680 config HAVE_ARCH_PFN_VALID
681 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
683 config HW_PERF_EVENTS
687 config SYS_SUPPORTS_HUGETLBFS
690 config ARCH_WANT_HUGE_PMD_SHARE
691 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
693 config ARCH_HAS_CACHE_LINE_SIZE
699 bool "Enable seccomp to safely compute untrusted bytecode"
701 This kernel feature is useful for number crunching applications
702 that may need to compute untrusted bytecode during their
703 execution. By using pipes or other transports made available to
704 the process as file descriptors supporting the read/write
705 syscalls, it's possible to isolate those applications in
706 their own address space using seccomp. Once seccomp is
707 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
708 and the task is only allowed to execute a few safe syscalls
709 defined by each seccomp mode.
712 bool "Enable paravirtualization code"
714 This changes the kernel so it can modify itself when it is run
715 under a hypervisor, potentially improving performance significantly
716 over full virtualization.
718 config PARAVIRT_TIME_ACCOUNTING
719 bool "Paravirtual steal time accounting"
723 Select this option to enable fine granularity task steal time
724 accounting. Time spent executing other tasks in parallel with
725 the current vCPU is discounted from the vCPU power. To account for
726 that, there can be a small performance impact.
728 If in doubt, say N here.
731 depends on PM_SLEEP_SMP
733 bool "kexec system call"
735 kexec is a system call that implements the ability to shutdown your
736 current kernel, and to start another kernel. It is like a reboot
737 but it is independent of the system firmware. And like a reboot
738 you can start any kernel with it, not just Linux.
745 bool "Xen guest support on ARM64"
746 depends on ARM64 && OF
750 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
752 config FORCE_MAX_ZONEORDER
754 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
755 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
758 The kernel memory allocator divides physically contiguous memory
759 blocks into "zones", where each zone is a power of two number of
760 pages. This option selects the largest power of two that the kernel
761 keeps in the memory allocator. If you need to allocate very large
762 blocks of physically contiguous memory, then you may need to
765 This config option is actually maximum order plus one. For example,
766 a value of 11 means that the largest free memory block is 2^10 pages.
768 We make sure that we can allocate upto a HugePage size for each configuration.
770 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
772 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
773 4M allocations matching the default size used by generic code.
775 menuconfig ARMV8_DEPRECATED
776 bool "Emulate deprecated/obsolete ARMv8 instructions"
779 Legacy software support may require certain instructions
780 that have been deprecated or obsoleted in the architecture.
782 Enable this config to enable selective emulation of these
790 bool "Emulate SWP/SWPB instructions"
792 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
793 they are always undefined. Say Y here to enable software
794 emulation of these instructions for userspace using LDXR/STXR.
796 In some older versions of glibc [<=2.8] SWP is used during futex
797 trylock() operations with the assumption that the code will not
798 be preempted. This invalid assumption may be more likely to fail
799 with SWP emulation enabled, leading to deadlock of the user
802 NOTE: when accessing uncached shared regions, LDXR/STXR rely
803 on an external transaction monitoring block called a global
804 monitor to maintain update atomicity. If your system does not
805 implement a global monitor, this option can cause programs that
806 perform SWP operations to uncached memory to deadlock.
810 config CP15_BARRIER_EMULATION
811 bool "Emulate CP15 Barrier instructions"
813 The CP15 barrier instructions - CP15ISB, CP15DSB, and
814 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
815 strongly recommended to use the ISB, DSB, and DMB
816 instructions instead.
818 Say Y here to enable software emulation of these
819 instructions for AArch32 userspace code. When this option is
820 enabled, CP15 barrier usage is traced which can help
821 identify software that needs updating.
825 config SETEND_EMULATION
826 bool "Emulate SETEND instruction"
828 The SETEND instruction alters the data-endianness of the
829 AArch32 EL0, and is deprecated in ARMv8.
831 Say Y here to enable software emulation of the instruction
832 for AArch32 userspace code.
834 Note: All the cpus on the system must have mixed endian support at EL0
835 for this feature to be enabled. If a new CPU - which doesn't support mixed
836 endian - is hotplugged in after this feature has been enabled, there could
837 be unexpected results in the applications.
842 config ARM64_SW_TTBR0_PAN
843 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
845 Enabling this option prevents the kernel from accessing
846 user-space memory directly by pointing TTBR0_EL1 to a reserved
847 zeroed area and reserved ASID. The user access routines
848 restore the valid TTBR0_EL1 temporarily.
850 menu "ARMv8.1 architectural features"
852 config ARM64_HW_AFDBM
853 bool "Support for hardware updates of the Access and Dirty page flags"
856 The ARMv8.1 architecture extensions introduce support for
857 hardware updates of the access and dirty information in page
858 table entries. When enabled in TCR_EL1 (HA and HD bits) on
859 capable processors, accesses to pages with PTE_AF cleared will
860 set this bit instead of raising an access flag fault.
861 Similarly, writes to read-only pages with the DBM bit set will
862 clear the read-only bit (AP[2]) instead of raising a
865 Kernels built with this configuration option enabled continue
866 to work on pre-ARMv8.1 hardware and the performance impact is
867 minimal. If unsure, say Y.
870 bool "Enable support for Privileged Access Never (PAN)"
873 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
874 prevents the kernel or hypervisor from accessing user-space (EL0)
877 Choosing this option will cause any unprotected (not using
878 copy_to_user et al) memory access to fail with a permission fault.
880 The feature is detected at runtime, and will remain as a 'nop'
881 instruction if the cpu does not implement the feature.
883 config ARM64_LSE_ATOMICS
884 bool "Atomic instructions"
886 As part of the Large System Extensions, ARMv8.1 introduces new
887 atomic instructions that are designed specifically to scale in
890 Say Y here to make use of these instructions for the in-kernel
891 atomic routines. This incurs a small overhead on CPUs that do
892 not support these instructions and requires the kernel to be
893 built with binutils >= 2.25.
896 bool "Enable support for Virtualization Host Extensions (VHE)"
899 Virtualization Host Extensions (VHE) allow the kernel to run
900 directly at EL2 (instead of EL1) on processors that support
901 it. This leads to better performance for KVM, as they reduce
902 the cost of the world switch.
904 Selecting this option allows the VHE feature to be detected
905 at runtime, and does not affect processors that do not
906 implement this feature.
910 menu "ARMv8.2 architectural features"
913 bool "Enable support for User Access Override (UAO)"
916 User Access Override (UAO; part of the ARMv8.2 Extensions)
917 causes the 'unprivileged' variant of the load/store instructions to
918 be overriden to be privileged.
920 This option changes get_user() and friends to use the 'unprivileged'
921 variant of the load/store instructions. This ensures that user-space
922 really did have access to the supplied memory. When addr_limit is
923 set to kernel memory the UAO bit will be set, allowing privileged
924 access to kernel memory.
926 Choosing this option will cause copy_to_user() et al to use user-space
929 The feature is detected at runtime, the kernel will use the
930 regular load/store instructions if the cpu does not implement the
935 config ARM64_MODULE_CMODEL_LARGE
938 config ARM64_MODULE_PLTS
940 select ARM64_MODULE_CMODEL_LARGE
941 select HAVE_MOD_ARCH_SPECIFIC
946 This builds the kernel as a Position Independent Executable (PIE),
947 which retains all relocation metadata required to relocate the
948 kernel binary at runtime to a different virtual address than the
949 address it was linked at.
950 Since AArch64 uses the RELA relocation format, this requires a
951 relocation pass at runtime even if the kernel is loaded at the
952 same address it was linked at.
954 config RANDOMIZE_BASE
955 bool "Randomize the address of the kernel image"
956 select ARM64_MODULE_PLTS if MODULES
959 Randomizes the virtual address at which the kernel image is
960 loaded, as a security feature that deters exploit attempts
961 relying on knowledge of the location of kernel internals.
963 It is the bootloader's job to provide entropy, by passing a
964 random u64 value in /chosen/kaslr-seed at kernel entry.
966 When booting via the UEFI stub, it will invoke the firmware's
967 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
968 to the kernel proper. In addition, it will randomise the physical
969 location of the kernel Image as well.
973 config RANDOMIZE_MODULE_REGION_FULL
974 bool "Randomize the module region independently from the core kernel"
975 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
978 Randomizes the location of the module region without considering the
979 location of the core kernel. This way, it is impossible for modules
980 to leak information about the location of core kernel data structures
981 but it does imply that function calls between modules and the core
982 kernel will need to be resolved via veneers in the module PLT.
984 When this option is not set, the module region will be randomized over
985 a limited range that contains the [_stext, _etext] interval of the
986 core kernel, so branch relocations are always in range.
992 config ARM64_ACPI_PARKING_PROTOCOL
993 bool "Enable support for the ARM64 ACPI parking protocol"
996 Enable support for the ARM64 ACPI parking protocol. If disabled
997 the kernel will not allow booting through the ARM64 ACPI parking
998 protocol even if the corresponding data is present in the ACPI
1002 string "Default kernel command string"
1005 Provide a set of default command-line options at build time by
1006 entering them here. As a minimum, you should specify the the
1007 root device (e.g. root=/dev/nfs).
1009 config CMDLINE_FORCE
1010 bool "Always use the default kernel command string"
1012 Always use the default kernel command string, even if the boot
1013 loader passes other arguments to the kernel.
1014 This is useful if you cannot or don't want to change the
1015 command-line options your boot loader passes to the kernel.
1021 bool "UEFI runtime support"
1022 depends on OF && !CPU_BIG_ENDIAN
1025 select EFI_PARAMS_FROM_FDT
1026 select EFI_RUNTIME_WRAPPERS
1031 This option provides support for runtime services provided
1032 by UEFI firmware (such as non-volatile variables, realtime
1033 clock, and platform reset). A UEFI stub is also provided to
1034 allow the kernel to be booted as an EFI application. This
1035 is only useful on systems that have UEFI firmware.
1038 bool "Enable support for SMBIOS (DMI) tables"
1042 This enables SMBIOS/DMI feature for systems.
1044 This option is only useful on systems that have UEFI firmware.
1045 However, even with this option, the resultant kernel should
1046 continue to boot on existing non-UEFI platforms.
1050 menu "Userspace binary formats"
1052 source "fs/Kconfig.binfmt"
1055 bool "Kernel support for 32-bit EL0"
1056 depends on ARM64_4K_PAGES || EXPERT
1057 select COMPAT_BINFMT_ELF if BINFMT_ELF
1059 select OLD_SIGSUSPEND3
1060 select COMPAT_OLD_SIGACTION
1062 This option enables support for a 32-bit EL0 running under a 64-bit
1063 kernel at EL1. AArch32-specific components such as system calls,
1064 the user helper functions, VFP support and the ptrace interface are
1065 handled appropriately by the kernel.
1067 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1068 that you will only be able to execute AArch32 binaries that were compiled
1069 with page size aligned segments.
1071 If you want to execute 32-bit userspace applications, say Y.
1073 config SYSVIPC_COMPAT
1075 depends on COMPAT && SYSVIPC
1079 depends on COMPAT && KEYS
1083 menu "Power management options"
1085 source "kernel/power/Kconfig"
1087 config ARCH_HIBERNATION_POSSIBLE
1091 config ARCH_HIBERNATION_HEADER
1093 depends on HIBERNATION
1095 config ARCH_SUSPEND_POSSIBLE
1100 menu "CPU Power Management"
1102 source "drivers/cpuidle/Kconfig"
1104 source "drivers/cpufreq/Kconfig"
1108 source "net/Kconfig"
1110 source "drivers/Kconfig"
1112 source "drivers/firmware/Kconfig"
1114 source "drivers/acpi/Kconfig"
1118 source "arch/arm64/kvm/Kconfig"
1120 source "arch/arm64/Kconfig.debug"
1122 source "security/Kconfig"
1124 source "crypto/Kconfig"
1126 source "arch/arm64/crypto/Kconfig"
1129 source "lib/Kconfig"