3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ACPI_SPCR_TABLE if ACPI
8 select ARCH_CLOCKSOURCE_DATA
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_GCOV_PROFILE_ALL
13 select ARCH_HAS_GIGANTIC_PAGE
15 select ARCH_HAS_SG_CHAIN
16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
17 select ARCH_USE_CMPXCHG_LOCKREF
18 select ARCH_SUPPORTS_ATOMIC_RMW
19 select ARCH_SUPPORTS_NUMA_BALANCING
20 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
21 select ARCH_WANT_FRAME_POINTERS
22 select ARCH_HAS_UBSAN_SANITIZE_ALL
26 select AUDIT_ARCH_COMPAT_GENERIC
27 select ARM_GIC_V2M if PCI
29 select ARM_GIC_V3_ITS if PCI
31 select BUILDTIME_EXTABLE_SORT
32 select CLONE_BACKWARDS
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select DCACHE_WORD_ACCESS
38 select GENERIC_ALLOCATOR
39 select GENERIC_CLOCKEVENTS
40 select GENERIC_CLOCKEVENTS_BROADCAST
41 select GENERIC_CPU_AUTOPROBE
42 select GENERIC_EARLY_IOREMAP
43 select GENERIC_IDLE_POLL_SETUP
44 select GENERIC_IRQ_PROBE
45 select GENERIC_IRQ_SHOW
46 select GENERIC_IRQ_SHOW_LEVEL
47 select GENERIC_PCI_IOMAP
48 select GENERIC_SCHED_CLOCK
49 select GENERIC_SMP_IDLE_THREAD
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select GENERIC_TIME_VSYSCALL
53 select HANDLE_DOMAIN_IRQ
54 select HARDIRQS_SW_RESEND
55 select HAVE_ACPI_APEI if (ACPI && EFI)
56 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
57 select HAVE_ARCH_AUDITSYSCALL
58 select HAVE_ARCH_BITREVERSE
59 select HAVE_ARCH_HARDENED_USERCOPY
60 select HAVE_ARCH_HUGE_VMAP
61 select HAVE_ARCH_JUMP_LABEL
62 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
64 select HAVE_ARCH_MMAP_RND_BITS
65 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
66 select HAVE_ARCH_SECCOMP_FILTER
67 select HAVE_ARCH_TRACEHOOK
68 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
71 select HAVE_C_RECORDMCOUNT
72 select HAVE_CC_STACKPROTECTOR
73 select HAVE_CMPXCHG_DOUBLE
74 select HAVE_CMPXCHG_LOCAL
75 select HAVE_CONTEXT_TRACKING
76 select HAVE_DEBUG_BUGVERBOSE
77 select HAVE_DEBUG_KMEMLEAK
78 select HAVE_DMA_API_DEBUG
79 select HAVE_DMA_CONTIGUOUS
80 select HAVE_DYNAMIC_FTRACE
81 select HAVE_EFFICIENT_UNALIGNED_ACCESS
82 select HAVE_FTRACE_MCOUNT_RECORD
83 select HAVE_FUNCTION_TRACER
84 select HAVE_FUNCTION_GRAPH_TRACER
85 select HAVE_GCC_PLUGINS
86 select HAVE_GENERIC_DMA_COHERENT
87 select HAVE_HW_BREAKPOINT if PERF_EVENTS
88 select HAVE_IRQ_TIME_ACCOUNTING
90 select HAVE_MEMBLOCK_NODE_MAP if NUMA
91 select HAVE_PATA_PLATFORM
92 select HAVE_PERF_EVENTS
94 select HAVE_PERF_USER_STACK_DUMP
95 select HAVE_REGS_AND_STACK_ACCESS_API
96 select HAVE_RCU_TABLE_FREE
97 select HAVE_SYSCALL_TRACEPOINTS
99 select HAVE_KRETPROBES if HAVE_KPROBES
100 select IOMMU_DMA if IOMMU_SUPPORT
102 select IRQ_FORCED_THREADING
103 select MODULES_USE_ELF_RELA
106 select OF_EARLY_FLATTREE
107 select OF_RESERVED_MEM
108 select PCI_ECAM if ACPI
112 select SYSCTL_EXCEPTION_TRACE
114 ARM 64-bit (AArch64) Linux support.
119 config ARCH_PHYS_ADDR_T_64BIT
128 config ARM64_PAGE_SHIFT
130 default 16 if ARM64_64K_PAGES
131 default 14 if ARM64_16K_PAGES
134 config ARM64_CONT_SHIFT
136 default 5 if ARM64_64K_PAGES
137 default 7 if ARM64_16K_PAGES
140 config ARCH_MMAP_RND_BITS_MIN
141 default 14 if ARM64_64K_PAGES
142 default 16 if ARM64_16K_PAGES
145 # max bits determined by the following formula:
146 # VA_BITS - PAGE_SHIFT - 3
147 config ARCH_MMAP_RND_BITS_MAX
148 default 19 if ARM64_VA_BITS=36
149 default 24 if ARM64_VA_BITS=39
150 default 27 if ARM64_VA_BITS=42
151 default 30 if ARM64_VA_BITS=47
152 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
153 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
154 default 33 if ARM64_VA_BITS=48
155 default 14 if ARM64_64K_PAGES
156 default 16 if ARM64_16K_PAGES
159 config ARCH_MMAP_RND_COMPAT_BITS_MIN
160 default 7 if ARM64_64K_PAGES
161 default 9 if ARM64_16K_PAGES
164 config ARCH_MMAP_RND_COMPAT_BITS_MAX
170 config STACKTRACE_SUPPORT
173 config ILLEGAL_POINTER_VALUE
175 default 0xdead000000000000
177 config LOCKDEP_SUPPORT
180 config TRACE_IRQFLAGS_SUPPORT
183 config RWSEM_XCHGADD_ALGORITHM
190 config GENERIC_BUG_RELATIVE_POINTERS
192 depends on GENERIC_BUG
194 config GENERIC_HWEIGHT
200 config GENERIC_CALIBRATE_DELAY
206 config HAVE_GENERIC_RCU_GUP
209 config ARCH_DMA_ADDR_T_64BIT
212 config NEED_DMA_MAP_STATE
215 config NEED_SG_DMA_LENGTH
227 config KERNEL_MODE_NEON
230 config FIX_EARLYCON_MEM
233 config PGTABLE_LEVELS
235 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
236 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
237 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
238 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
239 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
240 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
242 source "init/Kconfig"
244 source "kernel/Kconfig.freezer"
246 source "arch/arm64/Kconfig.platforms"
253 This feature enables support for PCI bus system. If you say Y
254 here, the kernel will include drivers and infrastructure code
255 to support PCI bus devices.
260 config PCI_DOMAINS_GENERIC
266 source "drivers/pci/Kconfig"
270 menu "Kernel Features"
272 menu "ARM errata workarounds via the alternatives framework"
274 config ARM64_ERRATUM_826319
275 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
278 This option adds an alternative code sequence to work around ARM
279 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
280 AXI master interface and an L2 cache.
282 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
283 and is unable to accept a certain write via this interface, it will
284 not progress on read data presented on the read data channel and the
287 The workaround promotes data cache clean instructions to
288 data cache clean-and-invalidate.
289 Please note that this does not necessarily enable the workaround,
290 as it depends on the alternative framework, which will only patch
291 the kernel if an affected CPU is detected.
295 config ARM64_ERRATUM_827319
296 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
299 This option adds an alternative code sequence to work around ARM
300 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
301 master interface and an L2 cache.
303 Under certain conditions this erratum can cause a clean line eviction
304 to occur at the same time as another transaction to the same address
305 on the AMBA 5 CHI interface, which can cause data corruption if the
306 interconnect reorders the two transactions.
308 The workaround promotes data cache clean instructions to
309 data cache clean-and-invalidate.
310 Please note that this does not necessarily enable the workaround,
311 as it depends on the alternative framework, which will only patch
312 the kernel if an affected CPU is detected.
316 config ARM64_ERRATUM_824069
317 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
320 This option adds an alternative code sequence to work around ARM
321 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
322 to a coherent interconnect.
324 If a Cortex-A53 processor is executing a store or prefetch for
325 write instruction at the same time as a processor in another
326 cluster is executing a cache maintenance operation to the same
327 address, then this erratum might cause a clean cache line to be
328 incorrectly marked as dirty.
330 The workaround promotes data cache clean instructions to
331 data cache clean-and-invalidate.
332 Please note that this option does not necessarily enable the
333 workaround, as it depends on the alternative framework, which will
334 only patch the kernel if an affected CPU is detected.
338 config ARM64_ERRATUM_819472
339 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
342 This option adds an alternative code sequence to work around ARM
343 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
344 present when it is connected to a coherent interconnect.
346 If the processor is executing a load and store exclusive sequence at
347 the same time as a processor in another cluster is executing a cache
348 maintenance operation to the same address, then this erratum might
349 cause data corruption.
351 The workaround promotes data cache clean instructions to
352 data cache clean-and-invalidate.
353 Please note that this does not necessarily enable the workaround,
354 as it depends on the alternative framework, which will only patch
355 the kernel if an affected CPU is detected.
359 config ARM64_ERRATUM_832075
360 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
363 This option adds an alternative code sequence to work around ARM
364 erratum 832075 on Cortex-A57 parts up to r1p2.
366 Affected Cortex-A57 parts might deadlock when exclusive load/store
367 instructions to Write-Back memory are mixed with Device loads.
369 The workaround is to promote device loads to use Load-Acquire
371 Please note that this does not necessarily enable the workaround,
372 as it depends on the alternative framework, which will only patch
373 the kernel if an affected CPU is detected.
377 config ARM64_ERRATUM_834220
378 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
382 This option adds an alternative code sequence to work around ARM
383 erratum 834220 on Cortex-A57 parts up to r1p2.
385 Affected Cortex-A57 parts might report a Stage 2 translation
386 fault as the result of a Stage 1 fault for load crossing a
387 page boundary when there is a permission or device memory
388 alignment fault at Stage 1 and a translation fault at Stage 2.
390 The workaround is to verify that the Stage 1 translation
391 doesn't generate a fault before handling the Stage 2 fault.
392 Please note that this does not necessarily enable the workaround,
393 as it depends on the alternative framework, which will only patch
394 the kernel if an affected CPU is detected.
398 config ARM64_ERRATUM_845719
399 bool "Cortex-A53: 845719: a load might read incorrect data"
403 This option adds an alternative code sequence to work around ARM
404 erratum 845719 on Cortex-A53 parts up to r0p4.
406 When running a compat (AArch32) userspace on an affected Cortex-A53
407 part, a load at EL0 from a virtual address that matches the bottom 32
408 bits of the virtual address used by a recent load at (AArch64) EL1
409 might return incorrect data.
411 The workaround is to write the contextidr_el1 register on exception
412 return to a 32-bit task.
413 Please note that this does not necessarily enable the workaround,
414 as it depends on the alternative framework, which will only patch
415 the kernel if an affected CPU is detected.
419 config ARM64_ERRATUM_843419
420 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
422 select ARM64_MODULE_CMODEL_LARGE if MODULES
424 This option links the kernel with '--fix-cortex-a53-843419' and
425 builds modules using the large memory model in order to avoid the use
426 of the ADRP instruction, which can cause a subsequent memory access
427 to use an incorrect address on Cortex-A53 parts up to r0p4.
431 config CAVIUM_ERRATUM_22375
432 bool "Cavium erratum 22375, 24313"
435 Enable workaround for erratum 22375, 24313.
437 This implements two gicv3-its errata workarounds for ThunderX. Both
438 with small impact affecting only ITS table allocation.
440 erratum 22375: only alloc 8MB table size
441 erratum 24313: ignore memory access type
443 The fixes are in ITS initialization and basically ignore memory access
444 type and table size provided by the TYPER and BASER registers.
448 config CAVIUM_ERRATUM_23144
449 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
453 ITS SYNC command hang for cross node io and collections/cpu mapping.
457 config CAVIUM_ERRATUM_23154
458 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
461 The gicv3 of ThunderX requires a modified version for
462 reading the IAR status to ensure data synchronization
463 (access to icc_iar1_el1 is not sync'ed before and after).
467 config CAVIUM_ERRATUM_27456
468 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
471 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
472 instructions may cause the icache to become corrupted if it
473 contains data for a non-current ASID. The fix is to
474 invalidate the icache when changing the mm context.
483 default ARM64_4K_PAGES
485 Page size (translation granule) configuration.
487 config ARM64_4K_PAGES
490 This feature enables 4KB pages support.
492 config ARM64_16K_PAGES
495 The system will use 16KB pages support. AArch32 emulation
496 requires applications compiled with 16K (or a multiple of 16K)
499 config ARM64_64K_PAGES
502 This feature enables 64KB pages support (4KB by default)
503 allowing only two levels of page tables and faster TLB
504 look-up. AArch32 emulation requires applications compiled
505 with 64K aligned segments.
510 prompt "Virtual address space size"
511 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
512 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
513 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
515 Allows choosing one of multiple possible virtual address
516 space sizes. The level of translation table is determined by
517 a combination of page size and virtual address space size.
519 config ARM64_VA_BITS_36
520 bool "36-bit" if EXPERT
521 depends on ARM64_16K_PAGES
523 config ARM64_VA_BITS_39
525 depends on ARM64_4K_PAGES
527 config ARM64_VA_BITS_42
529 depends on ARM64_64K_PAGES
531 config ARM64_VA_BITS_47
533 depends on ARM64_16K_PAGES
535 config ARM64_VA_BITS_48
542 default 36 if ARM64_VA_BITS_36
543 default 39 if ARM64_VA_BITS_39
544 default 42 if ARM64_VA_BITS_42
545 default 47 if ARM64_VA_BITS_47
546 default 48 if ARM64_VA_BITS_48
548 config CPU_BIG_ENDIAN
549 bool "Build big-endian kernel"
551 Say Y if you plan on running a kernel in big-endian mode.
554 bool "Multi-core scheduler support"
556 Multi-core scheduler support improves the CPU scheduler's decision
557 making when dealing with multi-core CPU chips at a cost of slightly
558 increased overhead in some places. If unsure say N here.
561 bool "SMT scheduler support"
563 Improves the CPU scheduler's decision making when dealing with
564 MultiThreading at a cost of slightly increased overhead in some
565 places. If unsure say N here.
568 int "Maximum number of CPUs (2-4096)"
570 # These have to remain sorted largest to smallest
574 bool "Support for hot-pluggable CPUs"
575 select GENERIC_IRQ_MIGRATION
577 Say Y here to experiment with turning CPUs off and on. CPUs
578 can be controlled through /sys/devices/system/cpu.
580 # Common NUMA Features
582 bool "Numa Memory Allocation and Scheduler Support"
583 select ACPI_NUMA if ACPI
586 Enable NUMA (Non Uniform Memory Access) support.
588 The kernel will try to allocate memory used by a CPU on the
589 local memory of the CPU and add some more
590 NUMA awareness to the kernel.
593 int "Maximum NUMA Nodes (as a power of 2)"
596 depends on NEED_MULTIPLE_NODES
598 Specify the maximum number of NUMA Nodes available on the target
599 system. Increases memory reserved to accommodate various tables.
601 config USE_PERCPU_NUMA_NODE_ID
605 config HAVE_SETUP_PER_CPU_AREA
609 config NEED_PER_CPU_EMBED_FIRST_CHUNK
613 source kernel/Kconfig.preempt
614 source kernel/Kconfig.hz
616 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
619 config ARCH_HAS_HOLES_MEMORYMODEL
620 def_bool y if SPARSEMEM
622 config ARCH_SPARSEMEM_ENABLE
624 select SPARSEMEM_VMEMMAP_ENABLE
626 config ARCH_SPARSEMEM_DEFAULT
627 def_bool ARCH_SPARSEMEM_ENABLE
629 config ARCH_SELECT_MEMORY_MODEL
630 def_bool ARCH_SPARSEMEM_ENABLE
632 config HAVE_ARCH_PFN_VALID
633 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
635 config HW_PERF_EVENTS
639 config SYS_SUPPORTS_HUGETLBFS
642 config ARCH_WANT_HUGE_PMD_SHARE
643 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
645 config ARCH_HAS_CACHE_LINE_SIZE
651 bool "Enable seccomp to safely compute untrusted bytecode"
653 This kernel feature is useful for number crunching applications
654 that may need to compute untrusted bytecode during their
655 execution. By using pipes or other transports made available to
656 the process as file descriptors supporting the read/write
657 syscalls, it's possible to isolate those applications in
658 their own address space using seccomp. Once seccomp is
659 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
660 and the task is only allowed to execute a few safe syscalls
661 defined by each seccomp mode.
664 bool "Enable paravirtualization code"
666 This changes the kernel so it can modify itself when it is run
667 under a hypervisor, potentially improving performance significantly
668 over full virtualization.
670 config PARAVIRT_TIME_ACCOUNTING
671 bool "Paravirtual steal time accounting"
675 Select this option to enable fine granularity task steal time
676 accounting. Time spent executing other tasks in parallel with
677 the current vCPU is discounted from the vCPU power. To account for
678 that, there can be a small performance impact.
680 If in doubt, say N here.
683 depends on PM_SLEEP_SMP
685 bool "kexec system call"
687 kexec is a system call that implements the ability to shutdown your
688 current kernel, and to start another kernel. It is like a reboot
689 but it is independent of the system firmware. And like a reboot
690 you can start any kernel with it, not just Linux.
697 bool "Xen guest support on ARM64"
698 depends on ARM64 && OF
702 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
704 config FORCE_MAX_ZONEORDER
706 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
707 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
710 The kernel memory allocator divides physically contiguous memory
711 blocks into "zones", where each zone is a power of two number of
712 pages. This option selects the largest power of two that the kernel
713 keeps in the memory allocator. If you need to allocate very large
714 blocks of physically contiguous memory, then you may need to
717 This config option is actually maximum order plus one. For example,
718 a value of 11 means that the largest free memory block is 2^10 pages.
720 We make sure that we can allocate upto a HugePage size for each configuration.
722 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
724 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
725 4M allocations matching the default size used by generic code.
727 menuconfig ARMV8_DEPRECATED
728 bool "Emulate deprecated/obsolete ARMv8 instructions"
731 Legacy software support may require certain instructions
732 that have been deprecated or obsoleted in the architecture.
734 Enable this config to enable selective emulation of these
742 bool "Emulate SWP/SWPB instructions"
744 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
745 they are always undefined. Say Y here to enable software
746 emulation of these instructions for userspace using LDXR/STXR.
748 In some older versions of glibc [<=2.8] SWP is used during futex
749 trylock() operations with the assumption that the code will not
750 be preempted. This invalid assumption may be more likely to fail
751 with SWP emulation enabled, leading to deadlock of the user
754 NOTE: when accessing uncached shared regions, LDXR/STXR rely
755 on an external transaction monitoring block called a global
756 monitor to maintain update atomicity. If your system does not
757 implement a global monitor, this option can cause programs that
758 perform SWP operations to uncached memory to deadlock.
762 config CP15_BARRIER_EMULATION
763 bool "Emulate CP15 Barrier instructions"
765 The CP15 barrier instructions - CP15ISB, CP15DSB, and
766 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
767 strongly recommended to use the ISB, DSB, and DMB
768 instructions instead.
770 Say Y here to enable software emulation of these
771 instructions for AArch32 userspace code. When this option is
772 enabled, CP15 barrier usage is traced which can help
773 identify software that needs updating.
777 config SETEND_EMULATION
778 bool "Emulate SETEND instruction"
780 The SETEND instruction alters the data-endianness of the
781 AArch32 EL0, and is deprecated in ARMv8.
783 Say Y here to enable software emulation of the instruction
784 for AArch32 userspace code.
786 Note: All the cpus on the system must have mixed endian support at EL0
787 for this feature to be enabled. If a new CPU - which doesn't support mixed
788 endian - is hotplugged in after this feature has been enabled, there could
789 be unexpected results in the applications.
794 menu "ARMv8.1 architectural features"
796 config ARM64_HW_AFDBM
797 bool "Support for hardware updates of the Access and Dirty page flags"
800 The ARMv8.1 architecture extensions introduce support for
801 hardware updates of the access and dirty information in page
802 table entries. When enabled in TCR_EL1 (HA and HD bits) on
803 capable processors, accesses to pages with PTE_AF cleared will
804 set this bit instead of raising an access flag fault.
805 Similarly, writes to read-only pages with the DBM bit set will
806 clear the read-only bit (AP[2]) instead of raising a
809 Kernels built with this configuration option enabled continue
810 to work on pre-ARMv8.1 hardware and the performance impact is
811 minimal. If unsure, say Y.
814 bool "Enable support for Privileged Access Never (PAN)"
817 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
818 prevents the kernel or hypervisor from accessing user-space (EL0)
821 Choosing this option will cause any unprotected (not using
822 copy_to_user et al) memory access to fail with a permission fault.
824 The feature is detected at runtime, and will remain as a 'nop'
825 instruction if the cpu does not implement the feature.
827 config ARM64_LSE_ATOMICS
828 bool "Atomic instructions"
830 As part of the Large System Extensions, ARMv8.1 introduces new
831 atomic instructions that are designed specifically to scale in
834 Say Y here to make use of these instructions for the in-kernel
835 atomic routines. This incurs a small overhead on CPUs that do
836 not support these instructions and requires the kernel to be
837 built with binutils >= 2.25.
840 bool "Enable support for Virtualization Host Extensions (VHE)"
843 Virtualization Host Extensions (VHE) allow the kernel to run
844 directly at EL2 (instead of EL1) on processors that support
845 it. This leads to better performance for KVM, as they reduce
846 the cost of the world switch.
848 Selecting this option allows the VHE feature to be detected
849 at runtime, and does not affect processors that do not
850 implement this feature.
854 menu "ARMv8.2 architectural features"
857 bool "Enable support for User Access Override (UAO)"
860 User Access Override (UAO; part of the ARMv8.2 Extensions)
861 causes the 'unprivileged' variant of the load/store instructions to
862 be overriden to be privileged.
864 This option changes get_user() and friends to use the 'unprivileged'
865 variant of the load/store instructions. This ensures that user-space
866 really did have access to the supplied memory. When addr_limit is
867 set to kernel memory the UAO bit will be set, allowing privileged
868 access to kernel memory.
870 Choosing this option will cause copy_to_user() et al to use user-space
873 The feature is detected at runtime, the kernel will use the
874 regular load/store instructions if the cpu does not implement the
879 config ARM64_MODULE_CMODEL_LARGE
882 config ARM64_MODULE_PLTS
884 select ARM64_MODULE_CMODEL_LARGE
885 select HAVE_MOD_ARCH_SPECIFIC
890 This builds the kernel as a Position Independent Executable (PIE),
891 which retains all relocation metadata required to relocate the
892 kernel binary at runtime to a different virtual address than the
893 address it was linked at.
894 Since AArch64 uses the RELA relocation format, this requires a
895 relocation pass at runtime even if the kernel is loaded at the
896 same address it was linked at.
898 config RANDOMIZE_BASE
899 bool "Randomize the address of the kernel image"
900 select ARM64_MODULE_PLTS if MODULES
903 Randomizes the virtual address at which the kernel image is
904 loaded, as a security feature that deters exploit attempts
905 relying on knowledge of the location of kernel internals.
907 It is the bootloader's job to provide entropy, by passing a
908 random u64 value in /chosen/kaslr-seed at kernel entry.
910 When booting via the UEFI stub, it will invoke the firmware's
911 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
912 to the kernel proper. In addition, it will randomise the physical
913 location of the kernel Image as well.
917 config RANDOMIZE_MODULE_REGION_FULL
918 bool "Randomize the module region independently from the core kernel"
919 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
922 Randomizes the location of the module region without considering the
923 location of the core kernel. This way, it is impossible for modules
924 to leak information about the location of core kernel data structures
925 but it does imply that function calls between modules and the core
926 kernel will need to be resolved via veneers in the module PLT.
928 When this option is not set, the module region will be randomized over
929 a limited range that contains the [_stext, _etext] interval of the
930 core kernel, so branch relocations are always in range.
936 config ARM64_ACPI_PARKING_PROTOCOL
937 bool "Enable support for the ARM64 ACPI parking protocol"
940 Enable support for the ARM64 ACPI parking protocol. If disabled
941 the kernel will not allow booting through the ARM64 ACPI parking
942 protocol even if the corresponding data is present in the ACPI
946 string "Default kernel command string"
949 Provide a set of default command-line options at build time by
950 entering them here. As a minimum, you should specify the the
951 root device (e.g. root=/dev/nfs).
954 bool "Always use the default kernel command string"
956 Always use the default kernel command string, even if the boot
957 loader passes other arguments to the kernel.
958 This is useful if you cannot or don't want to change the
959 command-line options your boot loader passes to the kernel.
965 bool "UEFI runtime support"
966 depends on OF && !CPU_BIG_ENDIAN
969 select EFI_PARAMS_FROM_FDT
970 select EFI_RUNTIME_WRAPPERS
975 This option provides support for runtime services provided
976 by UEFI firmware (such as non-volatile variables, realtime
977 clock, and platform reset). A UEFI stub is also provided to
978 allow the kernel to be booted as an EFI application. This
979 is only useful on systems that have UEFI firmware.
982 bool "Enable support for SMBIOS (DMI) tables"
986 This enables SMBIOS/DMI feature for systems.
988 This option is only useful on systems that have UEFI firmware.
989 However, even with this option, the resultant kernel should
990 continue to boot on existing non-UEFI platforms.
994 menu "Userspace binary formats"
996 source "fs/Kconfig.binfmt"
999 bool "Kernel support for 32-bit EL0"
1000 depends on ARM64_4K_PAGES || EXPERT
1001 select COMPAT_BINFMT_ELF
1003 select OLD_SIGSUSPEND3
1004 select COMPAT_OLD_SIGACTION
1006 This option enables support for a 32-bit EL0 running under a 64-bit
1007 kernel at EL1. AArch32-specific components such as system calls,
1008 the user helper functions, VFP support and the ptrace interface are
1009 handled appropriately by the kernel.
1011 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1012 that you will only be able to execute AArch32 binaries that were compiled
1013 with page size aligned segments.
1015 If you want to execute 32-bit userspace applications, say Y.
1017 config SYSVIPC_COMPAT
1019 depends on COMPAT && SYSVIPC
1023 menu "Power management options"
1025 source "kernel/power/Kconfig"
1027 config ARCH_HIBERNATION_POSSIBLE
1031 config ARCH_HIBERNATION_HEADER
1033 depends on HIBERNATION
1035 config ARCH_SUSPEND_POSSIBLE
1040 menu "CPU Power Management"
1042 source "drivers/cpuidle/Kconfig"
1044 source "drivers/cpufreq/Kconfig"
1048 source "net/Kconfig"
1050 source "drivers/Kconfig"
1052 source "drivers/firmware/Kconfig"
1054 source "drivers/acpi/Kconfig"
1058 source "arch/arm64/kvm/Kconfig"
1060 source "arch/arm64/Kconfig.debug"
1062 source "security/Kconfig"
1064 source "crypto/Kconfig"
1066 source "arch/arm64/crypto/Kconfig"
1069 source "lib/Kconfig"