1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_MMAP_PGPROT
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_HAS_FAST_MULTIPLIER
21 select ARCH_HAS_FORTIFY_SOURCE
22 select ARCH_HAS_GCOV_PROFILE_ALL
23 select ARCH_HAS_GIGANTIC_PAGE
25 select ARCH_HAS_KEEPINITRD
26 select ARCH_HAS_MEMBARRIER_SYNC_CORE
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_MEMORY
30 select ARCH_HAS_STRICT_KERNEL_RWX
31 select ARCH_HAS_STRICT_MODULE_RWX
32 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
33 select ARCH_HAS_SYNC_DMA_FOR_CPU
34 select ARCH_HAS_SYSCALL_WRAPPER
35 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
36 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
37 select ARCH_HAVE_NMI_SAFE_CMPXCHG
38 select ARCH_INLINE_READ_LOCK if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
64 select ARCH_KEEP_MEMBLOCK
65 select ARCH_USE_CMPXCHG_LOCKREF
66 select ARCH_USE_QUEUED_RWLOCKS
67 select ARCH_USE_QUEUED_SPINLOCKS
68 select ARCH_SUPPORTS_MEMORY_FAILURE
69 select ARCH_SUPPORTS_ATOMIC_RMW
70 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
71 select ARCH_SUPPORTS_NUMA_BALANCING
72 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
73 select ARCH_WANT_FRAME_POINTERS
74 select ARCH_HAS_UBSAN_SANITIZE_ALL
78 select AUDIT_ARCH_COMPAT_GENERIC
79 select ARM_GIC_V2M if PCI
81 select ARM_GIC_V3_ITS if PCI
83 select BUILDTIME_EXTABLE_SORT
84 select CLONE_BACKWARDS
86 select CPU_PM if (SUSPEND || CPU_IDLE)
88 select DCACHE_WORD_ACCESS
89 select DMA_DIRECT_REMAP
92 select GENERIC_ALLOCATOR
93 select GENERIC_ARCH_TOPOLOGY
94 select GENERIC_CLOCKEVENTS
95 select GENERIC_CLOCKEVENTS_BROADCAST
96 select GENERIC_CPU_AUTOPROBE
97 select GENERIC_CPU_VULNERABILITIES
98 select GENERIC_EARLY_IOREMAP
99 select GENERIC_IDLE_POLL_SETUP
100 select GENERIC_IRQ_MULTI_HANDLER
101 select GENERIC_IRQ_PROBE
102 select GENERIC_IRQ_SHOW
103 select GENERIC_IRQ_SHOW_LEVEL
104 select GENERIC_PCI_IOMAP
105 select GENERIC_SCHED_CLOCK
106 select GENERIC_SMP_IDLE_THREAD
107 select GENERIC_STRNCPY_FROM_USER
108 select GENERIC_STRNLEN_USER
109 select GENERIC_TIME_VSYSCALL
110 select HANDLE_DOMAIN_IRQ
111 select HARDIRQS_SW_RESEND
113 select HAVE_ACPI_APEI if (ACPI && EFI)
114 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
115 select HAVE_ARCH_AUDITSYSCALL
116 select HAVE_ARCH_BITREVERSE
117 select HAVE_ARCH_HUGE_VMAP
118 select HAVE_ARCH_JUMP_LABEL
119 select HAVE_ARCH_JUMP_LABEL_RELATIVE
120 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
121 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
122 select HAVE_ARCH_KGDB
123 select HAVE_ARCH_MMAP_RND_BITS
124 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
125 select HAVE_ARCH_PREL32_RELOCATIONS
126 select HAVE_ARCH_SECCOMP_FILTER
127 select HAVE_ARCH_STACKLEAK
128 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
129 select HAVE_ARCH_TRACEHOOK
130 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
131 select HAVE_ARCH_VMAP_STACK
132 select HAVE_ARM_SMCCC
134 select HAVE_C_RECORDMCOUNT
135 select HAVE_CMPXCHG_DOUBLE
136 select HAVE_CMPXCHG_LOCAL
137 select HAVE_CONTEXT_TRACKING
138 select HAVE_DEBUG_BUGVERBOSE
139 select HAVE_DEBUG_KMEMLEAK
140 select HAVE_DMA_CONTIGUOUS
141 select HAVE_DYNAMIC_FTRACE
142 select HAVE_EFFICIENT_UNALIGNED_ACCESS
143 select HAVE_FTRACE_MCOUNT_RECORD
144 select HAVE_FUNCTION_TRACER
145 select HAVE_FUNCTION_GRAPH_TRACER
146 select HAVE_GCC_PLUGINS
147 select HAVE_HW_BREAKPOINT if PERF_EVENTS
148 select HAVE_IRQ_TIME_ACCOUNTING
149 select HAVE_MEMBLOCK_NODE_MAP if NUMA
151 select HAVE_PATA_PLATFORM
152 select HAVE_PERF_EVENTS
153 select HAVE_PERF_REGS
154 select HAVE_PERF_USER_STACK_DUMP
155 select HAVE_REGS_AND_STACK_ACCESS_API
156 select HAVE_FUNCTION_ARG_ACCESS_API
157 select HAVE_RCU_TABLE_FREE
159 select HAVE_STACKPROTECTOR
160 select HAVE_SYSCALL_TRACEPOINTS
162 select HAVE_KRETPROBES
163 select IOMMU_DMA if IOMMU_SUPPORT
165 select IRQ_FORCED_THREADING
166 select MODULES_USE_ELF_RELA
167 select NEED_DMA_MAP_STATE
168 select NEED_SG_DMA_LENGTH
170 select OF_EARLY_FLATTREE
171 select PCI_DOMAINS_GENERIC if PCI
172 select PCI_ECAM if (ACPI && PCI)
173 select PCI_SYSCALL if PCI
179 select SYSCTL_EXCEPTION_TRACE
180 select THREAD_INFO_IN_TASK
182 ARM 64-bit (AArch64) Linux support.
190 config ARM64_PAGE_SHIFT
192 default 16 if ARM64_64K_PAGES
193 default 14 if ARM64_16K_PAGES
196 config ARM64_CONT_SHIFT
198 default 5 if ARM64_64K_PAGES
199 default 7 if ARM64_16K_PAGES
202 config ARCH_MMAP_RND_BITS_MIN
203 default 14 if ARM64_64K_PAGES
204 default 16 if ARM64_16K_PAGES
207 # max bits determined by the following formula:
208 # VA_BITS - PAGE_SHIFT - 3
209 config ARCH_MMAP_RND_BITS_MAX
210 default 19 if ARM64_VA_BITS=36
211 default 24 if ARM64_VA_BITS=39
212 default 27 if ARM64_VA_BITS=42
213 default 30 if ARM64_VA_BITS=47
214 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
215 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
216 default 33 if ARM64_VA_BITS=48
217 default 14 if ARM64_64K_PAGES
218 default 16 if ARM64_16K_PAGES
221 config ARCH_MMAP_RND_COMPAT_BITS_MIN
222 default 7 if ARM64_64K_PAGES
223 default 9 if ARM64_16K_PAGES
226 config ARCH_MMAP_RND_COMPAT_BITS_MAX
232 config STACKTRACE_SUPPORT
235 config ILLEGAL_POINTER_VALUE
237 default 0xdead000000000000
239 config LOCKDEP_SUPPORT
242 config TRACE_IRQFLAGS_SUPPORT
249 config GENERIC_BUG_RELATIVE_POINTERS
251 depends on GENERIC_BUG
253 config GENERIC_HWEIGHT
259 config GENERIC_CALIBRATE_DELAY
265 config HAVE_GENERIC_GUP
268 config ARCH_ENABLE_MEMORY_HOTPLUG
274 config KERNEL_MODE_NEON
277 config FIX_EARLYCON_MEM
280 config PGTABLE_LEVELS
282 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
283 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
284 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
285 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
286 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
287 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
289 config ARCH_SUPPORTS_UPROBES
292 config ARCH_PROC_KCORE_TEXT
295 source "arch/arm64/Kconfig.platforms"
297 menu "Kernel Features"
299 menu "ARM errata workarounds via the alternatives framework"
301 config ARM64_WORKAROUND_CLEAN_CACHE
304 config ARM64_ERRATUM_826319
305 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
307 select ARM64_WORKAROUND_CLEAN_CACHE
309 This option adds an alternative code sequence to work around ARM
310 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
311 AXI master interface and an L2 cache.
313 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
314 and is unable to accept a certain write via this interface, it will
315 not progress on read data presented on the read data channel and the
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this does not necessarily enable the workaround,
321 as it depends on the alternative framework, which will only patch
322 the kernel if an affected CPU is detected.
326 config ARM64_ERRATUM_827319
327 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
329 select ARM64_WORKAROUND_CLEAN_CACHE
331 This option adds an alternative code sequence to work around ARM
332 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
333 master interface and an L2 cache.
335 Under certain conditions this erratum can cause a clean line eviction
336 to occur at the same time as another transaction to the same address
337 on the AMBA 5 CHI interface, which can cause data corruption if the
338 interconnect reorders the two transactions.
340 The workaround promotes data cache clean instructions to
341 data cache clean-and-invalidate.
342 Please note that this does not necessarily enable the workaround,
343 as it depends on the alternative framework, which will only patch
344 the kernel if an affected CPU is detected.
348 config ARM64_ERRATUM_824069
349 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
351 select ARM64_WORKAROUND_CLEAN_CACHE
353 This option adds an alternative code sequence to work around ARM
354 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
355 to a coherent interconnect.
357 If a Cortex-A53 processor is executing a store or prefetch for
358 write instruction at the same time as a processor in another
359 cluster is executing a cache maintenance operation to the same
360 address, then this erratum might cause a clean cache line to be
361 incorrectly marked as dirty.
363 The workaround promotes data cache clean instructions to
364 data cache clean-and-invalidate.
365 Please note that this option does not necessarily enable the
366 workaround, as it depends on the alternative framework, which will
367 only patch the kernel if an affected CPU is detected.
371 config ARM64_ERRATUM_819472
372 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
374 select ARM64_WORKAROUND_CLEAN_CACHE
376 This option adds an alternative code sequence to work around ARM
377 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
378 present when it is connected to a coherent interconnect.
380 If the processor is executing a load and store exclusive sequence at
381 the same time as a processor in another cluster is executing a cache
382 maintenance operation to the same address, then this erratum might
383 cause data corruption.
385 The workaround promotes data cache clean instructions to
386 data cache clean-and-invalidate.
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_832075
394 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
397 This option adds an alternative code sequence to work around ARM
398 erratum 832075 on Cortex-A57 parts up to r1p2.
400 Affected Cortex-A57 parts might deadlock when exclusive load/store
401 instructions to Write-Back memory are mixed with Device loads.
403 The workaround is to promote device loads to use Load-Acquire
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
411 config ARM64_ERRATUM_834220
412 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
416 This option adds an alternative code sequence to work around ARM
417 erratum 834220 on Cortex-A57 parts up to r1p2.
419 Affected Cortex-A57 parts might report a Stage 2 translation
420 fault as the result of a Stage 1 fault for load crossing a
421 page boundary when there is a permission or device memory
422 alignment fault at Stage 1 and a translation fault at Stage 2.
424 The workaround is to verify that the Stage 1 translation
425 doesn't generate a fault before handling the Stage 2 fault.
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_845719
433 bool "Cortex-A53: 845719: a load might read incorrect data"
437 This option adds an alternative code sequence to work around ARM
438 erratum 845719 on Cortex-A53 parts up to r0p4.
440 When running a compat (AArch32) userspace on an affected Cortex-A53
441 part, a load at EL0 from a virtual address that matches the bottom 32
442 bits of the virtual address used by a recent load at (AArch64) EL1
443 might return incorrect data.
445 The workaround is to write the contextidr_el1 register on exception
446 return to a 32-bit task.
447 Please note that this does not necessarily enable the workaround,
448 as it depends on the alternative framework, which will only patch
449 the kernel if an affected CPU is detected.
453 config ARM64_ERRATUM_843419
454 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
456 select ARM64_MODULE_PLTS if MODULES
458 This option links the kernel with '--fix-cortex-a53-843419' and
459 enables PLT support to replace certain ADRP instructions, which can
460 cause subsequent memory accesses to use an incorrect address on
461 Cortex-A53 parts up to r0p4.
465 config ARM64_ERRATUM_1024718
466 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
469 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
471 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
472 update of the hardware dirty bit when the DBM/AP bits are updated
473 without a break-before-make. The workaround is to disable the usage
474 of hardware DBM locally on the affected cores. CPUs not affected by
475 this erratum will continue to use the feature.
479 config ARM64_ERRATUM_1188873
480 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
483 select ARM_ARCH_TIMER_OOL_WORKAROUND
485 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
488 Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
489 cause register corruption when accessing the timer registers
490 from AArch32 userspace.
494 config ARM64_ERRATUM_1165522
495 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
498 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
500 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
501 corrupted TLBs by speculating an AT instruction during a guest
506 config ARM64_ERRATUM_1286807
507 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
509 select ARM64_WORKAROUND_REPEAT_TLBI
511 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
513 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
514 address for a cacheable mapping of a location is being
515 accessed by a core while another core is remapping the virtual
516 address to a new physical page using the recommended
517 break-before-make sequence, then under very rare circumstances
518 TLBI+DSB completes before a read using the translation being
519 invalidated has been observed by other observers. The
520 workaround repeats the TLBI+DSB operation.
524 config CAVIUM_ERRATUM_22375
525 bool "Cavium erratum 22375, 24313"
528 Enable workaround for errata 22375 and 24313.
530 This implements two gicv3-its errata workarounds for ThunderX. Both
531 with a small impact affecting only ITS table allocation.
533 erratum 22375: only alloc 8MB table size
534 erratum 24313: ignore memory access type
536 The fixes are in ITS initialization and basically ignore memory access
537 type and table size provided by the TYPER and BASER registers.
541 config CAVIUM_ERRATUM_23144
542 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
546 ITS SYNC command hang for cross node io and collections/cpu mapping.
550 config CAVIUM_ERRATUM_23154
551 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
554 The gicv3 of ThunderX requires a modified version for
555 reading the IAR status to ensure data synchronization
556 (access to icc_iar1_el1 is not sync'ed before and after).
560 config CAVIUM_ERRATUM_27456
561 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
564 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
565 instructions may cause the icache to become corrupted if it
566 contains data for a non-current ASID. The fix is to
567 invalidate the icache when changing the mm context.
571 config CAVIUM_ERRATUM_30115
572 bool "Cavium erratum 30115: Guest may disable interrupts in host"
575 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
576 1.2, and T83 Pass 1.0, KVM guest execution may disable
577 interrupts in host. Trapping both GICv3 group-0 and group-1
578 accesses sidesteps the issue.
582 config QCOM_FALKOR_ERRATUM_1003
583 bool "Falkor E1003: Incorrect translation due to ASID change"
586 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
587 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
588 in TTBR1_EL1, this situation only occurs in the entry trampoline and
589 then only for entries in the walk cache, since the leaf translation
590 is unchanged. Work around the erratum by invalidating the walk cache
591 entries for the trampoline before entering the kernel proper.
593 config ARM64_WORKAROUND_REPEAT_TLBI
596 config QCOM_FALKOR_ERRATUM_1009
597 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
599 select ARM64_WORKAROUND_REPEAT_TLBI
601 On Falkor v1, the CPU may prematurely complete a DSB following a
602 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
603 one more time to fix the issue.
607 config QCOM_QDF2400_ERRATUM_0065
608 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
611 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
612 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
613 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
617 config SOCIONEXT_SYNQUACER_PREITS
618 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
621 Socionext Synquacer SoCs implement a separate h/w block to generate
622 MSI doorbell writes with non-zero values for the device ID.
626 config HISILICON_ERRATUM_161600802
627 bool "Hip07 161600802: Erroneous redistributor VLPI base"
630 The HiSilicon Hip07 SoC uses the wrong redistributor base
631 when issued ITS commands such as VMOVP and VMAPP, and requires
632 a 128kB offset to be applied to the target address in this commands.
636 config QCOM_FALKOR_ERRATUM_E1041
637 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
640 Falkor CPU may speculatively fetch instructions from an improper
641 memory location when MMU translation is changed from SCTLR_ELn[M]=1
642 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
646 config FUJITSU_ERRATUM_010001
647 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
650 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
651 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
652 accesses may cause undefined fault (Data abort, DFSC=0b111111).
653 This fault occurs under a specific hardware condition when a
654 load/store instruction performs an address translation using:
655 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
656 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
657 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
658 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
660 The workaround is to ensure these bits are clear in TCR_ELx.
661 The workaround only affects the Fujitsu-A64FX.
670 default ARM64_4K_PAGES
672 Page size (translation granule) configuration.
674 config ARM64_4K_PAGES
677 This feature enables 4KB pages support.
679 config ARM64_16K_PAGES
682 The system will use 16KB pages support. AArch32 emulation
683 requires applications compiled with 16K (or a multiple of 16K)
686 config ARM64_64K_PAGES
689 This feature enables 64KB pages support (4KB by default)
690 allowing only two levels of page tables and faster TLB
691 look-up. AArch32 emulation requires applications compiled
692 with 64K aligned segments.
697 prompt "Virtual address space size"
698 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
699 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
700 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
702 Allows choosing one of multiple possible virtual address
703 space sizes. The level of translation table is determined by
704 a combination of page size and virtual address space size.
706 config ARM64_VA_BITS_36
707 bool "36-bit" if EXPERT
708 depends on ARM64_16K_PAGES
710 config ARM64_VA_BITS_39
712 depends on ARM64_4K_PAGES
714 config ARM64_VA_BITS_42
716 depends on ARM64_64K_PAGES
718 config ARM64_VA_BITS_47
720 depends on ARM64_16K_PAGES
722 config ARM64_VA_BITS_48
725 config ARM64_USER_VA_BITS_52
727 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
729 Enable 52-bit virtual addressing for userspace when explicitly
730 requested via a hint to mmap(). The kernel will continue to
731 use 48-bit virtual addresses for its own mappings.
733 NOTE: Enabling 52-bit virtual addressing in conjunction with
734 ARMv8.3 Pointer Authentication will result in the PAC being
735 reduced from 7 bits to 3 bits, which may have a significant
736 impact on its susceptibility to brute-force attacks.
738 If unsure, select 48-bit virtual addressing instead.
742 config ARM64_FORCE_52BIT
743 bool "Force 52-bit virtual addresses for userspace"
744 depends on ARM64_USER_VA_BITS_52 && EXPERT
746 For systems with 52-bit userspace VAs enabled, the kernel will attempt
747 to maintain compatibility with older software by providing 48-bit VAs
748 unless a hint is supplied to mmap.
750 This configuration option disables the 48-bit compatibility logic, and
751 forces all userspace addresses to be 52-bit on HW that supports it. One
752 should only enable this configuration option for stress testing userspace
753 memory management code. If unsure say N here.
757 default 36 if ARM64_VA_BITS_36
758 default 39 if ARM64_VA_BITS_39
759 default 42 if ARM64_VA_BITS_42
760 default 47 if ARM64_VA_BITS_47
761 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
764 prompt "Physical address space size"
765 default ARM64_PA_BITS_48
767 Choose the maximum physical address range that the kernel will
770 config ARM64_PA_BITS_48
773 config ARM64_PA_BITS_52
774 bool "52-bit (ARMv8.2)"
775 depends on ARM64_64K_PAGES
776 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
778 Enable support for a 52-bit physical address space, introduced as
779 part of the ARMv8.2-LPA extension.
781 With this enabled, the kernel will also continue to work on CPUs that
782 do not support ARMv8.2-LPA, but with some added memory overhead (and
783 minor performance overhead).
789 default 48 if ARM64_PA_BITS_48
790 default 52 if ARM64_PA_BITS_52
792 config CPU_BIG_ENDIAN
793 bool "Build big-endian kernel"
795 Say Y if you plan on running a kernel in big-endian mode.
798 bool "Multi-core scheduler support"
800 Multi-core scheduler support improves the CPU scheduler's decision
801 making when dealing with multi-core CPU chips at a cost of slightly
802 increased overhead in some places. If unsure say N here.
805 bool "SMT scheduler support"
807 Improves the CPU scheduler's decision making when dealing with
808 MultiThreading at a cost of slightly increased overhead in some
809 places. If unsure say N here.
812 int "Maximum number of CPUs (2-4096)"
817 bool "Support for hot-pluggable CPUs"
818 select GENERIC_IRQ_MIGRATION
820 Say Y here to experiment with turning CPUs off and on. CPUs
821 can be controlled through /sys/devices/system/cpu.
823 # Common NUMA Features
825 bool "Numa Memory Allocation and Scheduler Support"
826 select ACPI_NUMA if ACPI
829 Enable NUMA (Non Uniform Memory Access) support.
831 The kernel will try to allocate memory used by a CPU on the
832 local memory of the CPU and add some more
833 NUMA awareness to the kernel.
836 int "Maximum NUMA Nodes (as a power of 2)"
839 depends on NEED_MULTIPLE_NODES
841 Specify the maximum number of NUMA Nodes available on the target
842 system. Increases memory reserved to accommodate various tables.
844 config USE_PERCPU_NUMA_NODE_ID
848 config HAVE_SETUP_PER_CPU_AREA
852 config NEED_PER_CPU_EMBED_FIRST_CHUNK
859 source "kernel/Kconfig.hz"
861 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
864 config ARCH_SPARSEMEM_ENABLE
866 select SPARSEMEM_VMEMMAP_ENABLE
868 config ARCH_SPARSEMEM_DEFAULT
869 def_bool ARCH_SPARSEMEM_ENABLE
871 config ARCH_SELECT_MEMORY_MODEL
872 def_bool ARCH_SPARSEMEM_ENABLE
874 config ARCH_FLATMEM_ENABLE
877 config HAVE_ARCH_PFN_VALID
880 config HW_PERF_EVENTS
884 config SYS_SUPPORTS_HUGETLBFS
887 config ARCH_WANT_HUGE_PMD_SHARE
888 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
890 config ARCH_HAS_CACHE_LINE_SIZE
893 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
894 def_bool y if PGTABLE_LEVELS > 2
897 bool "Enable seccomp to safely compute untrusted bytecode"
899 This kernel feature is useful for number crunching applications
900 that may need to compute untrusted bytecode during their
901 execution. By using pipes or other transports made available to
902 the process as file descriptors supporting the read/write
903 syscalls, it's possible to isolate those applications in
904 their own address space using seccomp. Once seccomp is
905 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
906 and the task is only allowed to execute a few safe syscalls
907 defined by each seccomp mode.
910 bool "Enable paravirtualization code"
912 This changes the kernel so it can modify itself when it is run
913 under a hypervisor, potentially improving performance significantly
914 over full virtualization.
916 config PARAVIRT_TIME_ACCOUNTING
917 bool "Paravirtual steal time accounting"
921 Select this option to enable fine granularity task steal time
922 accounting. Time spent executing other tasks in parallel with
923 the current vCPU is discounted from the vCPU power. To account for
924 that, there can be a small performance impact.
926 If in doubt, say N here.
929 depends on PM_SLEEP_SMP
931 bool "kexec system call"
933 kexec is a system call that implements the ability to shutdown your
934 current kernel, and to start another kernel. It is like a reboot
935 but it is independent of the system firmware. And like a reboot
936 you can start any kernel with it, not just Linux.
939 bool "kexec file based system call"
942 This is new version of kexec system call. This system call is
943 file based and takes file descriptors as system call argument
944 for kernel and initramfs as opposed to list of segments as
945 accepted by previous system call.
947 config KEXEC_VERIFY_SIG
948 bool "Verify kernel signature during kexec_file_load() syscall"
949 depends on KEXEC_FILE
951 Select this option to verify a signature with loaded kernel
952 image. If configured, any attempt of loading a image without
953 valid signature will fail.
955 In addition to that option, you need to enable signature
956 verification for the corresponding kernel image type being
957 loaded in order for this to work.
959 config KEXEC_IMAGE_VERIFY_SIG
960 bool "Enable Image signature verification support"
962 depends on KEXEC_VERIFY_SIG
963 depends on EFI && SIGNED_PE_FILE_VERIFICATION
965 Enable Image signature verification support.
967 comment "Support for PE file signature verification disabled"
968 depends on KEXEC_VERIFY_SIG
969 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
972 bool "Build kdump crash kernel"
974 Generate crash dump after being started by kexec. This should
975 be normally only set in special crash dump kernels which are
976 loaded in the main kernel with kexec-tools into a specially
977 reserved region and then later executed after a crash by
980 For more details see Documentation/kdump/kdump.txt
987 bool "Xen guest support on ARM64"
988 depends on ARM64 && OF
992 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
994 config FORCE_MAX_ZONEORDER
996 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
997 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1000 The kernel memory allocator divides physically contiguous memory
1001 blocks into "zones", where each zone is a power of two number of
1002 pages. This option selects the largest power of two that the kernel
1003 keeps in the memory allocator. If you need to allocate very large
1004 blocks of physically contiguous memory, then you may need to
1005 increase this value.
1007 This config option is actually maximum order plus one. For example,
1008 a value of 11 means that the largest free memory block is 2^10 pages.
1010 We make sure that we can allocate upto a HugePage size for each configuration.
1012 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1014 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1015 4M allocations matching the default size used by generic code.
1017 config UNMAP_KERNEL_AT_EL0
1018 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1021 Speculation attacks against some high-performance processors can
1022 be used to bypass MMU permission checks and leak kernel data to
1023 userspace. This can be defended against by unmapping the kernel
1024 when running in userspace, mapping it back in on exception entry
1025 via a trampoline page in the vector table.
1029 config HARDEN_BRANCH_PREDICTOR
1030 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1033 Speculation attacks against some high-performance processors rely on
1034 being able to manipulate the branch predictor for a victim context by
1035 executing aliasing branches in the attacker context. Such attacks
1036 can be partially mitigated against by clearing internal branch
1037 predictor state and limiting the prediction logic in some situations.
1039 This config option will take CPU-specific actions to harden the
1040 branch predictor against aliasing attacks and may rely on specific
1041 instruction sequences or control bits being set by the system
1046 config HARDEN_EL2_VECTORS
1047 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1050 Speculation attacks against some high-performance processors can
1051 be used to leak privileged information such as the vector base
1052 register, resulting in a potential defeat of the EL2 layout
1055 This config option will map the vectors to a fixed location,
1056 independent of the EL2 code mapping, so that revealing VBAR_EL2
1057 to an attacker does not give away any extra information. This
1058 only gets enabled on affected CPUs.
1063 bool "Speculative Store Bypass Disable" if EXPERT
1066 This enables mitigation of the bypassing of previous stores
1067 by speculative loads.
1071 config RODATA_FULL_DEFAULT_ENABLED
1072 bool "Apply r/o permissions of VM areas also to their linear aliases"
1075 Apply read-only attributes of VM areas to the linear alias of
1076 the backing pages as well. This prevents code or read-only data
1077 from being modified (inadvertently or intentionally) via another
1078 mapping of the same memory page. This additional enhancement can
1079 be turned off at runtime by passing rodata=[off|on] (and turned on
1080 with rodata=full if this option is set to 'n')
1082 This requires the linear region to be mapped down to pages,
1083 which may adversely affect performance in some cases.
1085 config ARM64_SW_TTBR0_PAN
1086 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1088 Enabling this option prevents the kernel from accessing
1089 user-space memory directly by pointing TTBR0_EL1 to a reserved
1090 zeroed area and reserved ASID. The user access routines
1091 restore the valid TTBR0_EL1 temporarily.
1094 bool "Kernel support for 32-bit EL0"
1095 depends on ARM64_4K_PAGES || EXPERT
1096 select COMPAT_BINFMT_ELF if BINFMT_ELF
1098 select OLD_SIGSUSPEND3
1099 select COMPAT_OLD_SIGACTION
1101 This option enables support for a 32-bit EL0 running under a 64-bit
1102 kernel at EL1. AArch32-specific components such as system calls,
1103 the user helper functions, VFP support and the ptrace interface are
1104 handled appropriately by the kernel.
1106 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1107 that you will only be able to execute AArch32 binaries that were compiled
1108 with page size aligned segments.
1110 If you want to execute 32-bit userspace applications, say Y.
1114 config KUSER_HELPERS
1115 bool "Enable kuser helpers page for 32 bit applications"
1118 Warning: disabling this option may break 32-bit user programs.
1120 Provide kuser helpers to compat tasks. The kernel provides
1121 helper code to userspace in read only form at a fixed location
1122 to allow userspace to be independent of the CPU type fitted to
1123 the system. This permits binaries to be run on ARMv4 through
1124 to ARMv8 without modification.
1126 See Documentation/arm/kernel_user_helpers.txt for details.
1128 However, the fixed address nature of these helpers can be used
1129 by ROP (return orientated programming) authors when creating
1132 If all of the binaries and libraries which run on your platform
1133 are built specifically for your platform, and make no use of
1134 these helpers, then you can turn this option off to hinder
1135 such exploits. However, in that case, if a binary or library
1136 relying on those helpers is run, it will not function correctly.
1138 Say N here only if you are absolutely certain that you do not
1139 need these helpers; otherwise, the safe option is to say Y.
1142 menuconfig ARMV8_DEPRECATED
1143 bool "Emulate deprecated/obsolete ARMv8 instructions"
1146 Legacy software support may require certain instructions
1147 that have been deprecated or obsoleted in the architecture.
1149 Enable this config to enable selective emulation of these
1156 config SWP_EMULATION
1157 bool "Emulate SWP/SWPB instructions"
1159 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1160 they are always undefined. Say Y here to enable software
1161 emulation of these instructions for userspace using LDXR/STXR.
1163 In some older versions of glibc [<=2.8] SWP is used during futex
1164 trylock() operations with the assumption that the code will not
1165 be preempted. This invalid assumption may be more likely to fail
1166 with SWP emulation enabled, leading to deadlock of the user
1169 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1170 on an external transaction monitoring block called a global
1171 monitor to maintain update atomicity. If your system does not
1172 implement a global monitor, this option can cause programs that
1173 perform SWP operations to uncached memory to deadlock.
1177 config CP15_BARRIER_EMULATION
1178 bool "Emulate CP15 Barrier instructions"
1180 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1181 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1182 strongly recommended to use the ISB, DSB, and DMB
1183 instructions instead.
1185 Say Y here to enable software emulation of these
1186 instructions for AArch32 userspace code. When this option is
1187 enabled, CP15 barrier usage is traced which can help
1188 identify software that needs updating.
1192 config SETEND_EMULATION
1193 bool "Emulate SETEND instruction"
1195 The SETEND instruction alters the data-endianness of the
1196 AArch32 EL0, and is deprecated in ARMv8.
1198 Say Y here to enable software emulation of the instruction
1199 for AArch32 userspace code.
1201 Note: All the cpus on the system must have mixed endian support at EL0
1202 for this feature to be enabled. If a new CPU - which doesn't support mixed
1203 endian - is hotplugged in after this feature has been enabled, there could
1204 be unexpected results in the applications.
1211 menu "ARMv8.1 architectural features"
1213 config ARM64_HW_AFDBM
1214 bool "Support for hardware updates of the Access and Dirty page flags"
1217 The ARMv8.1 architecture extensions introduce support for
1218 hardware updates of the access and dirty information in page
1219 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1220 capable processors, accesses to pages with PTE_AF cleared will
1221 set this bit instead of raising an access flag fault.
1222 Similarly, writes to read-only pages with the DBM bit set will
1223 clear the read-only bit (AP[2]) instead of raising a
1226 Kernels built with this configuration option enabled continue
1227 to work on pre-ARMv8.1 hardware and the performance impact is
1228 minimal. If unsure, say Y.
1231 bool "Enable support for Privileged Access Never (PAN)"
1234 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1235 prevents the kernel or hypervisor from accessing user-space (EL0)
1238 Choosing this option will cause any unprotected (not using
1239 copy_to_user et al) memory access to fail with a permission fault.
1241 The feature is detected at runtime, and will remain as a 'nop'
1242 instruction if the cpu does not implement the feature.
1244 config ARM64_LSE_ATOMICS
1245 bool "Atomic instructions"
1248 As part of the Large System Extensions, ARMv8.1 introduces new
1249 atomic instructions that are designed specifically to scale in
1252 Say Y here to make use of these instructions for the in-kernel
1253 atomic routines. This incurs a small overhead on CPUs that do
1254 not support these instructions and requires the kernel to be
1255 built with binutils >= 2.25 in order for the new instructions
1259 bool "Enable support for Virtualization Host Extensions (VHE)"
1262 Virtualization Host Extensions (VHE) allow the kernel to run
1263 directly at EL2 (instead of EL1) on processors that support
1264 it. This leads to better performance for KVM, as they reduce
1265 the cost of the world switch.
1267 Selecting this option allows the VHE feature to be detected
1268 at runtime, and does not affect processors that do not
1269 implement this feature.
1273 menu "ARMv8.2 architectural features"
1276 bool "Enable support for User Access Override (UAO)"
1279 User Access Override (UAO; part of the ARMv8.2 Extensions)
1280 causes the 'unprivileged' variant of the load/store instructions to
1281 be overridden to be privileged.
1283 This option changes get_user() and friends to use the 'unprivileged'
1284 variant of the load/store instructions. This ensures that user-space
1285 really did have access to the supplied memory. When addr_limit is
1286 set to kernel memory the UAO bit will be set, allowing privileged
1287 access to kernel memory.
1289 Choosing this option will cause copy_to_user() et al to use user-space
1292 The feature is detected at runtime, the kernel will use the
1293 regular load/store instructions if the cpu does not implement the
1297 bool "Enable support for persistent memory"
1298 select ARCH_HAS_PMEM_API
1299 select ARCH_HAS_UACCESS_FLUSHCACHE
1301 Say Y to enable support for the persistent memory API based on the
1302 ARMv8.2 DCPoP feature.
1304 The feature is detected at runtime, and the kernel will use DC CVAC
1305 operations if DC CVAP is not supported (following the behaviour of
1306 DC CVAP itself if the system does not define a point of persistence).
1308 config ARM64_RAS_EXTN
1309 bool "Enable support for RAS CPU Extensions"
1312 CPUs that support the Reliability, Availability and Serviceability
1313 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1314 errors, classify them and report them to software.
1316 On CPUs with these extensions system software can use additional
1317 barriers to determine if faults are pending and read the
1318 classification from a new set of registers.
1320 Selecting this feature will allow the kernel to use these barriers
1321 and access the new registers if the system supports the extension.
1322 Platform RAS features may additionally depend on firmware support.
1325 bool "Enable support for Common Not Private (CNP) translations"
1327 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1329 Common Not Private (CNP) allows translation table entries to
1330 be shared between different PEs in the same inner shareable
1331 domain, so the hardware can use this fact to optimise the
1332 caching of such entries in the TLB.
1334 Selecting this option allows the CNP feature to be detected
1335 at runtime, and does not affect PEs that do not implement
1340 menu "ARMv8.3 architectural features"
1342 config ARM64_PTR_AUTH
1343 bool "Enable support for pointer authentication"
1345 depends on !KVM || ARM64_VHE
1347 Pointer authentication (part of the ARMv8.3 Extensions) provides
1348 instructions for signing and authenticating pointers against secret
1349 keys, which can be used to mitigate Return Oriented Programming (ROP)
1352 This option enables these instructions at EL0 (i.e. for userspace).
1354 Choosing this option will cause the kernel to initialise secret keys
1355 for each process at exec() time, with these keys being
1356 context-switched along with the process.
1358 The feature is detected at runtime. If the feature is not present in
1359 hardware it will not be advertised to userspace/KVM guest nor will it
1360 be enabled. However, KVM guest also require VHE mode and hence
1361 CONFIG_ARM64_VHE=y option to use this feature.
1366 bool "ARM Scalable Vector Extension support"
1368 depends on !KVM || ARM64_VHE
1370 The Scalable Vector Extension (SVE) is an extension to the AArch64
1371 execution state which complements and extends the SIMD functionality
1372 of the base architecture to support much larger vectors and to enable
1373 additional vectorisation opportunities.
1375 To enable use of this extension on CPUs that implement it, say Y.
1377 On CPUs that support the SVE2 extensions, this option will enable
1380 Note that for architectural reasons, firmware _must_ implement SVE
1381 support when running on SVE capable hardware. The required support
1384 * version 1.5 and later of the ARM Trusted Firmware
1385 * the AArch64 boot wrapper since commit 5e1261e08abf
1386 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1388 For other firmware implementations, consult the firmware documentation
1391 If you need the kernel to boot on SVE-capable hardware with broken
1392 firmware, you may need to say N here until you get your firmware
1393 fixed. Otherwise, you may experience firmware panics or lockups when
1394 booting the kernel. If unsure and you are not observing these
1395 symptoms, you should assume that it is safe to say Y.
1397 CPUs that support SVE are architecturally required to support the
1398 Virtualization Host Extensions (VHE), so the kernel makes no
1399 provision for supporting SVE alongside KVM without VHE enabled.
1400 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1401 KVM in the same kernel image.
1403 config ARM64_MODULE_PLTS
1405 select HAVE_MOD_ARCH_SPECIFIC
1407 config ARM64_PSEUDO_NMI
1408 bool "Support for NMI-like interrupts"
1409 select CONFIG_ARM_GIC_V3
1411 Adds support for mimicking Non-Maskable Interrupts through the use of
1412 GIC interrupt priority. This support requires version 3 or later of
1415 This high priority configuration for interrupts needs to be
1416 explicitly enabled by setting the kernel parameter
1417 "irqchip.gicv3_pseudo_nmi" to 1.
1424 This builds the kernel as a Position Independent Executable (PIE),
1425 which retains all relocation metadata required to relocate the
1426 kernel binary at runtime to a different virtual address than the
1427 address it was linked at.
1428 Since AArch64 uses the RELA relocation format, this requires a
1429 relocation pass at runtime even if the kernel is loaded at the
1430 same address it was linked at.
1432 config RANDOMIZE_BASE
1433 bool "Randomize the address of the kernel image"
1434 select ARM64_MODULE_PLTS if MODULES
1437 Randomizes the virtual address at which the kernel image is
1438 loaded, as a security feature that deters exploit attempts
1439 relying on knowledge of the location of kernel internals.
1441 It is the bootloader's job to provide entropy, by passing a
1442 random u64 value in /chosen/kaslr-seed at kernel entry.
1444 When booting via the UEFI stub, it will invoke the firmware's
1445 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1446 to the kernel proper. In addition, it will randomise the physical
1447 location of the kernel Image as well.
1451 config RANDOMIZE_MODULE_REGION_FULL
1452 bool "Randomize the module region over a 4 GB range"
1453 depends on RANDOMIZE_BASE
1456 Randomizes the location of the module region inside a 4 GB window
1457 covering the core kernel. This way, it is less likely for modules
1458 to leak information about the location of core kernel data structures
1459 but it does imply that function calls between modules and the core
1460 kernel will need to be resolved via veneers in the module PLT.
1462 When this option is not set, the module region will be randomized over
1463 a limited range that contains the [_stext, _etext] interval of the
1464 core kernel, so branch relocations are always in range.
1466 config CC_HAVE_STACKPROTECTOR_SYSREG
1467 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1469 config STACKPROTECTOR_PER_TASK
1471 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1477 config ARM64_ACPI_PARKING_PROTOCOL
1478 bool "Enable support for the ARM64 ACPI parking protocol"
1481 Enable support for the ARM64 ACPI parking protocol. If disabled
1482 the kernel will not allow booting through the ARM64 ACPI parking
1483 protocol even if the corresponding data is present in the ACPI
1487 string "Default kernel command string"
1490 Provide a set of default command-line options at build time by
1491 entering them here. As a minimum, you should specify the the
1492 root device (e.g. root=/dev/nfs).
1494 config CMDLINE_FORCE
1495 bool "Always use the default kernel command string"
1497 Always use the default kernel command string, even if the boot
1498 loader passes other arguments to the kernel.
1499 This is useful if you cannot or don't want to change the
1500 command-line options your boot loader passes to the kernel.
1506 bool "UEFI runtime support"
1507 depends on OF && !CPU_BIG_ENDIAN
1508 depends on KERNEL_MODE_NEON
1509 select ARCH_SUPPORTS_ACPI
1512 select EFI_PARAMS_FROM_FDT
1513 select EFI_RUNTIME_WRAPPERS
1518 This option provides support for runtime services provided
1519 by UEFI firmware (such as non-volatile variables, realtime
1520 clock, and platform reset). A UEFI stub is also provided to
1521 allow the kernel to be booted as an EFI application. This
1522 is only useful on systems that have UEFI firmware.
1525 bool "Enable support for SMBIOS (DMI) tables"
1529 This enables SMBIOS/DMI feature for systems.
1531 This option is only useful on systems that have UEFI firmware.
1532 However, even with this option, the resultant kernel should
1533 continue to boot on existing non-UEFI platforms.
1537 config SYSVIPC_COMPAT
1539 depends on COMPAT && SYSVIPC
1541 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1543 depends on HUGETLB_PAGE && MIGRATION
1545 menu "Power management options"
1547 source "kernel/power/Kconfig"
1549 config ARCH_HIBERNATION_POSSIBLE
1553 config ARCH_HIBERNATION_HEADER
1555 depends on HIBERNATION
1557 config ARCH_SUSPEND_POSSIBLE
1562 menu "CPU Power Management"
1564 source "drivers/cpuidle/Kconfig"
1566 source "drivers/cpufreq/Kconfig"
1570 source "drivers/firmware/Kconfig"
1572 source "drivers/acpi/Kconfig"
1574 source "arch/arm64/kvm/Kconfig"
1577 source "arch/arm64/crypto/Kconfig"