3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
30 select GENERIC_ALLOCATOR
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CLOCKEVENTS_BROADCAST
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select GENERIC_TIME_VSYSCALL
45 select HANDLE_DOMAIN_IRQ
46 select HARDIRQS_SW_RESEND
47 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
48 select HAVE_ARCH_AUDITSYSCALL
49 select HAVE_ARCH_BITREVERSE
50 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_SECCOMP_FILTER
53 select HAVE_ARCH_TRACEHOOK
55 select HAVE_C_RECORDMCOUNT
56 select HAVE_CC_STACKPROTECTOR
57 select HAVE_CMPXCHG_DOUBLE
58 select HAVE_CMPXCHG_LOCAL
59 select HAVE_DEBUG_BUGVERBOSE
60 select HAVE_DEBUG_KMEMLEAK
61 select HAVE_DMA_API_DEBUG
63 select HAVE_DMA_CONTIGUOUS
64 select HAVE_DYNAMIC_FTRACE
65 select HAVE_EFFICIENT_UNALIGNED_ACCESS
66 select HAVE_FTRACE_MCOUNT_RECORD
67 select HAVE_FUNCTION_TRACER
68 select HAVE_FUNCTION_GRAPH_TRACER
69 select HAVE_GENERIC_DMA_COHERENT
70 select HAVE_HW_BREAKPOINT if PERF_EVENTS
72 select HAVE_PATA_PLATFORM
73 select HAVE_PERF_EVENTS
75 select HAVE_PERF_USER_STACK_DUMP
76 select HAVE_RCU_TABLE_FREE
77 select HAVE_SYSCALL_TRACEPOINTS
79 select IRQ_FORCED_THREADING
80 select MODULES_USE_ELF_RELA
83 select OF_EARLY_FLATTREE
84 select OF_RESERVED_MEM
85 select PERF_USE_VMALLOC
90 select SYSCTL_EXCEPTION_TRACE
91 select HAVE_CONTEXT_TRACKING
93 ARM 64-bit (AArch64) Linux support.
98 config ARCH_PHYS_ADDR_T_64BIT
107 config STACKTRACE_SUPPORT
110 config ILLEGAL_POINTER_VALUE
112 default 0xdead000000000000
114 config LOCKDEP_SUPPORT
117 config TRACE_IRQFLAGS_SUPPORT
120 config RWSEM_XCHGADD_ALGORITHM
127 config GENERIC_BUG_RELATIVE_POINTERS
129 depends on GENERIC_BUG
131 config GENERIC_HWEIGHT
137 config GENERIC_CALIBRATE_DELAY
143 config HAVE_GENERIC_RCU_GUP
146 config ARCH_DMA_ADDR_T_64BIT
149 config NEED_DMA_MAP_STATE
152 config NEED_SG_DMA_LENGTH
164 config KERNEL_MODE_NEON
167 config FIX_EARLYCON_MEM
170 config PGTABLE_LEVELS
172 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
173 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
174 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
175 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
177 source "init/Kconfig"
179 source "kernel/Kconfig.freezer"
181 source "arch/arm64/Kconfig.platforms"
188 This feature enables support for PCI bus system. If you say Y
189 here, the kernel will include drivers and infrastructure code
190 to support PCI bus devices.
195 config PCI_DOMAINS_GENERIC
201 source "drivers/pci/Kconfig"
202 source "drivers/pci/pcie/Kconfig"
203 source "drivers/pci/hotplug/Kconfig"
207 menu "Kernel Features"
209 menu "ARM errata workarounds via the alternatives framework"
211 config ARM64_ERRATUM_826319
212 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
215 This option adds an alternative code sequence to work around ARM
216 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
217 AXI master interface and an L2 cache.
219 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
220 and is unable to accept a certain write via this interface, it will
221 not progress on read data presented on the read data channel and the
224 The workaround promotes data cache clean instructions to
225 data cache clean-and-invalidate.
226 Please note that this does not necessarily enable the workaround,
227 as it depends on the alternative framework, which will only patch
228 the kernel if an affected CPU is detected.
232 config ARM64_ERRATUM_827319
233 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
236 This option adds an alternative code sequence to work around ARM
237 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
238 master interface and an L2 cache.
240 Under certain conditions this erratum can cause a clean line eviction
241 to occur at the same time as another transaction to the same address
242 on the AMBA 5 CHI interface, which can cause data corruption if the
243 interconnect reorders the two transactions.
245 The workaround promotes data cache clean instructions to
246 data cache clean-and-invalidate.
247 Please note that this does not necessarily enable the workaround,
248 as it depends on the alternative framework, which will only patch
249 the kernel if an affected CPU is detected.
253 config ARM64_ERRATUM_824069
254 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
257 This option adds an alternative code sequence to work around ARM
258 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
259 to a coherent interconnect.
261 If a Cortex-A53 processor is executing a store or prefetch for
262 write instruction at the same time as a processor in another
263 cluster is executing a cache maintenance operation to the same
264 address, then this erratum might cause a clean cache line to be
265 incorrectly marked as dirty.
267 The workaround promotes data cache clean instructions to
268 data cache clean-and-invalidate.
269 Please note that this option does not necessarily enable the
270 workaround, as it depends on the alternative framework, which will
271 only patch the kernel if an affected CPU is detected.
275 config ARM64_ERRATUM_819472
276 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
279 This option adds an alternative code sequence to work around ARM
280 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
281 present when it is connected to a coherent interconnect.
283 If the processor is executing a load and store exclusive sequence at
284 the same time as a processor in another cluster is executing a cache
285 maintenance operation to the same address, then this erratum might
286 cause data corruption.
288 The workaround promotes data cache clean instructions to
289 data cache clean-and-invalidate.
290 Please note that this does not necessarily enable the workaround,
291 as it depends on the alternative framework, which will only patch
292 the kernel if an affected CPU is detected.
296 config ARM64_ERRATUM_832075
297 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
300 This option adds an alternative code sequence to work around ARM
301 erratum 832075 on Cortex-A57 parts up to r1p2.
303 Affected Cortex-A57 parts might deadlock when exclusive load/store
304 instructions to Write-Back memory are mixed with Device loads.
306 The workaround is to promote device loads to use Load-Acquire
308 Please note that this does not necessarily enable the workaround,
309 as it depends on the alternative framework, which will only patch
310 the kernel if an affected CPU is detected.
314 config ARM64_ERRATUM_845719
315 bool "Cortex-A53: 845719: a load might read incorrect data"
319 This option adds an alternative code sequence to work around ARM
320 erratum 845719 on Cortex-A53 parts up to r0p4.
322 When running a compat (AArch32) userspace on an affected Cortex-A53
323 part, a load at EL0 from a virtual address that matches the bottom 32
324 bits of the virtual address used by a recent load at (AArch64) EL1
325 might return incorrect data.
327 The workaround is to write the contextidr_el1 register on exception
328 return to a 32-bit task.
329 Please note that this does not necessarily enable the workaround,
330 as it depends on the alternative framework, which will only patch
331 the kernel if an affected CPU is detected.
335 config ARM64_ERRATUM_843419
336 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
340 This option builds kernel modules using the large memory model in
341 order to avoid the use of the ADRP instruction, which can cause
342 a subsequent memory access to use an incorrect address on Cortex-A53
345 Note that the kernel itself must be linked with a version of ld
346 which fixes potentially affected ADRP instructions through the
356 default ARM64_4K_PAGES
358 Page size (translation granule) configuration.
360 config ARM64_4K_PAGES
363 This feature enables 4KB pages support.
365 config ARM64_64K_PAGES
368 This feature enables 64KB pages support (4KB by default)
369 allowing only two levels of page tables and faster TLB
370 look-up. AArch32 emulation is not available when this feature
376 prompt "Virtual address space size"
377 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
378 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
380 Allows choosing one of multiple possible virtual address
381 space sizes. The level of translation table is determined by
382 a combination of page size and virtual address space size.
384 config ARM64_VA_BITS_39
386 depends on ARM64_4K_PAGES
388 config ARM64_VA_BITS_42
390 depends on ARM64_64K_PAGES
392 config ARM64_VA_BITS_48
399 default 39 if ARM64_VA_BITS_39
400 default 42 if ARM64_VA_BITS_42
401 default 48 if ARM64_VA_BITS_48
403 config CPU_BIG_ENDIAN
404 bool "Build big-endian kernel"
406 Say Y if you plan on running a kernel in big-endian mode.
409 bool "Multi-core scheduler support"
411 Multi-core scheduler support improves the CPU scheduler's decision
412 making when dealing with multi-core CPU chips at a cost of slightly
413 increased overhead in some places. If unsure say N here.
416 bool "SMT scheduler support"
418 Improves the CPU scheduler's decision making when dealing with
419 MultiThreading at a cost of slightly increased overhead in some
420 places. If unsure say N here.
423 int "Maximum number of CPUs (2-4096)"
425 # These have to remain sorted largest to smallest
429 bool "Support for hot-pluggable CPUs"
431 Say Y here to experiment with turning CPUs off and on. CPUs
432 can be controlled through /sys/devices/system/cpu.
434 source kernel/Kconfig.preempt
440 config ARCH_HAS_HOLES_MEMORYMODEL
441 def_bool y if SPARSEMEM
443 config ARCH_SPARSEMEM_ENABLE
445 select SPARSEMEM_VMEMMAP_ENABLE
447 config ARCH_SPARSEMEM_DEFAULT
448 def_bool ARCH_SPARSEMEM_ENABLE
450 config ARCH_SELECT_MEMORY_MODEL
451 def_bool ARCH_SPARSEMEM_ENABLE
453 config HAVE_ARCH_PFN_VALID
454 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
456 config HW_PERF_EVENTS
460 config SYS_SUPPORTS_HUGETLBFS
463 config ARCH_WANT_GENERAL_HUGETLB
466 config ARCH_WANT_HUGE_PMD_SHARE
467 def_bool y if !ARM64_64K_PAGES
469 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
472 config ARCH_HAS_CACHE_LINE_SIZE
478 bool "Enable seccomp to safely compute untrusted bytecode"
480 This kernel feature is useful for number crunching applications
481 that may need to compute untrusted bytecode during their
482 execution. By using pipes or other transports made available to
483 the process as file descriptors supporting the read/write
484 syscalls, it's possible to isolate those applications in
485 their own address space using seccomp. Once seccomp is
486 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
487 and the task is only allowed to execute a few safe syscalls
488 defined by each seccomp mode.
495 bool "Xen guest support on ARM64"
496 depends on ARM64 && OF
499 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
501 config FORCE_MAX_ZONEORDER
503 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
506 menuconfig ARMV8_DEPRECATED
507 bool "Emulate deprecated/obsolete ARMv8 instructions"
510 Legacy software support may require certain instructions
511 that have been deprecated or obsoleted in the architecture.
513 Enable this config to enable selective emulation of these
521 bool "Emulate SWP/SWPB instructions"
523 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
524 they are always undefined. Say Y here to enable software
525 emulation of these instructions for userspace using LDXR/STXR.
527 In some older versions of glibc [<=2.8] SWP is used during futex
528 trylock() operations with the assumption that the code will not
529 be preempted. This invalid assumption may be more likely to fail
530 with SWP emulation enabled, leading to deadlock of the user
533 NOTE: when accessing uncached shared regions, LDXR/STXR rely
534 on an external transaction monitoring block called a global
535 monitor to maintain update atomicity. If your system does not
536 implement a global monitor, this option can cause programs that
537 perform SWP operations to uncached memory to deadlock.
541 config CP15_BARRIER_EMULATION
542 bool "Emulate CP15 Barrier instructions"
544 The CP15 barrier instructions - CP15ISB, CP15DSB, and
545 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
546 strongly recommended to use the ISB, DSB, and DMB
547 instructions instead.
549 Say Y here to enable software emulation of these
550 instructions for AArch32 userspace code. When this option is
551 enabled, CP15 barrier usage is traced which can help
552 identify software that needs updating.
556 config SETEND_EMULATION
557 bool "Emulate SETEND instruction"
559 The SETEND instruction alters the data-endianness of the
560 AArch32 EL0, and is deprecated in ARMv8.
562 Say Y here to enable software emulation of the instruction
563 for AArch32 userspace code.
565 Note: All the cpus on the system must have mixed endian support at EL0
566 for this feature to be enabled. If a new CPU - which doesn't support mixed
567 endian - is hotplugged in after this feature has been enabled, there could
568 be unexpected results in the applications.
573 menu "ARMv8.1 architectural features"
575 config ARM64_HW_AFDBM
576 bool "Support for hardware updates of the Access and Dirty page flags"
579 The ARMv8.1 architecture extensions introduce support for
580 hardware updates of the access and dirty information in page
581 table entries. When enabled in TCR_EL1 (HA and HD bits) on
582 capable processors, accesses to pages with PTE_AF cleared will
583 set this bit instead of raising an access flag fault.
584 Similarly, writes to read-only pages with the DBM bit set will
585 clear the read-only bit (AP[2]) instead of raising a
588 Kernels built with this configuration option enabled continue
589 to work on pre-ARMv8.1 hardware and the performance impact is
590 minimal. If unsure, say Y.
593 bool "Enable support for Privileged Access Never (PAN)"
596 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
597 prevents the kernel or hypervisor from accessing user-space (EL0)
600 Choosing this option will cause any unprotected (not using
601 copy_to_user et al) memory access to fail with a permission fault.
603 The feature is detected at runtime, and will remain as a 'nop'
604 instruction if the cpu does not implement the feature.
606 config ARM64_LSE_ATOMICS
607 bool "Atomic instructions"
609 As part of the Large System Extensions, ARMv8.1 introduces new
610 atomic instructions that are designed specifically to scale in
613 Say Y here to make use of these instructions for the in-kernel
614 atomic routines. This incurs a small overhead on CPUs that do
615 not support these instructions and requires the kernel to be
616 built with binutils >= 2.25.
625 string "Default kernel command string"
628 Provide a set of default command-line options at build time by
629 entering them here. As a minimum, you should specify the the
630 root device (e.g. root=/dev/nfs).
633 bool "Always use the default kernel command string"
635 Always use the default kernel command string, even if the boot
636 loader passes other arguments to the kernel.
637 This is useful if you cannot or don't want to change the
638 command-line options your boot loader passes to the kernel.
644 bool "UEFI runtime support"
645 depends on OF && !CPU_BIG_ENDIAN
648 select EFI_PARAMS_FROM_FDT
649 select EFI_RUNTIME_WRAPPERS
654 This option provides support for runtime services provided
655 by UEFI firmware (such as non-volatile variables, realtime
656 clock, and platform reset). A UEFI stub is also provided to
657 allow the kernel to be booted as an EFI application. This
658 is only useful on systems that have UEFI firmware.
661 bool "Enable support for SMBIOS (DMI) tables"
665 This enables SMBIOS/DMI feature for systems.
667 This option is only useful on systems that have UEFI firmware.
668 However, even with this option, the resultant kernel should
669 continue to boot on existing non-UEFI platforms.
673 menu "Userspace binary formats"
675 source "fs/Kconfig.binfmt"
678 bool "Kernel support for 32-bit EL0"
679 depends on !ARM64_64K_PAGES || EXPERT
680 select COMPAT_BINFMT_ELF
682 select OLD_SIGSUSPEND3
683 select COMPAT_OLD_SIGACTION
685 This option enables support for a 32-bit EL0 running under a 64-bit
686 kernel at EL1. AArch32-specific components such as system calls,
687 the user helper functions, VFP support and the ptrace interface are
688 handled appropriately by the kernel.
690 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
691 will only be able to execute AArch32 binaries that were compiled with
692 64k aligned segments.
694 If you want to execute 32-bit userspace applications, say Y.
696 config SYSVIPC_COMPAT
698 depends on COMPAT && SYSVIPC
702 menu "Power management options"
704 source "kernel/power/Kconfig"
706 config ARCH_SUSPEND_POSSIBLE
711 menu "CPU Power Management"
713 source "drivers/cpuidle/Kconfig"
715 source "drivers/cpufreq/Kconfig"
721 source "drivers/Kconfig"
723 source "drivers/firmware/Kconfig"
725 source "drivers/acpi/Kconfig"
729 source "arch/arm64/kvm/Kconfig"
731 source "arch/arm64/Kconfig.debug"
733 source "security/Kconfig"
735 source "crypto/Kconfig"
737 source "arch/arm64/crypto/Kconfig"