3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_GCOV_PROFILE_ALL
16 select ARCH_HAS_GIGANTIC_PAGE
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_SG_CHAIN
20 select ARCH_HAS_STRICT_KERNEL_RWX
21 select ARCH_HAS_STRICT_MODULE_RWX
22 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
23 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
24 select ARCH_USE_CMPXCHG_LOCKREF
25 select ARCH_SUPPORTS_MEMORY_FAILURE
26 select ARCH_SUPPORTS_ATOMIC_RMW
27 select ARCH_SUPPORTS_NUMA_BALANCING
28 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
29 select ARCH_WANT_FRAME_POINTERS
30 select ARCH_HAS_UBSAN_SANITIZE_ALL
34 select AUDIT_ARCH_COMPAT_GENERIC
35 select ARM_GIC_V2M if PCI
37 select ARM_GIC_V3_ITS if PCI
39 select BUILDTIME_EXTABLE_SORT
40 select CLONE_BACKWARDS
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select DCACHE_WORD_ACCESS
46 select GENERIC_ALLOCATOR
47 select GENERIC_ARCH_TOPOLOGY
48 select GENERIC_CLOCKEVENTS
49 select GENERIC_CLOCKEVENTS_BROADCAST
50 select GENERIC_CPU_AUTOPROBE
51 select GENERIC_EARLY_IOREMAP
52 select GENERIC_IDLE_POLL_SETUP
53 select GENERIC_IRQ_PROBE
54 select GENERIC_IRQ_SHOW
55 select GENERIC_IRQ_SHOW_LEVEL
56 select GENERIC_PCI_IOMAP
57 select GENERIC_SCHED_CLOCK
58 select GENERIC_SMP_IDLE_THREAD
59 select GENERIC_STRNCPY_FROM_USER
60 select GENERIC_STRNLEN_USER
61 select GENERIC_TIME_VSYSCALL
62 select HANDLE_DOMAIN_IRQ
63 select HARDIRQS_SW_RESEND
64 select HAVE_ACPI_APEI if (ACPI && EFI)
65 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
66 select HAVE_ARCH_AUDITSYSCALL
67 select HAVE_ARCH_BITREVERSE
68 select HAVE_ARCH_HUGE_VMAP
69 select HAVE_ARCH_JUMP_LABEL
70 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
72 select HAVE_ARCH_MMAP_RND_BITS
73 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
74 select HAVE_ARCH_SECCOMP_FILTER
75 select HAVE_ARCH_TRACEHOOK
76 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
79 select HAVE_C_RECORDMCOUNT
80 select HAVE_CC_STACKPROTECTOR
81 select HAVE_CMPXCHG_DOUBLE
82 select HAVE_CMPXCHG_LOCAL
83 select HAVE_CONTEXT_TRACKING
84 select HAVE_DEBUG_BUGVERBOSE
85 select HAVE_DEBUG_KMEMLEAK
86 select HAVE_DMA_API_DEBUG
87 select HAVE_DMA_CONTIGUOUS
88 select HAVE_DYNAMIC_FTRACE
89 select HAVE_EFFICIENT_UNALIGNED_ACCESS
90 select HAVE_FTRACE_MCOUNT_RECORD
91 select HAVE_FUNCTION_TRACER
92 select HAVE_FUNCTION_GRAPH_TRACER
93 select HAVE_GCC_PLUGINS
94 select HAVE_GENERIC_DMA_COHERENT
95 select HAVE_HW_BREAKPOINT if PERF_EVENTS
96 select HAVE_IRQ_TIME_ACCOUNTING
98 select HAVE_MEMBLOCK_NODE_MAP if NUMA
99 select HAVE_NMI if ACPI_APEI_SEA
100 select HAVE_PATA_PLATFORM
101 select HAVE_PERF_EVENTS
102 select HAVE_PERF_REGS
103 select HAVE_PERF_USER_STACK_DUMP
104 select HAVE_REGS_AND_STACK_ACCESS_API
105 select HAVE_RCU_TABLE_FREE
106 select HAVE_SYSCALL_TRACEPOINTS
108 select HAVE_KRETPROBES
109 select IOMMU_DMA if IOMMU_SUPPORT
111 select IRQ_FORCED_THREADING
112 select MODULES_USE_ELF_RELA
115 select OF_EARLY_FLATTREE
116 select OF_RESERVED_MEM
117 select PCI_ECAM if ACPI
121 select SYSCTL_EXCEPTION_TRACE
122 select THREAD_INFO_IN_TASK
124 ARM 64-bit (AArch64) Linux support.
129 config ARCH_PHYS_ADDR_T_64BIT
135 config ARM64_PAGE_SHIFT
137 default 16 if ARM64_64K_PAGES
138 default 14 if ARM64_16K_PAGES
141 config ARM64_CONT_SHIFT
143 default 5 if ARM64_64K_PAGES
144 default 7 if ARM64_16K_PAGES
147 config ARCH_MMAP_RND_BITS_MIN
148 default 14 if ARM64_64K_PAGES
149 default 16 if ARM64_16K_PAGES
152 # max bits determined by the following formula:
153 # VA_BITS - PAGE_SHIFT - 3
154 config ARCH_MMAP_RND_BITS_MAX
155 default 19 if ARM64_VA_BITS=36
156 default 24 if ARM64_VA_BITS=39
157 default 27 if ARM64_VA_BITS=42
158 default 30 if ARM64_VA_BITS=47
159 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
160 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
161 default 33 if ARM64_VA_BITS=48
162 default 14 if ARM64_64K_PAGES
163 default 16 if ARM64_16K_PAGES
166 config ARCH_MMAP_RND_COMPAT_BITS_MIN
167 default 7 if ARM64_64K_PAGES
168 default 9 if ARM64_16K_PAGES
171 config ARCH_MMAP_RND_COMPAT_BITS_MAX
177 config STACKTRACE_SUPPORT
180 config ILLEGAL_POINTER_VALUE
182 default 0xdead000000000000
184 config LOCKDEP_SUPPORT
187 config TRACE_IRQFLAGS_SUPPORT
190 config RWSEM_XCHGADD_ALGORITHM
197 config GENERIC_BUG_RELATIVE_POINTERS
199 depends on GENERIC_BUG
201 config GENERIC_HWEIGHT
207 config GENERIC_CALIBRATE_DELAY
213 config HAVE_GENERIC_GUP
216 config ARCH_DMA_ADDR_T_64BIT
219 config NEED_DMA_MAP_STATE
222 config NEED_SG_DMA_LENGTH
234 config KERNEL_MODE_NEON
237 config FIX_EARLYCON_MEM
240 config PGTABLE_LEVELS
242 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
243 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
244 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
245 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
246 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
247 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
249 config ARCH_SUPPORTS_UPROBES
252 config ARCH_PROC_KCORE_TEXT
255 source "init/Kconfig"
257 source "kernel/Kconfig.freezer"
259 source "arch/arm64/Kconfig.platforms"
266 This feature enables support for PCI bus system. If you say Y
267 here, the kernel will include drivers and infrastructure code
268 to support PCI bus devices.
273 config PCI_DOMAINS_GENERIC
279 source "drivers/pci/Kconfig"
283 menu "Kernel Features"
285 menu "ARM errata workarounds via the alternatives framework"
287 config ARM64_ERRATUM_826319
288 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
291 This option adds an alternative code sequence to work around ARM
292 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
293 AXI master interface and an L2 cache.
295 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
296 and is unable to accept a certain write via this interface, it will
297 not progress on read data presented on the read data channel and the
300 The workaround promotes data cache clean instructions to
301 data cache clean-and-invalidate.
302 Please note that this does not necessarily enable the workaround,
303 as it depends on the alternative framework, which will only patch
304 the kernel if an affected CPU is detected.
308 config ARM64_ERRATUM_827319
309 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
312 This option adds an alternative code sequence to work around ARM
313 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
314 master interface and an L2 cache.
316 Under certain conditions this erratum can cause a clean line eviction
317 to occur at the same time as another transaction to the same address
318 on the AMBA 5 CHI interface, which can cause data corruption if the
319 interconnect reorders the two transactions.
321 The workaround promotes data cache clean instructions to
322 data cache clean-and-invalidate.
323 Please note that this does not necessarily enable the workaround,
324 as it depends on the alternative framework, which will only patch
325 the kernel if an affected CPU is detected.
329 config ARM64_ERRATUM_824069
330 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
333 This option adds an alternative code sequence to work around ARM
334 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
335 to a coherent interconnect.
337 If a Cortex-A53 processor is executing a store or prefetch for
338 write instruction at the same time as a processor in another
339 cluster is executing a cache maintenance operation to the same
340 address, then this erratum might cause a clean cache line to be
341 incorrectly marked as dirty.
343 The workaround promotes data cache clean instructions to
344 data cache clean-and-invalidate.
345 Please note that this option does not necessarily enable the
346 workaround, as it depends on the alternative framework, which will
347 only patch the kernel if an affected CPU is detected.
351 config ARM64_ERRATUM_819472
352 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
355 This option adds an alternative code sequence to work around ARM
356 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
357 present when it is connected to a coherent interconnect.
359 If the processor is executing a load and store exclusive sequence at
360 the same time as a processor in another cluster is executing a cache
361 maintenance operation to the same address, then this erratum might
362 cause data corruption.
364 The workaround promotes data cache clean instructions to
365 data cache clean-and-invalidate.
366 Please note that this does not necessarily enable the workaround,
367 as it depends on the alternative framework, which will only patch
368 the kernel if an affected CPU is detected.
372 config ARM64_ERRATUM_832075
373 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
376 This option adds an alternative code sequence to work around ARM
377 erratum 832075 on Cortex-A57 parts up to r1p2.
379 Affected Cortex-A57 parts might deadlock when exclusive load/store
380 instructions to Write-Back memory are mixed with Device loads.
382 The workaround is to promote device loads to use Load-Acquire
384 Please note that this does not necessarily enable the workaround,
385 as it depends on the alternative framework, which will only patch
386 the kernel if an affected CPU is detected.
390 config ARM64_ERRATUM_834220
391 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
395 This option adds an alternative code sequence to work around ARM
396 erratum 834220 on Cortex-A57 parts up to r1p2.
398 Affected Cortex-A57 parts might report a Stage 2 translation
399 fault as the result of a Stage 1 fault for load crossing a
400 page boundary when there is a permission or device memory
401 alignment fault at Stage 1 and a translation fault at Stage 2.
403 The workaround is to verify that the Stage 1 translation
404 doesn't generate a fault before handling the Stage 2 fault.
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
411 config ARM64_ERRATUM_845719
412 bool "Cortex-A53: 845719: a load might read incorrect data"
416 This option adds an alternative code sequence to work around ARM
417 erratum 845719 on Cortex-A53 parts up to r0p4.
419 When running a compat (AArch32) userspace on an affected Cortex-A53
420 part, a load at EL0 from a virtual address that matches the bottom 32
421 bits of the virtual address used by a recent load at (AArch64) EL1
422 might return incorrect data.
424 The workaround is to write the contextidr_el1 register on exception
425 return to a 32-bit task.
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_843419
433 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
435 select ARM64_MODULE_CMODEL_LARGE if MODULES
437 This option links the kernel with '--fix-cortex-a53-843419' and
438 builds modules using the large memory model in order to avoid the use
439 of the ADRP instruction, which can cause a subsequent memory access
440 to use an incorrect address on Cortex-A53 parts up to r0p4.
444 config CAVIUM_ERRATUM_22375
445 bool "Cavium erratum 22375, 24313"
448 Enable workaround for erratum 22375, 24313.
450 This implements two gicv3-its errata workarounds for ThunderX. Both
451 with small impact affecting only ITS table allocation.
453 erratum 22375: only alloc 8MB table size
454 erratum 24313: ignore memory access type
456 The fixes are in ITS initialization and basically ignore memory access
457 type and table size provided by the TYPER and BASER registers.
461 config CAVIUM_ERRATUM_23144
462 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
466 ITS SYNC command hang for cross node io and collections/cpu mapping.
470 config CAVIUM_ERRATUM_23154
471 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
474 The gicv3 of ThunderX requires a modified version for
475 reading the IAR status to ensure data synchronization
476 (access to icc_iar1_el1 is not sync'ed before and after).
480 config CAVIUM_ERRATUM_27456
481 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
484 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
485 instructions may cause the icache to become corrupted if it
486 contains data for a non-current ASID. The fix is to
487 invalidate the icache when changing the mm context.
491 config QCOM_FALKOR_ERRATUM_1003
492 bool "Falkor E1003: Incorrect translation due to ASID change"
494 select ARM64_PAN if ARM64_SW_TTBR0_PAN
496 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
497 and BADDR are changed together in TTBRx_EL1. The workaround for this
498 issue is to use a reserved ASID in cpu_do_switch_mm() before
499 switching to the new ASID. Saying Y here selects ARM64_PAN if
500 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
501 maintaining the E1003 workaround in the software PAN emulation code
502 would be an unnecessary complication. The affected Falkor v1 CPU
503 implements ARMv8.1 hardware PAN support and using hardware PAN
504 support versus software PAN emulation is mutually exclusive at
509 config QCOM_FALKOR_ERRATUM_1009
510 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
513 On Falkor v1, the CPU may prematurely complete a DSB following a
514 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
515 one more time to fix the issue.
519 config QCOM_QDF2400_ERRATUM_0065
520 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
523 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
524 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
525 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
534 default ARM64_4K_PAGES
536 Page size (translation granule) configuration.
538 config ARM64_4K_PAGES
541 This feature enables 4KB pages support.
543 config ARM64_16K_PAGES
546 The system will use 16KB pages support. AArch32 emulation
547 requires applications compiled with 16K (or a multiple of 16K)
550 config ARM64_64K_PAGES
553 This feature enables 64KB pages support (4KB by default)
554 allowing only two levels of page tables and faster TLB
555 look-up. AArch32 emulation requires applications compiled
556 with 64K aligned segments.
561 prompt "Virtual address space size"
562 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
563 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
564 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
566 Allows choosing one of multiple possible virtual address
567 space sizes. The level of translation table is determined by
568 a combination of page size and virtual address space size.
570 config ARM64_VA_BITS_36
571 bool "36-bit" if EXPERT
572 depends on ARM64_16K_PAGES
574 config ARM64_VA_BITS_39
576 depends on ARM64_4K_PAGES
578 config ARM64_VA_BITS_42
580 depends on ARM64_64K_PAGES
582 config ARM64_VA_BITS_47
584 depends on ARM64_16K_PAGES
586 config ARM64_VA_BITS_48
593 default 36 if ARM64_VA_BITS_36
594 default 39 if ARM64_VA_BITS_39
595 default 42 if ARM64_VA_BITS_42
596 default 47 if ARM64_VA_BITS_47
597 default 48 if ARM64_VA_BITS_48
599 config CPU_BIG_ENDIAN
600 bool "Build big-endian kernel"
602 Say Y if you plan on running a kernel in big-endian mode.
605 bool "Multi-core scheduler support"
607 Multi-core scheduler support improves the CPU scheduler's decision
608 making when dealing with multi-core CPU chips at a cost of slightly
609 increased overhead in some places. If unsure say N here.
612 bool "SMT scheduler support"
614 Improves the CPU scheduler's decision making when dealing with
615 MultiThreading at a cost of slightly increased overhead in some
616 places. If unsure say N here.
619 int "Maximum number of CPUs (2-4096)"
621 # These have to remain sorted largest to smallest
625 bool "Support for hot-pluggable CPUs"
626 select GENERIC_IRQ_MIGRATION
628 Say Y here to experiment with turning CPUs off and on. CPUs
629 can be controlled through /sys/devices/system/cpu.
631 # Common NUMA Features
633 bool "Numa Memory Allocation and Scheduler Support"
634 select ACPI_NUMA if ACPI
637 Enable NUMA (Non Uniform Memory Access) support.
639 The kernel will try to allocate memory used by a CPU on the
640 local memory of the CPU and add some more
641 NUMA awareness to the kernel.
644 int "Maximum NUMA Nodes (as a power of 2)"
647 depends on NEED_MULTIPLE_NODES
649 Specify the maximum number of NUMA Nodes available on the target
650 system. Increases memory reserved to accommodate various tables.
652 config USE_PERCPU_NUMA_NODE_ID
656 config HAVE_SETUP_PER_CPU_AREA
660 config NEED_PER_CPU_EMBED_FIRST_CHUNK
668 source kernel/Kconfig.preempt
669 source kernel/Kconfig.hz
671 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
674 config ARCH_HAS_HOLES_MEMORYMODEL
675 def_bool y if SPARSEMEM
677 config ARCH_SPARSEMEM_ENABLE
679 select SPARSEMEM_VMEMMAP_ENABLE
681 config ARCH_SPARSEMEM_DEFAULT
682 def_bool ARCH_SPARSEMEM_ENABLE
684 config ARCH_SELECT_MEMORY_MODEL
685 def_bool ARCH_SPARSEMEM_ENABLE
687 config HAVE_ARCH_PFN_VALID
688 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
690 config HW_PERF_EVENTS
694 config SYS_SUPPORTS_HUGETLBFS
697 config ARCH_WANT_HUGE_PMD_SHARE
698 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
700 config ARCH_HAS_CACHE_LINE_SIZE
706 bool "Enable seccomp to safely compute untrusted bytecode"
708 This kernel feature is useful for number crunching applications
709 that may need to compute untrusted bytecode during their
710 execution. By using pipes or other transports made available to
711 the process as file descriptors supporting the read/write
712 syscalls, it's possible to isolate those applications in
713 their own address space using seccomp. Once seccomp is
714 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
715 and the task is only allowed to execute a few safe syscalls
716 defined by each seccomp mode.
719 bool "Enable paravirtualization code"
721 This changes the kernel so it can modify itself when it is run
722 under a hypervisor, potentially improving performance significantly
723 over full virtualization.
725 config PARAVIRT_TIME_ACCOUNTING
726 bool "Paravirtual steal time accounting"
730 Select this option to enable fine granularity task steal time
731 accounting. Time spent executing other tasks in parallel with
732 the current vCPU is discounted from the vCPU power. To account for
733 that, there can be a small performance impact.
735 If in doubt, say N here.
738 depends on PM_SLEEP_SMP
740 bool "kexec system call"
742 kexec is a system call that implements the ability to shutdown your
743 current kernel, and to start another kernel. It is like a reboot
744 but it is independent of the system firmware. And like a reboot
745 you can start any kernel with it, not just Linux.
748 bool "Build kdump crash kernel"
750 Generate crash dump after being started by kexec. This should
751 be normally only set in special crash dump kernels which are
752 loaded in the main kernel with kexec-tools into a specially
753 reserved region and then later executed after a crash by
756 For more details see Documentation/kdump/kdump.txt
763 bool "Xen guest support on ARM64"
764 depends on ARM64 && OF
768 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
770 config FORCE_MAX_ZONEORDER
772 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
773 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
776 The kernel memory allocator divides physically contiguous memory
777 blocks into "zones", where each zone is a power of two number of
778 pages. This option selects the largest power of two that the kernel
779 keeps in the memory allocator. If you need to allocate very large
780 blocks of physically contiguous memory, then you may need to
783 This config option is actually maximum order plus one. For example,
784 a value of 11 means that the largest free memory block is 2^10 pages.
786 We make sure that we can allocate upto a HugePage size for each configuration.
788 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
790 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
791 4M allocations matching the default size used by generic code.
793 menuconfig ARMV8_DEPRECATED
794 bool "Emulate deprecated/obsolete ARMv8 instructions"
797 Legacy software support may require certain instructions
798 that have been deprecated or obsoleted in the architecture.
800 Enable this config to enable selective emulation of these
808 bool "Emulate SWP/SWPB instructions"
810 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
811 they are always undefined. Say Y here to enable software
812 emulation of these instructions for userspace using LDXR/STXR.
814 In some older versions of glibc [<=2.8] SWP is used during futex
815 trylock() operations with the assumption that the code will not
816 be preempted. This invalid assumption may be more likely to fail
817 with SWP emulation enabled, leading to deadlock of the user
820 NOTE: when accessing uncached shared regions, LDXR/STXR rely
821 on an external transaction monitoring block called a global
822 monitor to maintain update atomicity. If your system does not
823 implement a global monitor, this option can cause programs that
824 perform SWP operations to uncached memory to deadlock.
828 config CP15_BARRIER_EMULATION
829 bool "Emulate CP15 Barrier instructions"
831 The CP15 barrier instructions - CP15ISB, CP15DSB, and
832 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
833 strongly recommended to use the ISB, DSB, and DMB
834 instructions instead.
836 Say Y here to enable software emulation of these
837 instructions for AArch32 userspace code. When this option is
838 enabled, CP15 barrier usage is traced which can help
839 identify software that needs updating.
843 config SETEND_EMULATION
844 bool "Emulate SETEND instruction"
846 The SETEND instruction alters the data-endianness of the
847 AArch32 EL0, and is deprecated in ARMv8.
849 Say Y here to enable software emulation of the instruction
850 for AArch32 userspace code.
852 Note: All the cpus on the system must have mixed endian support at EL0
853 for this feature to be enabled. If a new CPU - which doesn't support mixed
854 endian - is hotplugged in after this feature has been enabled, there could
855 be unexpected results in the applications.
860 config ARM64_SW_TTBR0_PAN
861 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
863 Enabling this option prevents the kernel from accessing
864 user-space memory directly by pointing TTBR0_EL1 to a reserved
865 zeroed area and reserved ASID. The user access routines
866 restore the valid TTBR0_EL1 temporarily.
868 menu "ARMv8.1 architectural features"
870 config ARM64_HW_AFDBM
871 bool "Support for hardware updates of the Access and Dirty page flags"
874 The ARMv8.1 architecture extensions introduce support for
875 hardware updates of the access and dirty information in page
876 table entries. When enabled in TCR_EL1 (HA and HD bits) on
877 capable processors, accesses to pages with PTE_AF cleared will
878 set this bit instead of raising an access flag fault.
879 Similarly, writes to read-only pages with the DBM bit set will
880 clear the read-only bit (AP[2]) instead of raising a
883 Kernels built with this configuration option enabled continue
884 to work on pre-ARMv8.1 hardware and the performance impact is
885 minimal. If unsure, say Y.
888 bool "Enable support for Privileged Access Never (PAN)"
891 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
892 prevents the kernel or hypervisor from accessing user-space (EL0)
895 Choosing this option will cause any unprotected (not using
896 copy_to_user et al) memory access to fail with a permission fault.
898 The feature is detected at runtime, and will remain as a 'nop'
899 instruction if the cpu does not implement the feature.
901 config ARM64_LSE_ATOMICS
902 bool "Atomic instructions"
904 As part of the Large System Extensions, ARMv8.1 introduces new
905 atomic instructions that are designed specifically to scale in
908 Say Y here to make use of these instructions for the in-kernel
909 atomic routines. This incurs a small overhead on CPUs that do
910 not support these instructions and requires the kernel to be
911 built with binutils >= 2.25.
914 bool "Enable support for Virtualization Host Extensions (VHE)"
917 Virtualization Host Extensions (VHE) allow the kernel to run
918 directly at EL2 (instead of EL1) on processors that support
919 it. This leads to better performance for KVM, as they reduce
920 the cost of the world switch.
922 Selecting this option allows the VHE feature to be detected
923 at runtime, and does not affect processors that do not
924 implement this feature.
928 menu "ARMv8.2 architectural features"
931 bool "Enable support for User Access Override (UAO)"
934 User Access Override (UAO; part of the ARMv8.2 Extensions)
935 causes the 'unprivileged' variant of the load/store instructions to
936 be overriden to be privileged.
938 This option changes get_user() and friends to use the 'unprivileged'
939 variant of the load/store instructions. This ensures that user-space
940 really did have access to the supplied memory. When addr_limit is
941 set to kernel memory the UAO bit will be set, allowing privileged
942 access to kernel memory.
944 Choosing this option will cause copy_to_user() et al to use user-space
947 The feature is detected at runtime, the kernel will use the
948 regular load/store instructions if the cpu does not implement the
953 config ARM64_MODULE_CMODEL_LARGE
956 config ARM64_MODULE_PLTS
958 select ARM64_MODULE_CMODEL_LARGE
959 select HAVE_MOD_ARCH_SPECIFIC
964 This builds the kernel as a Position Independent Executable (PIE),
965 which retains all relocation metadata required to relocate the
966 kernel binary at runtime to a different virtual address than the
967 address it was linked at.
968 Since AArch64 uses the RELA relocation format, this requires a
969 relocation pass at runtime even if the kernel is loaded at the
970 same address it was linked at.
972 config RANDOMIZE_BASE
973 bool "Randomize the address of the kernel image"
974 select ARM64_MODULE_PLTS if MODULES
977 Randomizes the virtual address at which the kernel image is
978 loaded, as a security feature that deters exploit attempts
979 relying on knowledge of the location of kernel internals.
981 It is the bootloader's job to provide entropy, by passing a
982 random u64 value in /chosen/kaslr-seed at kernel entry.
984 When booting via the UEFI stub, it will invoke the firmware's
985 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
986 to the kernel proper. In addition, it will randomise the physical
987 location of the kernel Image as well.
991 config RANDOMIZE_MODULE_REGION_FULL
992 bool "Randomize the module region independently from the core kernel"
993 depends on RANDOMIZE_BASE
996 Randomizes the location of the module region without considering the
997 location of the core kernel. This way, it is impossible for modules
998 to leak information about the location of core kernel data structures
999 but it does imply that function calls between modules and the core
1000 kernel will need to be resolved via veneers in the module PLT.
1002 When this option is not set, the module region will be randomized over
1003 a limited range that contains the [_stext, _etext] interval of the
1004 core kernel, so branch relocations are always in range.
1010 config ARM64_ACPI_PARKING_PROTOCOL
1011 bool "Enable support for the ARM64 ACPI parking protocol"
1014 Enable support for the ARM64 ACPI parking protocol. If disabled
1015 the kernel will not allow booting through the ARM64 ACPI parking
1016 protocol even if the corresponding data is present in the ACPI
1020 string "Default kernel command string"
1023 Provide a set of default command-line options at build time by
1024 entering them here. As a minimum, you should specify the the
1025 root device (e.g. root=/dev/nfs).
1027 config CMDLINE_FORCE
1028 bool "Always use the default kernel command string"
1030 Always use the default kernel command string, even if the boot
1031 loader passes other arguments to the kernel.
1032 This is useful if you cannot or don't want to change the
1033 command-line options your boot loader passes to the kernel.
1039 bool "UEFI runtime support"
1040 depends on OF && !CPU_BIG_ENDIAN
1043 select EFI_PARAMS_FROM_FDT
1044 select EFI_RUNTIME_WRAPPERS
1049 This option provides support for runtime services provided
1050 by UEFI firmware (such as non-volatile variables, realtime
1051 clock, and platform reset). A UEFI stub is also provided to
1052 allow the kernel to be booted as an EFI application. This
1053 is only useful on systems that have UEFI firmware.
1056 bool "Enable support for SMBIOS (DMI) tables"
1060 This enables SMBIOS/DMI feature for systems.
1062 This option is only useful on systems that have UEFI firmware.
1063 However, even with this option, the resultant kernel should
1064 continue to boot on existing non-UEFI platforms.
1068 menu "Userspace binary formats"
1070 source "fs/Kconfig.binfmt"
1073 bool "Kernel support for 32-bit EL0"
1074 depends on ARM64_4K_PAGES || EXPERT
1075 select COMPAT_BINFMT_ELF if BINFMT_ELF
1077 select OLD_SIGSUSPEND3
1078 select COMPAT_OLD_SIGACTION
1080 This option enables support for a 32-bit EL0 running under a 64-bit
1081 kernel at EL1. AArch32-specific components such as system calls,
1082 the user helper functions, VFP support and the ptrace interface are
1083 handled appropriately by the kernel.
1085 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1086 that you will only be able to execute AArch32 binaries that were compiled
1087 with page size aligned segments.
1089 If you want to execute 32-bit userspace applications, say Y.
1091 config SYSVIPC_COMPAT
1093 depends on COMPAT && SYSVIPC
1097 menu "Power management options"
1099 source "kernel/power/Kconfig"
1101 config ARCH_HIBERNATION_POSSIBLE
1105 config ARCH_HIBERNATION_HEADER
1107 depends on HIBERNATION
1109 config ARCH_SUSPEND_POSSIBLE
1114 menu "CPU Power Management"
1116 source "drivers/cpuidle/Kconfig"
1118 source "drivers/cpufreq/Kconfig"
1122 source "net/Kconfig"
1124 source "drivers/Kconfig"
1126 source "drivers/firmware/Kconfig"
1128 source "drivers/acpi/Kconfig"
1132 source "arch/arm64/kvm/Kconfig"
1134 source "arch/arm64/Kconfig.debug"
1136 source "security/Kconfig"
1138 source "crypto/Kconfig"
1140 source "arch/arm64/crypto/Kconfig"
1143 source "lib/Kconfig"