3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
7 select ACPI_MCFG if ACPI
8 select ACPI_SPCR_TABLE if ACPI
9 select ARCH_CLOCKSOURCE_DATA
10 select ARCH_HAS_DEVMEM_IS_ALLOWED
11 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
12 select ARCH_HAS_ELF_RANDOMIZE
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_HAS_GIGANTIC_PAGE
16 select ARCH_HAS_SG_CHAIN
17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
18 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
19 select ARCH_USE_CMPXCHG_LOCKREF
20 select ARCH_SUPPORTS_ATOMIC_RMW
21 select ARCH_SUPPORTS_NUMA_BALANCING
22 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
23 select ARCH_WANT_FRAME_POINTERS
24 select ARCH_HAS_UBSAN_SANITIZE_ALL
28 select AUDIT_ARCH_COMPAT_GENERIC
29 select ARM_GIC_V2M if PCI
31 select ARM_GIC_V3_ITS if PCI
33 select BUILDTIME_EXTABLE_SORT
34 select CLONE_BACKWARDS
36 select CPU_PM if (SUSPEND || CPU_IDLE)
37 select DCACHE_WORD_ACCESS
40 select GENERIC_ALLOCATOR
41 select GENERIC_CLOCKEVENTS
42 select GENERIC_CLOCKEVENTS_BROADCAST
43 select GENERIC_CPU_AUTOPROBE
44 select GENERIC_EARLY_IOREMAP
45 select GENERIC_IDLE_POLL_SETUP
46 select GENERIC_IRQ_PROBE
47 select GENERIC_IRQ_SHOW
48 select GENERIC_IRQ_SHOW_LEVEL
49 select GENERIC_PCI_IOMAP
50 select GENERIC_SCHED_CLOCK
51 select GENERIC_SMP_IDLE_THREAD
52 select GENERIC_STRNCPY_FROM_USER
53 select GENERIC_STRNLEN_USER
54 select GENERIC_TIME_VSYSCALL
55 select HANDLE_DOMAIN_IRQ
56 select HARDIRQS_SW_RESEND
57 select HAVE_ACPI_APEI if (ACPI && EFI)
58 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
59 select HAVE_ARCH_AUDITSYSCALL
60 select HAVE_ARCH_BITREVERSE
61 select HAVE_ARCH_HARDENED_USERCOPY
62 select HAVE_ARCH_HUGE_VMAP
63 select HAVE_ARCH_JUMP_LABEL
64 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
66 select HAVE_ARCH_MMAP_RND_BITS
67 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
68 select HAVE_ARCH_SECCOMP_FILTER
69 select HAVE_ARCH_TRACEHOOK
70 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
73 select HAVE_C_RECORDMCOUNT
74 select HAVE_CC_STACKPROTECTOR
75 select HAVE_CMPXCHG_DOUBLE
76 select HAVE_CMPXCHG_LOCAL
77 select HAVE_CONTEXT_TRACKING
78 select HAVE_DEBUG_BUGVERBOSE
79 select HAVE_DEBUG_KMEMLEAK
80 select HAVE_DMA_API_DEBUG
81 select HAVE_DMA_CONTIGUOUS
82 select HAVE_DYNAMIC_FTRACE
83 select HAVE_EFFICIENT_UNALIGNED_ACCESS
84 select HAVE_FTRACE_MCOUNT_RECORD
85 select HAVE_FUNCTION_TRACER
86 select HAVE_FUNCTION_GRAPH_TRACER
87 select HAVE_GCC_PLUGINS
88 select HAVE_GENERIC_DMA_COHERENT
89 select HAVE_HW_BREAKPOINT if PERF_EVENTS
90 select HAVE_IRQ_TIME_ACCOUNTING
92 select HAVE_MEMBLOCK_NODE_MAP if NUMA
93 select HAVE_NMI if ACPI_APEI_SEA
94 select HAVE_PATA_PLATFORM
95 select HAVE_PERF_EVENTS
97 select HAVE_PERF_USER_STACK_DUMP
98 select HAVE_REGS_AND_STACK_ACCESS_API
99 select HAVE_RCU_TABLE_FREE
100 select HAVE_SYSCALL_TRACEPOINTS
102 select HAVE_KRETPROBES if HAVE_KPROBES
103 select IOMMU_DMA if IOMMU_SUPPORT
105 select IRQ_FORCED_THREADING
106 select MODULES_USE_ELF_RELA
109 select OF_EARLY_FLATTREE
110 select OF_RESERVED_MEM
111 select PCI_ECAM if ACPI
115 select SYSCTL_EXCEPTION_TRACE
116 select THREAD_INFO_IN_TASK
118 ARM 64-bit (AArch64) Linux support.
123 config ARCH_PHYS_ADDR_T_64BIT
132 config ARM64_PAGE_SHIFT
134 default 16 if ARM64_64K_PAGES
135 default 14 if ARM64_16K_PAGES
138 config ARM64_CONT_SHIFT
140 default 5 if ARM64_64K_PAGES
141 default 7 if ARM64_16K_PAGES
144 config ARCH_MMAP_RND_BITS_MIN
145 default 14 if ARM64_64K_PAGES
146 default 16 if ARM64_16K_PAGES
149 # max bits determined by the following formula:
150 # VA_BITS - PAGE_SHIFT - 3
151 config ARCH_MMAP_RND_BITS_MAX
152 default 19 if ARM64_VA_BITS=36
153 default 24 if ARM64_VA_BITS=39
154 default 27 if ARM64_VA_BITS=42
155 default 30 if ARM64_VA_BITS=47
156 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
157 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
158 default 33 if ARM64_VA_BITS=48
159 default 14 if ARM64_64K_PAGES
160 default 16 if ARM64_16K_PAGES
163 config ARCH_MMAP_RND_COMPAT_BITS_MIN
164 default 7 if ARM64_64K_PAGES
165 default 9 if ARM64_16K_PAGES
168 config ARCH_MMAP_RND_COMPAT_BITS_MAX
174 config STACKTRACE_SUPPORT
177 config ILLEGAL_POINTER_VALUE
179 default 0xdead000000000000
181 config LOCKDEP_SUPPORT
184 config TRACE_IRQFLAGS_SUPPORT
187 config RWSEM_XCHGADD_ALGORITHM
194 config GENERIC_BUG_RELATIVE_POINTERS
196 depends on GENERIC_BUG
198 config GENERIC_HWEIGHT
204 config GENERIC_CALIBRATE_DELAY
210 config HAVE_GENERIC_RCU_GUP
213 config ARCH_DMA_ADDR_T_64BIT
216 config NEED_DMA_MAP_STATE
219 config NEED_SG_DMA_LENGTH
231 config KERNEL_MODE_NEON
234 config FIX_EARLYCON_MEM
237 config PGTABLE_LEVELS
239 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
240 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
241 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
242 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
243 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
244 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
246 config ARCH_SUPPORTS_UPROBES
249 config ARCH_PROC_KCORE_TEXT
252 source "init/Kconfig"
254 source "kernel/Kconfig.freezer"
256 source "arch/arm64/Kconfig.platforms"
263 This feature enables support for PCI bus system. If you say Y
264 here, the kernel will include drivers and infrastructure code
265 to support PCI bus devices.
270 config PCI_DOMAINS_GENERIC
276 source "drivers/pci/Kconfig"
280 menu "Kernel Features"
282 menu "ARM errata workarounds via the alternatives framework"
284 config ARM64_ERRATUM_826319
285 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
288 This option adds an alternative code sequence to work around ARM
289 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
290 AXI master interface and an L2 cache.
292 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
293 and is unable to accept a certain write via this interface, it will
294 not progress on read data presented on the read data channel and the
297 The workaround promotes data cache clean instructions to
298 data cache clean-and-invalidate.
299 Please note that this does not necessarily enable the workaround,
300 as it depends on the alternative framework, which will only patch
301 the kernel if an affected CPU is detected.
305 config ARM64_ERRATUM_827319
306 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
309 This option adds an alternative code sequence to work around ARM
310 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
311 master interface and an L2 cache.
313 Under certain conditions this erratum can cause a clean line eviction
314 to occur at the same time as another transaction to the same address
315 on the AMBA 5 CHI interface, which can cause data corruption if the
316 interconnect reorders the two transactions.
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this does not necessarily enable the workaround,
321 as it depends on the alternative framework, which will only patch
322 the kernel if an affected CPU is detected.
326 config ARM64_ERRATUM_824069
327 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
330 This option adds an alternative code sequence to work around ARM
331 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
332 to a coherent interconnect.
334 If a Cortex-A53 processor is executing a store or prefetch for
335 write instruction at the same time as a processor in another
336 cluster is executing a cache maintenance operation to the same
337 address, then this erratum might cause a clean cache line to be
338 incorrectly marked as dirty.
340 The workaround promotes data cache clean instructions to
341 data cache clean-and-invalidate.
342 Please note that this option does not necessarily enable the
343 workaround, as it depends on the alternative framework, which will
344 only patch the kernel if an affected CPU is detected.
348 config ARM64_ERRATUM_819472
349 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
352 This option adds an alternative code sequence to work around ARM
353 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
354 present when it is connected to a coherent interconnect.
356 If the processor is executing a load and store exclusive sequence at
357 the same time as a processor in another cluster is executing a cache
358 maintenance operation to the same address, then this erratum might
359 cause data corruption.
361 The workaround promotes data cache clean instructions to
362 data cache clean-and-invalidate.
363 Please note that this does not necessarily enable the workaround,
364 as it depends on the alternative framework, which will only patch
365 the kernel if an affected CPU is detected.
369 config ARM64_ERRATUM_832075
370 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
373 This option adds an alternative code sequence to work around ARM
374 erratum 832075 on Cortex-A57 parts up to r1p2.
376 Affected Cortex-A57 parts might deadlock when exclusive load/store
377 instructions to Write-Back memory are mixed with Device loads.
379 The workaround is to promote device loads to use Load-Acquire
381 Please note that this does not necessarily enable the workaround,
382 as it depends on the alternative framework, which will only patch
383 the kernel if an affected CPU is detected.
387 config ARM64_ERRATUM_834220
388 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
392 This option adds an alternative code sequence to work around ARM
393 erratum 834220 on Cortex-A57 parts up to r1p2.
395 Affected Cortex-A57 parts might report a Stage 2 translation
396 fault as the result of a Stage 1 fault for load crossing a
397 page boundary when there is a permission or device memory
398 alignment fault at Stage 1 and a translation fault at Stage 2.
400 The workaround is to verify that the Stage 1 translation
401 doesn't generate a fault before handling the Stage 2 fault.
402 Please note that this does not necessarily enable the workaround,
403 as it depends on the alternative framework, which will only patch
404 the kernel if an affected CPU is detected.
408 config ARM64_ERRATUM_845719
409 bool "Cortex-A53: 845719: a load might read incorrect data"
413 This option adds an alternative code sequence to work around ARM
414 erratum 845719 on Cortex-A53 parts up to r0p4.
416 When running a compat (AArch32) userspace on an affected Cortex-A53
417 part, a load at EL0 from a virtual address that matches the bottom 32
418 bits of the virtual address used by a recent load at (AArch64) EL1
419 might return incorrect data.
421 The workaround is to write the contextidr_el1 register on exception
422 return to a 32-bit task.
423 Please note that this does not necessarily enable the workaround,
424 as it depends on the alternative framework, which will only patch
425 the kernel if an affected CPU is detected.
429 config ARM64_ERRATUM_843419
430 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
432 select ARM64_MODULE_CMODEL_LARGE if MODULES
434 This option links the kernel with '--fix-cortex-a53-843419' and
435 builds modules using the large memory model in order to avoid the use
436 of the ADRP instruction, which can cause a subsequent memory access
437 to use an incorrect address on Cortex-A53 parts up to r0p4.
441 config CAVIUM_ERRATUM_22375
442 bool "Cavium erratum 22375, 24313"
445 Enable workaround for erratum 22375, 24313.
447 This implements two gicv3-its errata workarounds for ThunderX. Both
448 with small impact affecting only ITS table allocation.
450 erratum 22375: only alloc 8MB table size
451 erratum 24313: ignore memory access type
453 The fixes are in ITS initialization and basically ignore memory access
454 type and table size provided by the TYPER and BASER registers.
458 config CAVIUM_ERRATUM_23144
459 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
463 ITS SYNC command hang for cross node io and collections/cpu mapping.
467 config CAVIUM_ERRATUM_23154
468 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
471 The gicv3 of ThunderX requires a modified version for
472 reading the IAR status to ensure data synchronization
473 (access to icc_iar1_el1 is not sync'ed before and after).
477 config CAVIUM_ERRATUM_27456
478 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
481 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
482 instructions may cause the icache to become corrupted if it
483 contains data for a non-current ASID. The fix is to
484 invalidate the icache when changing the mm context.
488 config QCOM_FALKOR_ERRATUM_1003
489 bool "Falkor E1003: Incorrect translation due to ASID change"
491 select ARM64_PAN if ARM64_SW_TTBR0_PAN
493 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
494 and BADDR are changed together in TTBRx_EL1. The workaround for this
495 issue is to use a reserved ASID in cpu_do_switch_mm() before
496 switching to the new ASID. Saying Y here selects ARM64_PAN if
497 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
498 maintaining the E1003 workaround in the software PAN emulation code
499 would be an unnecessary complication. The affected Falkor v1 CPU
500 implements ARMv8.1 hardware PAN support and using hardware PAN
501 support versus software PAN emulation is mutually exclusive at
506 config QCOM_FALKOR_ERRATUM_1009
507 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
510 On Falkor v1, the CPU may prematurely complete a DSB following a
511 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
512 one more time to fix the issue.
516 config QCOM_QDF2400_ERRATUM_0065
517 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
520 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
521 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
522 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
531 default ARM64_4K_PAGES
533 Page size (translation granule) configuration.
535 config ARM64_4K_PAGES
538 This feature enables 4KB pages support.
540 config ARM64_16K_PAGES
543 The system will use 16KB pages support. AArch32 emulation
544 requires applications compiled with 16K (or a multiple of 16K)
547 config ARM64_64K_PAGES
550 This feature enables 64KB pages support (4KB by default)
551 allowing only two levels of page tables and faster TLB
552 look-up. AArch32 emulation requires applications compiled
553 with 64K aligned segments.
558 prompt "Virtual address space size"
559 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
560 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
561 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
563 Allows choosing one of multiple possible virtual address
564 space sizes. The level of translation table is determined by
565 a combination of page size and virtual address space size.
567 config ARM64_VA_BITS_36
568 bool "36-bit" if EXPERT
569 depends on ARM64_16K_PAGES
571 config ARM64_VA_BITS_39
573 depends on ARM64_4K_PAGES
575 config ARM64_VA_BITS_42
577 depends on ARM64_64K_PAGES
579 config ARM64_VA_BITS_47
581 depends on ARM64_16K_PAGES
583 config ARM64_VA_BITS_48
590 default 36 if ARM64_VA_BITS_36
591 default 39 if ARM64_VA_BITS_39
592 default 42 if ARM64_VA_BITS_42
593 default 47 if ARM64_VA_BITS_47
594 default 48 if ARM64_VA_BITS_48
596 config CPU_BIG_ENDIAN
597 bool "Build big-endian kernel"
599 Say Y if you plan on running a kernel in big-endian mode.
602 bool "Multi-core scheduler support"
604 Multi-core scheduler support improves the CPU scheduler's decision
605 making when dealing with multi-core CPU chips at a cost of slightly
606 increased overhead in some places. If unsure say N here.
609 bool "SMT scheduler support"
611 Improves the CPU scheduler's decision making when dealing with
612 MultiThreading at a cost of slightly increased overhead in some
613 places. If unsure say N here.
616 int "Maximum number of CPUs (2-4096)"
618 # These have to remain sorted largest to smallest
622 bool "Support for hot-pluggable CPUs"
623 select GENERIC_IRQ_MIGRATION
625 Say Y here to experiment with turning CPUs off and on. CPUs
626 can be controlled through /sys/devices/system/cpu.
628 # Common NUMA Features
630 bool "Numa Memory Allocation and Scheduler Support"
631 select ACPI_NUMA if ACPI
634 Enable NUMA (Non Uniform Memory Access) support.
636 The kernel will try to allocate memory used by a CPU on the
637 local memory of the CPU and add some more
638 NUMA awareness to the kernel.
641 int "Maximum NUMA Nodes (as a power of 2)"
644 depends on NEED_MULTIPLE_NODES
646 Specify the maximum number of NUMA Nodes available on the target
647 system. Increases memory reserved to accommodate various tables.
649 config USE_PERCPU_NUMA_NODE_ID
653 config HAVE_SETUP_PER_CPU_AREA
657 config NEED_PER_CPU_EMBED_FIRST_CHUNK
661 source kernel/Kconfig.preempt
662 source kernel/Kconfig.hz
664 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
667 config ARCH_HAS_HOLES_MEMORYMODEL
668 def_bool y if SPARSEMEM
670 config ARCH_SPARSEMEM_ENABLE
672 select SPARSEMEM_VMEMMAP_ENABLE
674 config ARCH_SPARSEMEM_DEFAULT
675 def_bool ARCH_SPARSEMEM_ENABLE
677 config ARCH_SELECT_MEMORY_MODEL
678 def_bool ARCH_SPARSEMEM_ENABLE
680 config HAVE_ARCH_PFN_VALID
681 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
683 config HW_PERF_EVENTS
687 config SYS_SUPPORTS_HUGETLBFS
690 config ARCH_WANT_HUGE_PMD_SHARE
691 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
693 config ARCH_HAS_CACHE_LINE_SIZE
699 bool "Enable seccomp to safely compute untrusted bytecode"
701 This kernel feature is useful for number crunching applications
702 that may need to compute untrusted bytecode during their
703 execution. By using pipes or other transports made available to
704 the process as file descriptors supporting the read/write
705 syscalls, it's possible to isolate those applications in
706 their own address space using seccomp. Once seccomp is
707 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
708 and the task is only allowed to execute a few safe syscalls
709 defined by each seccomp mode.
712 bool "Enable paravirtualization code"
714 This changes the kernel so it can modify itself when it is run
715 under a hypervisor, potentially improving performance significantly
716 over full virtualization.
718 config PARAVIRT_TIME_ACCOUNTING
719 bool "Paravirtual steal time accounting"
723 Select this option to enable fine granularity task steal time
724 accounting. Time spent executing other tasks in parallel with
725 the current vCPU is discounted from the vCPU power. To account for
726 that, there can be a small performance impact.
728 If in doubt, say N here.
731 depends on PM_SLEEP_SMP
733 bool "kexec system call"
735 kexec is a system call that implements the ability to shutdown your
736 current kernel, and to start another kernel. It is like a reboot
737 but it is independent of the system firmware. And like a reboot
738 you can start any kernel with it, not just Linux.
741 bool "Build kdump crash kernel"
743 Generate crash dump after being started by kexec. This should
744 be normally only set in special crash dump kernels which are
745 loaded in the main kernel with kexec-tools into a specially
746 reserved region and then later executed after a crash by
749 For more details see Documentation/kdump/kdump.txt
756 bool "Xen guest support on ARM64"
757 depends on ARM64 && OF
761 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
763 config FORCE_MAX_ZONEORDER
765 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
766 default "13" if (ARCH_THUNDER && ARM64_4K_PAGES)
767 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
770 The kernel memory allocator divides physically contiguous memory
771 blocks into "zones", where each zone is a power of two number of
772 pages. This option selects the largest power of two that the kernel
773 keeps in the memory allocator. If you need to allocate very large
774 blocks of physically contiguous memory, then you may need to
777 This config option is actually maximum order plus one. For example,
778 a value of 11 means that the largest free memory block is 2^10 pages.
780 We make sure that we can allocate upto a HugePage size for each configuration.
782 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
784 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
785 4M allocations matching the default size used by generic code.
787 menuconfig ARMV8_DEPRECATED
788 bool "Emulate deprecated/obsolete ARMv8 instructions"
791 Legacy software support may require certain instructions
792 that have been deprecated or obsoleted in the architecture.
794 Enable this config to enable selective emulation of these
802 bool "Emulate SWP/SWPB instructions"
804 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
805 they are always undefined. Say Y here to enable software
806 emulation of these instructions for userspace using LDXR/STXR.
808 In some older versions of glibc [<=2.8] SWP is used during futex
809 trylock() operations with the assumption that the code will not
810 be preempted. This invalid assumption may be more likely to fail
811 with SWP emulation enabled, leading to deadlock of the user
814 NOTE: when accessing uncached shared regions, LDXR/STXR rely
815 on an external transaction monitoring block called a global
816 monitor to maintain update atomicity. If your system does not
817 implement a global monitor, this option can cause programs that
818 perform SWP operations to uncached memory to deadlock.
822 config CP15_BARRIER_EMULATION
823 bool "Emulate CP15 Barrier instructions"
825 The CP15 barrier instructions - CP15ISB, CP15DSB, and
826 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
827 strongly recommended to use the ISB, DSB, and DMB
828 instructions instead.
830 Say Y here to enable software emulation of these
831 instructions for AArch32 userspace code. When this option is
832 enabled, CP15 barrier usage is traced which can help
833 identify software that needs updating.
837 config SETEND_EMULATION
838 bool "Emulate SETEND instruction"
840 The SETEND instruction alters the data-endianness of the
841 AArch32 EL0, and is deprecated in ARMv8.
843 Say Y here to enable software emulation of the instruction
844 for AArch32 userspace code.
846 Note: All the cpus on the system must have mixed endian support at EL0
847 for this feature to be enabled. If a new CPU - which doesn't support mixed
848 endian - is hotplugged in after this feature has been enabled, there could
849 be unexpected results in the applications.
854 config ARM64_SW_TTBR0_PAN
855 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
857 Enabling this option prevents the kernel from accessing
858 user-space memory directly by pointing TTBR0_EL1 to a reserved
859 zeroed area and reserved ASID. The user access routines
860 restore the valid TTBR0_EL1 temporarily.
862 menu "ARMv8.1 architectural features"
864 config ARM64_HW_AFDBM
865 bool "Support for hardware updates of the Access and Dirty page flags"
868 The ARMv8.1 architecture extensions introduce support for
869 hardware updates of the access and dirty information in page
870 table entries. When enabled in TCR_EL1 (HA and HD bits) on
871 capable processors, accesses to pages with PTE_AF cleared will
872 set this bit instead of raising an access flag fault.
873 Similarly, writes to read-only pages with the DBM bit set will
874 clear the read-only bit (AP[2]) instead of raising a
877 Kernels built with this configuration option enabled continue
878 to work on pre-ARMv8.1 hardware and the performance impact is
879 minimal. If unsure, say Y.
882 bool "Enable support for Privileged Access Never (PAN)"
885 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
886 prevents the kernel or hypervisor from accessing user-space (EL0)
889 Choosing this option will cause any unprotected (not using
890 copy_to_user et al) memory access to fail with a permission fault.
892 The feature is detected at runtime, and will remain as a 'nop'
893 instruction if the cpu does not implement the feature.
895 config ARM64_LSE_ATOMICS
896 bool "Atomic instructions"
898 As part of the Large System Extensions, ARMv8.1 introduces new
899 atomic instructions that are designed specifically to scale in
902 Say Y here to make use of these instructions for the in-kernel
903 atomic routines. This incurs a small overhead on CPUs that do
904 not support these instructions and requires the kernel to be
905 built with binutils >= 2.25.
908 bool "Enable support for Virtualization Host Extensions (VHE)"
911 Virtualization Host Extensions (VHE) allow the kernel to run
912 directly at EL2 (instead of EL1) on processors that support
913 it. This leads to better performance for KVM, as they reduce
914 the cost of the world switch.
916 Selecting this option allows the VHE feature to be detected
917 at runtime, and does not affect processors that do not
918 implement this feature.
922 menu "ARMv8.2 architectural features"
925 bool "Enable support for User Access Override (UAO)"
928 User Access Override (UAO; part of the ARMv8.2 Extensions)
929 causes the 'unprivileged' variant of the load/store instructions to
930 be overriden to be privileged.
932 This option changes get_user() and friends to use the 'unprivileged'
933 variant of the load/store instructions. This ensures that user-space
934 really did have access to the supplied memory. When addr_limit is
935 set to kernel memory the UAO bit will be set, allowing privileged
936 access to kernel memory.
938 Choosing this option will cause copy_to_user() et al to use user-space
941 The feature is detected at runtime, the kernel will use the
942 regular load/store instructions if the cpu does not implement the
947 config ARM64_MODULE_CMODEL_LARGE
950 config ARM64_MODULE_PLTS
952 select ARM64_MODULE_CMODEL_LARGE
953 select HAVE_MOD_ARCH_SPECIFIC
958 This builds the kernel as a Position Independent Executable (PIE),
959 which retains all relocation metadata required to relocate the
960 kernel binary at runtime to a different virtual address than the
961 address it was linked at.
962 Since AArch64 uses the RELA relocation format, this requires a
963 relocation pass at runtime even if the kernel is loaded at the
964 same address it was linked at.
966 config RANDOMIZE_BASE
967 bool "Randomize the address of the kernel image"
968 select ARM64_MODULE_PLTS if MODULES
971 Randomizes the virtual address at which the kernel image is
972 loaded, as a security feature that deters exploit attempts
973 relying on knowledge of the location of kernel internals.
975 It is the bootloader's job to provide entropy, by passing a
976 random u64 value in /chosen/kaslr-seed at kernel entry.
978 When booting via the UEFI stub, it will invoke the firmware's
979 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
980 to the kernel proper. In addition, it will randomise the physical
981 location of the kernel Image as well.
985 config RANDOMIZE_MODULE_REGION_FULL
986 bool "Randomize the module region independently from the core kernel"
987 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
990 Randomizes the location of the module region without considering the
991 location of the core kernel. This way, it is impossible for modules
992 to leak information about the location of core kernel data structures
993 but it does imply that function calls between modules and the core
994 kernel will need to be resolved via veneers in the module PLT.
996 When this option is not set, the module region will be randomized over
997 a limited range that contains the [_stext, _etext] interval of the
998 core kernel, so branch relocations are always in range.
1004 config ARM64_ACPI_PARKING_PROTOCOL
1005 bool "Enable support for the ARM64 ACPI parking protocol"
1008 Enable support for the ARM64 ACPI parking protocol. If disabled
1009 the kernel will not allow booting through the ARM64 ACPI parking
1010 protocol even if the corresponding data is present in the ACPI
1014 string "Default kernel command string"
1017 Provide a set of default command-line options at build time by
1018 entering them here. As a minimum, you should specify the the
1019 root device (e.g. root=/dev/nfs).
1021 config CMDLINE_FORCE
1022 bool "Always use the default kernel command string"
1024 Always use the default kernel command string, even if the boot
1025 loader passes other arguments to the kernel.
1026 This is useful if you cannot or don't want to change the
1027 command-line options your boot loader passes to the kernel.
1033 bool "UEFI runtime support"
1034 depends on OF && !CPU_BIG_ENDIAN
1037 select EFI_PARAMS_FROM_FDT
1038 select EFI_RUNTIME_WRAPPERS
1043 This option provides support for runtime services provided
1044 by UEFI firmware (such as non-volatile variables, realtime
1045 clock, and platform reset). A UEFI stub is also provided to
1046 allow the kernel to be booted as an EFI application. This
1047 is only useful on systems that have UEFI firmware.
1050 bool "Enable support for SMBIOS (DMI) tables"
1054 This enables SMBIOS/DMI feature for systems.
1056 This option is only useful on systems that have UEFI firmware.
1057 However, even with this option, the resultant kernel should
1058 continue to boot on existing non-UEFI platforms.
1062 menu "Userspace binary formats"
1064 source "fs/Kconfig.binfmt"
1067 bool "Kernel support for 32-bit EL0"
1068 depends on ARM64_4K_PAGES || EXPERT
1069 select COMPAT_BINFMT_ELF
1071 select OLD_SIGSUSPEND3
1072 select COMPAT_OLD_SIGACTION
1074 This option enables support for a 32-bit EL0 running under a 64-bit
1075 kernel at EL1. AArch32-specific components such as system calls,
1076 the user helper functions, VFP support and the ptrace interface are
1077 handled appropriately by the kernel.
1079 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1080 that you will only be able to execute AArch32 binaries that were compiled
1081 with page size aligned segments.
1083 If you want to execute 32-bit userspace applications, say Y.
1085 config SYSVIPC_COMPAT
1087 depends on COMPAT && SYSVIPC
1091 menu "Power management options"
1093 source "kernel/power/Kconfig"
1095 config ARCH_HIBERNATION_POSSIBLE
1099 config ARCH_HIBERNATION_HEADER
1101 depends on HIBERNATION
1103 config ARCH_SUSPEND_POSSIBLE
1108 menu "CPU Power Management"
1110 source "drivers/cpuidle/Kconfig"
1112 source "drivers/cpufreq/Kconfig"
1116 source "net/Kconfig"
1118 source "drivers/Kconfig"
1120 source "ubuntu/Kconfig"
1122 source "drivers/firmware/Kconfig"
1124 source "drivers/acpi/Kconfig"
1128 source "arch/arm64/kvm/Kconfig"
1130 source "arch/arm64/Kconfig.debug"
1132 source "security/Kconfig"
1134 source "crypto/Kconfig"
1136 source "arch/arm64/crypto/Kconfig"
1139 source "lib/Kconfig"