arch/arm64/Kconfig

   1 config ARM64
   2         def_bool y
   3         select ACPI_CCA_REQUIRED if ACPI
   4         select ACPI_GENERIC_GSI if ACPI
   5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   6         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   7         select ARCH_HAS_ELF_RANDOMIZE
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_HAS_SG_CHAIN
  10         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  11         select ARCH_USE_CMPXCHG_LOCKREF
  12         select ARCH_SUPPORTS_ATOMIC_RMW
  13         select ARCH_WANT_OPTIONAL_GPIOLIB
  14         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
  15         select ARCH_WANT_FRAME_POINTERS
  16         select ARM_AMBA
  17         select ARM_ARCH_TIMER
  18         select ARM_GIC
  19         select AUDIT_ARCH_COMPAT_GENERIC
  20         select ARM_GIC_V2M if PCI_MSI
  21         select ARM_GIC_V3
  22         select ARM_GIC_V3_ITS if PCI_MSI
  23         select BUILDTIME_EXTABLE_SORT
  24         select CLONE_BACKWARDS
  25         select COMMON_CLK
  26         select CPU_PM if (SUSPEND || CPU_IDLE)
  27         select DCACHE_WORD_ACCESS
  28         select EDAC_SUPPORT
  29         select GENERIC_ALLOCATOR
  30         select GENERIC_CLOCKEVENTS
  31         select GENERIC_CLOCKEVENTS_BROADCAST
  32         select GENERIC_CPU_AUTOPROBE
  33         select GENERIC_EARLY_IOREMAP
  34         select GENERIC_IRQ_PROBE
  35         select GENERIC_IRQ_SHOW
  36         select GENERIC_IRQ_SHOW_LEVEL
  37         select GENERIC_PCI_IOMAP
  38         select GENERIC_SCHED_CLOCK
  39         select GENERIC_SMP_IDLE_THREAD
  40         select GENERIC_STRNCPY_FROM_USER
  41         select GENERIC_STRNLEN_USER
  42         select GENERIC_TIME_VSYSCALL
  43         select HANDLE_DOMAIN_IRQ
  44         select HARDIRQS_SW_RESEND
  45         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
  46         select HAVE_ARCH_AUDITSYSCALL
  47         select HAVE_ARCH_BITREVERSE
  48         select HAVE_ARCH_JUMP_LABEL
  49         select HAVE_ARCH_KGDB
  50         select HAVE_ARCH_SECCOMP_FILTER
  51         select HAVE_ARCH_TRACEHOOK
  52         select HAVE_BPF_JIT
  53         select HAVE_C_RECORDMCOUNT
  54         select HAVE_CC_STACKPROTECTOR
  55         select HAVE_CMPXCHG_DOUBLE
  56         select HAVE_DEBUG_BUGVERBOSE
  57         select HAVE_DEBUG_KMEMLEAK
  58         select HAVE_DMA_API_DEBUG
  59         select HAVE_DMA_ATTRS
  60         select HAVE_DMA_CONTIGUOUS
  61         select HAVE_DYNAMIC_FTRACE
  62         select HAVE_EFFICIENT_UNALIGNED_ACCESS
  63         select HAVE_FTRACE_MCOUNT_RECORD
  64         select HAVE_FUNCTION_TRACER
  65         select HAVE_FUNCTION_GRAPH_TRACER
  66         select HAVE_GENERIC_DMA_COHERENT
  67         select HAVE_HW_BREAKPOINT if PERF_EVENTS
  68         select HAVE_MEMBLOCK
  69         select HAVE_PATA_PLATFORM
  70         select HAVE_PERF_EVENTS
  71         select HAVE_PERF_REGS
  72         select HAVE_PERF_USER_STACK_DUMP
  73         select HAVE_RCU_TABLE_FREE
  74         select HAVE_SYSCALL_TRACEPOINTS
  75         select IRQ_DOMAIN
  76         select IRQ_FORCED_THREADING
  77         select MODULES_USE_ELF_RELA
  78         select NO_BOOTMEM
  79         select OF
  80         select OF_EARLY_FLATTREE
  81         select OF_RESERVED_MEM
  82         select PERF_USE_VMALLOC
  83         select POWER_RESET
  84         select POWER_SUPPLY
  85         select RTC_LIB
  86         select SPARSE_IRQ
  87         select SYSCTL_EXCEPTION_TRACE
  88         select HAVE_CONTEXT_TRACKING
  89         help
  90           ARM 64-bit (AArch64) Linux support.
  91
  92 config 64BIT
  93         def_bool y
  94
  95 config ARCH_PHYS_ADDR_T_64BIT
  96         def_bool y
  97
  98 config MMU
  99         def_bool y
 100
 101 config NO_IOPORT_MAP
 102         def_bool y if !PCI
 103
 104 config STACKTRACE_SUPPORT
 105         def_bool y
 106
 107 config LOCKDEP_SUPPORT
 108         def_bool y
 109
 110 config TRACE_IRQFLAGS_SUPPORT
 111         def_bool y
 112
 113 config RWSEM_XCHGADD_ALGORITHM
 114         def_bool y
 115
 116 config GENERIC_HWEIGHT
 117         def_bool y
 118
 119 config GENERIC_CSUM
 120         def_bool y
 121
 122 config GENERIC_CALIBRATE_DELAY
 123         def_bool y
 124
 125 config ZONE_DMA
 126         def_bool y
 127
 128 config HAVE_GENERIC_RCU_GUP
 129         def_bool y
 130
 131 config ARCH_DMA_ADDR_T_64BIT
 132         def_bool y
 133
 134 config NEED_DMA_MAP_STATE
 135         def_bool y
 136
 137 config NEED_SG_DMA_LENGTH
 138         def_bool y
 139
 140 config SMP
 141         def_bool y
 142
 143 config SWIOTLB
 144         def_bool y
 145
 146 config IOMMU_HELPER
 147         def_bool SWIOTLB
 148
 149 config KERNEL_MODE_NEON
 150         def_bool y
 151
 152 config FIX_EARLYCON_MEM
 153         def_bool y
 154
 155 config PGTABLE_LEVELS
 156         int
 157         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 158         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 159         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 160         default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
 161
 162 source "init/Kconfig"
 163
 164 source "kernel/Kconfig.freezer"
 165
 166 menu "Platform selection"
 167
 168 config ARCH_EXYNOS
 169         bool
 170         help
 171           This enables support for Samsung Exynos SoC family
 172
 173 config ARCH_EXYNOS7
 174         bool "ARMv8 based Samsung Exynos7"
 175         select ARCH_EXYNOS
 176         select COMMON_CLK_SAMSUNG
 177         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 178         select HAVE_S3C_RTC if RTC_CLASS
 179         select PINCTRL
 180         select PINCTRL_EXYNOS
 181
 182         help
 183           This enables support for Samsung Exynos7 SoC family
 184
 185 config ARCH_FSL_LS2085A
 186         bool "Freescale LS2085A SOC"
 187         help
 188           This enables support for Freescale LS2085A SOC.
 189
 190 config ARCH_HISI
 191         bool "Hisilicon SoC Family"
 192         help
 193           This enables support for Hisilicon ARMv8 SoC family
 194
 195 config ARCH_MEDIATEK
 196         bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
 197         select ARM_GIC
 198         select PINCTRL
 199         help
 200           Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
 201
 202 config ARCH_QCOM
 203         bool "Qualcomm Platforms"
 204         select PINCTRL
 205         help
 206           This enables support for the ARMv8 based Qualcomm chipsets.
 207
 208 config ARCH_SEATTLE
 209         bool "AMD Seattle SoC Family"
 210         help
 211           This enables support for AMD Seattle SOC Family
 212
 213 config ARCH_TEGRA
 214         bool "NVIDIA Tegra SoC Family"
 215         select ARCH_HAS_RESET_CONTROLLER
 216         select ARCH_REQUIRE_GPIOLIB
 217         select CLKDEV_LOOKUP
 218         select CLKSRC_MMIO
 219         select CLKSRC_OF
 220         select GENERIC_CLOCKEVENTS
 221         select HAVE_CLK
 222         select PINCTRL
 223         select RESET_CONTROLLER
 224         help
 225           This enables support for the NVIDIA Tegra SoC family.
 226
 227 config ARCH_TEGRA_132_SOC
 228         bool "NVIDIA Tegra132 SoC"
 229         depends on ARCH_TEGRA
 230         select PINCTRL_TEGRA124
 231         select USB_ULPI if USB_PHY
 232         select USB_ULPI_VIEWPORT if USB_PHY
 233         help
 234           Enable support for NVIDIA Tegra132 SoC, based on the Denver
 235           ARMv8 CPU.  The Tegra132 SoC is similar to the Tegra124 SoC,
 236           but contains an NVIDIA Denver CPU complex in place of
 237           Tegra124's "4+1" Cortex-A15 CPU complex.
 238
 239 config ARCH_SPRD
 240         bool "Spreadtrum SoC platform"
 241         help
 242           Support for Spreadtrum ARM based SoCs
 243
 244 config ARCH_THUNDER
 245         bool "Cavium Inc. Thunder SoC Family"
 246         help
 247           This enables support for Cavium's Thunder Family of SoCs.
 248
 249 config ARCH_VEXPRESS
 250         bool "ARMv8 software model (Versatile Express)"
 251         select ARCH_REQUIRE_GPIOLIB
 252         select COMMON_CLK_VERSATILE
 253         select POWER_RESET_VEXPRESS
 254         select VEXPRESS_CONFIG
 255         help
 256           This enables support for the ARMv8 software model (Versatile
 257           Express).
 258
 259 config ARCH_XGENE
 260         bool "AppliedMicro X-Gene SOC Family"
 261         help
 262           This enables support for AppliedMicro X-Gene SOC Family
 263
 264 config ARCH_ZYNQMP
 265         bool "Xilinx ZynqMP Family"
 266         help
 267           This enables support for Xilinx ZynqMP Family
 268
 269 endmenu
 270
 271 menu "Bus support"
 272
 273 config PCI
 274         bool "PCI support"
 275         help
 276           This feature enables support for PCI bus system. If you say Y
 277           here, the kernel will include drivers and infrastructure code
 278           to support PCI bus devices.
 279
 280 config PCI_DOMAINS
 281         def_bool PCI
 282
 283 config PCI_DOMAINS_GENERIC
 284         def_bool PCI
 285
 286 config PCI_SYSCALL
 287         def_bool PCI
 288
 289 source "drivers/pci/Kconfig"
 290 source "drivers/pci/pcie/Kconfig"
 291 source "drivers/pci/hotplug/Kconfig"
 292
 293 endmenu
 294
 295 menu "Kernel Features"
 296
 297 menu "ARM errata workarounds via the alternatives framework"
 298
 299 config ARM64_ERRATUM_826319
 300         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 301         default y
 302         help
 303           This option adds an alternative code sequence to work around ARM
 304           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 305           AXI master interface and an L2 cache.
 306
 307           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 308           and is unable to accept a certain write via this interface, it will
 309           not progress on read data presented on the read data channel and the
 310           system can deadlock.
 311
 312           The workaround promotes data cache clean instructions to
 313           data cache clean-and-invalidate.
 314           Please note that this does not necessarily enable the workaround,
 315           as it depends on the alternative framework, which will only patch
 316           the kernel if an affected CPU is detected.
 317
 318           If unsure, say Y.
 319
 320 config ARM64_ERRATUM_827319
 321         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 322         default y
 323         help
 324           This option adds an alternative code sequence to work around ARM
 325           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 326           master interface and an L2 cache.
 327
 328           Under certain conditions this erratum can cause a clean line eviction
 329           to occur at the same time as another transaction to the same address
 330           on the AMBA 5 CHI interface, which can cause data corruption if the
 331           interconnect reorders the two transactions.
 332
 333           The workaround promotes data cache clean instructions to
 334           data cache clean-and-invalidate.
 335           Please note that this does not necessarily enable the workaround,
 336           as it depends on the alternative framework, which will only patch
 337           the kernel if an affected CPU is detected.
 338
 339           If unsure, say Y.
 340
 341 config ARM64_ERRATUM_824069
 342         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 343         default y
 344         help
 345           This option adds an alternative code sequence to work around ARM
 346           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 347           to a coherent interconnect.
 348
 349           If a Cortex-A53 processor is executing a store or prefetch for
 350           write instruction at the same time as a processor in another
 351           cluster is executing a cache maintenance operation to the same
 352           address, then this erratum might cause a clean cache line to be
 353           incorrectly marked as dirty.
 354
 355           The workaround promotes data cache clean instructions to
 356           data cache clean-and-invalidate.
 357           Please note that this option does not necessarily enable the
 358           workaround, as it depends on the alternative framework, which will
 359           only patch the kernel if an affected CPU is detected.
 360
 361           If unsure, say Y.
 362
 363 config ARM64_ERRATUM_819472
 364         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 365         default y
 366         help
 367           This option adds an alternative code sequence to work around ARM
 368           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 369           present when it is connected to a coherent interconnect.
 370
 371           If the processor is executing a load and store exclusive sequence at
 372           the same time as a processor in another cluster is executing a cache
 373           maintenance operation to the same address, then this erratum might
 374           cause data corruption.
 375
 376           The workaround promotes data cache clean instructions to
 377           data cache clean-and-invalidate.
 378           Please note that this does not necessarily enable the workaround,
 379           as it depends on the alternative framework, which will only patch
 380           the kernel if an affected CPU is detected.
 381
 382           If unsure, say Y.
 383
 384 config ARM64_ERRATUM_832075
 385         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 386         default y
 387         help
 388           This option adds an alternative code sequence to work around ARM
 389           erratum 832075 on Cortex-A57 parts up to r1p2.
 390
 391           Affected Cortex-A57 parts might deadlock when exclusive load/store
 392           instructions to Write-Back memory are mixed with Device loads.
 393
 394           The workaround is to promote device loads to use Load-Acquire
 395           semantics.
 396           Please note that this does not necessarily enable the workaround,
 397           as it depends on the alternative framework, which will only patch
 398           the kernel if an affected CPU is detected.
 399
 400           If unsure, say Y.
 401
 402 config ARM64_ERRATUM_845719
 403         bool "Cortex-A53: 845719: a load might read incorrect data"
 404         depends on COMPAT
 405         default y
 406         help
 407           This option adds an alternative code sequence to work around ARM
 408           erratum 845719 on Cortex-A53 parts up to r0p4.
 409
 410           When running a compat (AArch32) userspace on an affected Cortex-A53
 411           part, a load at EL0 from a virtual address that matches the bottom 32
 412           bits of the virtual address used by a recent load at (AArch64) EL1
 413           might return incorrect data.
 414
 415           The workaround is to write the contextidr_el1 register on exception
 416           return to a 32-bit task.
 417           Please note that this does not necessarily enable the workaround,
 418           as it depends on the alternative framework, which will only patch
 419           the kernel if an affected CPU is detected.
 420
 421           If unsure, say Y.
 422
 423 endmenu
 424
 425
 426 choice
 427         prompt "Page size"
 428         default ARM64_4K_PAGES
 429         help
 430           Page size (translation granule) configuration.
 431
 432 config ARM64_4K_PAGES
 433         bool "4KB"
 434         help
 435           This feature enables 4KB pages support.
 436
 437 config ARM64_64K_PAGES
 438         bool "64KB"
 439         help
 440           This feature enables 64KB pages support (4KB by default)
 441           allowing only two levels of page tables and faster TLB
 442           look-up. AArch32 emulation is not available when this feature
 443           is enabled.
 444
 445 endchoice
 446
 447 choice
 448         prompt "Virtual address space size"
 449         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 450         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 451         help
 452           Allows choosing one of multiple possible virtual address
 453           space sizes. The level of translation table is determined by
 454           a combination of page size and virtual address space size.
 455
 456 config ARM64_VA_BITS_39
 457         bool "39-bit"
 458         depends on ARM64_4K_PAGES
 459
 460 config ARM64_VA_BITS_42
 461         bool "42-bit"
 462         depends on ARM64_64K_PAGES
 463
 464 config ARM64_VA_BITS_48
 465         bool "48-bit"
 466
 467 endchoice
 468
 469 config ARM64_VA_BITS
 470         int
 471         default 39 if ARM64_VA_BITS_39
 472         default 42 if ARM64_VA_BITS_42
 473         default 48 if ARM64_VA_BITS_48
 474
 475 config ARM64_HW_AFDBM
 476         bool "Support for hardware updates of the Access and Dirty page flags"
 477         default y
 478         help
 479           The ARMv8.1 architecture extensions introduce support for
 480           hardware updates of the access and dirty information in page
 481           table entries. When enabled in TCR_EL1 (HA and HD bits) on
 482           capable processors, accesses to pages with PTE_AF cleared will
 483           set this bit instead of raising an access flag fault.
 484           Similarly, writes to read-only pages with the DBM bit set will
 485           clear the read-only bit (AP[2]) instead of raising a
 486           permission fault.
 487
 488           Kernels built with this configuration option enabled continue
 489           to work on pre-ARMv8.1 hardware and the performance impact is
 490           minimal. If unsure, say Y.
 491
 492 config CPU_BIG_ENDIAN
 493        bool "Build big-endian kernel"
 494        help
 495          Say Y if you plan on running a kernel in big-endian mode.
 496
 497 config SCHED_MC
 498         bool "Multi-core scheduler support"
 499         help
 500           Multi-core scheduler support improves the CPU scheduler's decision
 501           making when dealing with multi-core CPU chips at a cost of slightly
 502           increased overhead in some places. If unsure say N here.
 503
 504 config SCHED_SMT
 505         bool "SMT scheduler support"
 506         help
 507           Improves the CPU scheduler's decision making when dealing with
 508           MultiThreading at a cost of slightly increased overhead in some
 509           places. If unsure say N here.
 510
 511 config NR_CPUS
 512         int "Maximum number of CPUs (2-4096)"
 513         range 2 4096
 514         # These have to remain sorted largest to smallest
 515         default "64"
 516
 517 config HOTPLUG_CPU
 518         bool "Support for hot-pluggable CPUs"
 519         help
 520           Say Y here to experiment with turning CPUs off and on.  CPUs
 521           can be controlled through /sys/devices/system/cpu.
 522
 523 source kernel/Kconfig.preempt
 524
 525 config HZ
 526         int
 527         default 100
 528
 529 config ARCH_HAS_HOLES_MEMORYMODEL
 530         def_bool y if SPARSEMEM
 531
 532 config ARCH_SPARSEMEM_ENABLE
 533         def_bool y
 534         select SPARSEMEM_VMEMMAP_ENABLE
 535
 536 config ARCH_SPARSEMEM_DEFAULT
 537         def_bool ARCH_SPARSEMEM_ENABLE
 538
 539 config ARCH_SELECT_MEMORY_MODEL
 540         def_bool ARCH_SPARSEMEM_ENABLE
 541
 542 config HAVE_ARCH_PFN_VALID
 543         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 544
 545 config HW_PERF_EVENTS
 546         bool "Enable hardware performance counter support for perf events"
 547         depends on PERF_EVENTS
 548         default y
 549         help
 550           Enable hardware performance counter support for perf events. If
 551           disabled, perf events will use software events only.
 552
 553 config SYS_SUPPORTS_HUGETLBFS
 554         def_bool y
 555
 556 config ARCH_WANT_GENERAL_HUGETLB
 557         def_bool y
 558
 559 config ARCH_WANT_HUGE_PMD_SHARE
 560         def_bool y if !ARM64_64K_PAGES
 561
 562 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 563         def_bool y
 564
 565 config ARCH_HAS_CACHE_LINE_SIZE
 566         def_bool y
 567
 568 source "mm/Kconfig"
 569
 570 config SECCOMP
 571         bool "Enable seccomp to safely compute untrusted bytecode"
 572         ---help---
 573           This kernel feature is useful for number crunching applications
 574           that may need to compute untrusted bytecode during their
 575           execution. By using pipes or other transports made available to
 576           the process as file descriptors supporting the read/write
 577           syscalls, it's possible to isolate those applications in
 578           their own address space using seccomp. Once seccomp is
 579           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 580           and the task is only allowed to execute a few safe syscalls
 581           defined by each seccomp mode.
 582
 583 config XEN_DOM0
 584         def_bool y
 585         depends on XEN
 586
 587 config XEN
 588         bool "Xen guest support on ARM64"
 589         depends on ARM64 && OF
 590         select SWIOTLB_XEN
 591         help
 592           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
 593
 594 config FORCE_MAX_ZONEORDER
 595         int
 596         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
 597         default "11"
 598
 599 config ARM64_PAN
 600         bool "Enable support for Privileged Access Never (PAN)"
 601         default y
 602         help
 603          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
 604          prevents the kernel or hypervisor from accessing user-space (EL0)
 605          memory directly.
 606
 607          Choosing this option will cause any unprotected (not using
 608          copy_to_user et al) memory access to fail with a permission fault.
 609
 610          The feature is detected at runtime, and will remain as a 'nop'
 611          instruction if the cpu does not implement the feature.
 612
 613 menuconfig ARMV8_DEPRECATED
 614         bool "Emulate deprecated/obsolete ARMv8 instructions"
 615         depends on COMPAT
 616         help
 617           Legacy software support may require certain instructions
 618           that have been deprecated or obsoleted in the architecture.
 619
 620           Enable this config to enable selective emulation of these
 621           features.
 622
 623           If unsure, say Y
 624
 625 if ARMV8_DEPRECATED
 626
 627 config SWP_EMULATION
 628         bool "Emulate SWP/SWPB instructions"
 629         help
 630           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
 631           they are always undefined. Say Y here to enable software
 632           emulation of these instructions for userspace using LDXR/STXR.
 633
 634           In some older versions of glibc [<=2.8] SWP is used during futex
 635           trylock() operations with the assumption that the code will not
 636           be preempted. This invalid assumption may be more likely to fail
 637           with SWP emulation enabled, leading to deadlock of the user
 638           application.
 639
 640           NOTE: when accessing uncached shared regions, LDXR/STXR rely
 641           on an external transaction monitoring block called a global
 642           monitor to maintain update atomicity. If your system does not
 643           implement a global monitor, this option can cause programs that
 644           perform SWP operations to uncached memory to deadlock.
 645
 646           If unsure, say Y
 647
 648 config CP15_BARRIER_EMULATION
 649         bool "Emulate CP15 Barrier instructions"
 650         help
 651           The CP15 barrier instructions - CP15ISB, CP15DSB, and
 652           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
 653           strongly recommended to use the ISB, DSB, and DMB
 654           instructions instead.
 655
 656           Say Y here to enable software emulation of these
 657           instructions for AArch32 userspace code. When this option is
 658           enabled, CP15 barrier usage is traced which can help
 659           identify software that needs updating.
 660
 661           If unsure, say Y
 662
 663 config SETEND_EMULATION
 664         bool "Emulate SETEND instruction"
 665         help
 666           The SETEND instruction alters the data-endianness of the
 667           AArch32 EL0, and is deprecated in ARMv8.
 668
 669           Say Y here to enable software emulation of the instruction
 670           for AArch32 userspace code.
 671
 672           Note: All the cpus on the system must have mixed endian support at EL0
 673           for this feature to be enabled. If a new CPU - which doesn't support mixed
 674           endian - is hotplugged in after this feature has been enabled, there could
 675           be unexpected results in the applications.
 676
 677           If unsure, say Y
 678 endif
 679
 680 endmenu
 681
 682 menu "Boot options"
 683
 684 config CMDLINE
 685         string "Default kernel command string"
 686         default ""
 687         help
 688           Provide a set of default command-line options at build time by
 689           entering them here. As a minimum, you should specify the the
 690           root device (e.g. root=/dev/nfs).
 691
 692 config CMDLINE_FORCE
 693         bool "Always use the default kernel command string"
 694         help
 695           Always use the default kernel command string, even if the boot
 696           loader passes other arguments to the kernel.
 697           This is useful if you cannot or don't want to change the
 698           command-line options your boot loader passes to the kernel.
 699
 700 config EFI_STUB
 701         bool
 702
 703 config EFI
 704         bool "UEFI runtime support"
 705         depends on OF && !CPU_BIG_ENDIAN
 706         select LIBFDT
 707         select UCS2_STRING
 708         select EFI_PARAMS_FROM_FDT
 709         select EFI_RUNTIME_WRAPPERS
 710         select EFI_STUB
 711         select EFI_ARMSTUB
 712         default y
 713         help
 714           This option provides support for runtime services provided
 715           by UEFI firmware (such as non-volatile variables, realtime
 716           clock, and platform reset). A UEFI stub is also provided to
 717           allow the kernel to be booted as an EFI application. This
 718           is only useful on systems that have UEFI firmware.
 719
 720 config DMI
 721         bool "Enable support for SMBIOS (DMI) tables"
 722         depends on EFI
 723         default y
 724         help
 725           This enables SMBIOS/DMI feature for systems.
 726
 727           This option is only useful on systems that have UEFI firmware.
 728           However, even with this option, the resultant kernel should
 729           continue to boot on existing non-UEFI platforms.
 730
 731 endmenu
 732
 733 menu "Userspace binary formats"
 734
 735 source "fs/Kconfig.binfmt"
 736
 737 config COMPAT
 738         bool "Kernel support for 32-bit EL0"
 739         depends on !ARM64_64K_PAGES || EXPERT
 740         select COMPAT_BINFMT_ELF
 741         select HAVE_UID16
 742         select OLD_SIGSUSPEND3
 743         select COMPAT_OLD_SIGACTION
 744         help
 745           This option enables support for a 32-bit EL0 running under a 64-bit
 746           kernel at EL1. AArch32-specific components such as system calls,
 747           the user helper functions, VFP support and the ptrace interface are
 748           handled appropriately by the kernel.
 749
 750           If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
 751           will only be able to execute AArch32 binaries that were compiled with
 752           64k aligned segments.
 753
 754           If you want to execute 32-bit userspace applications, say Y.
 755
 756 config SYSVIPC_COMPAT
 757         def_bool y
 758         depends on COMPAT && SYSVIPC
 759
 760 endmenu
 761
 762 menu "Power management options"
 763
 764 source "kernel/power/Kconfig"
 765
 766 config ARCH_SUSPEND_POSSIBLE
 767         def_bool y
 768
 769 endmenu
 770
 771 menu "CPU Power Management"
 772
 773 source "drivers/cpuidle/Kconfig"
 774
 775 source "drivers/cpufreq/Kconfig"
 776
 777 endmenu
 778
 779 source "net/Kconfig"
 780
 781 source "drivers/Kconfig"
 782
 783 source "drivers/firmware/Kconfig"
 784
 785 source "drivers/acpi/Kconfig"
 786
 787 source "fs/Kconfig"
 788
 789 source "arch/arm64/kvm/Kconfig"
 790
 791 source "arch/arm64/Kconfig.debug"
 792
 793 source "security/Kconfig"
 794
 795 source "crypto/Kconfig"
 796 if CRYPTO
 797 source "arch/arm64/crypto/Kconfig"
 798 endif
 799
 800 source "lib/Kconfig"