arch/arm64/Kconfig

   1 config ARM64
   2         def_bool y
   3         select ACPI_CCA_REQUIRED if ACPI
   4         select ACPI_GENERIC_GSI if ACPI
   5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   6         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   7         select ARCH_HAS_ELF_RANDOMIZE
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_HAS_SG_CHAIN
  10         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  11         select ARCH_USE_CMPXCHG_LOCKREF
  12         select ARCH_SUPPORTS_ATOMIC_RMW
  13         select ARCH_WANT_OPTIONAL_GPIOLIB
  14         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
  15         select ARCH_WANT_FRAME_POINTERS
  16         select ARM_AMBA
  17         select ARM_ARCH_TIMER
  18         select ARM_GIC
  19         select AUDIT_ARCH_COMPAT_GENERIC
  20         select ARM_GIC_V2M if PCI_MSI
  21         select ARM_GIC_V3
  22         select ARM_GIC_V3_ITS if PCI_MSI
  23         select ARM_PSCI_FW
  24         select BUILDTIME_EXTABLE_SORT
  25         select CLONE_BACKWARDS
  26         select COMMON_CLK
  27         select CPU_PM if (SUSPEND || CPU_IDLE)
  28         select DCACHE_WORD_ACCESS
  29         select EDAC_SUPPORT
  30         select FRAME_POINTER
  31         select GENERIC_ALLOCATOR
  32         select GENERIC_CLOCKEVENTS
  33         select GENERIC_CLOCKEVENTS_BROADCAST
  34         select GENERIC_CPU_AUTOPROBE
  35         select GENERIC_EARLY_IOREMAP
  36         select GENERIC_IDLE_POLL_SETUP
  37         select GENERIC_IRQ_PROBE
  38         select GENERIC_IRQ_SHOW
  39         select GENERIC_IRQ_SHOW_LEVEL
  40         select GENERIC_PCI_IOMAP
  41         select GENERIC_SCHED_CLOCK
  42         select GENERIC_SMP_IDLE_THREAD
  43         select GENERIC_STRNCPY_FROM_USER
  44         select GENERIC_STRNLEN_USER
  45         select GENERIC_TIME_VSYSCALL
  46         select HANDLE_DOMAIN_IRQ
  47         select HARDIRQS_SW_RESEND
  48         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
  49         select HAVE_ARCH_AUDITSYSCALL
  50         select HAVE_ARCH_BITREVERSE
  51         select HAVE_ARCH_JUMP_LABEL
  52         select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
  53         select HAVE_ARCH_KGDB
  54         select HAVE_ARCH_SECCOMP_FILTER
  55         select HAVE_ARCH_TRACEHOOK
  56         select HAVE_BPF_JIT
  57         select HAVE_C_RECORDMCOUNT
  58         select HAVE_CC_STACKPROTECTOR
  59         select HAVE_CMPXCHG_DOUBLE
  60         select HAVE_CMPXCHG_LOCAL
  61         select HAVE_DEBUG_BUGVERBOSE
  62         select HAVE_DEBUG_KMEMLEAK
  63         select HAVE_DMA_API_DEBUG
  64         select HAVE_DMA_ATTRS
  65         select HAVE_DMA_CONTIGUOUS
  66         select HAVE_DYNAMIC_FTRACE
  67         select HAVE_EFFICIENT_UNALIGNED_ACCESS
  68         select HAVE_FTRACE_MCOUNT_RECORD
  69         select HAVE_FUNCTION_TRACER
  70         select HAVE_FUNCTION_GRAPH_TRACER
  71         select HAVE_GENERIC_DMA_COHERENT
  72         select HAVE_HW_BREAKPOINT if PERF_EVENTS
  73         select HAVE_IRQ_TIME_ACCOUNTING
  74         select HAVE_MEMBLOCK
  75         select HAVE_PATA_PLATFORM
  76         select HAVE_PERF_EVENTS
  77         select HAVE_PERF_REGS
  78         select HAVE_PERF_USER_STACK_DUMP
  79         select HAVE_RCU_TABLE_FREE
  80         select HAVE_SYSCALL_TRACEPOINTS
  81         select IOMMU_DMA if IOMMU_SUPPORT
  82         select IRQ_DOMAIN
  83         select IRQ_FORCED_THREADING
  84         select MODULES_USE_ELF_RELA
  85         select NO_BOOTMEM
  86         select OF
  87         select OF_EARLY_FLATTREE
  88         select OF_RESERVED_MEM
  89         select PERF_USE_VMALLOC
  90         select POWER_RESET
  91         select POWER_SUPPLY
  92         select RTC_LIB
  93         select SPARSE_IRQ
  94         select SYSCTL_EXCEPTION_TRACE
  95         select HAVE_CONTEXT_TRACKING
  96         select HAVE_ARM_SMCCC
  97         help
  98           ARM 64-bit (AArch64) Linux support.
  99
 100 config 64BIT
 101         def_bool y
 102
 103 config ARCH_PHYS_ADDR_T_64BIT
 104         def_bool y
 105
 106 config MMU
 107         def_bool y
 108
 109 config NO_IOPORT_MAP
 110         def_bool y if !PCI
 111
 112 config STACKTRACE_SUPPORT
 113         def_bool y
 114
 115 config ILLEGAL_POINTER_VALUE
 116         hex
 117         default 0xdead000000000000
 118
 119 config LOCKDEP_SUPPORT
 120         def_bool y
 121
 122 config TRACE_IRQFLAGS_SUPPORT
 123         def_bool y
 124
 125 config RWSEM_XCHGADD_ALGORITHM
 126         def_bool y
 127
 128 config GENERIC_BUG
 129         def_bool y
 130         depends on BUG
 131
 132 config GENERIC_BUG_RELATIVE_POINTERS
 133         def_bool y
 134         depends on GENERIC_BUG
 135
 136 config GENERIC_HWEIGHT
 137         def_bool y
 138
 139 config GENERIC_CSUM
 140         def_bool y
 141
 142 config GENERIC_CALIBRATE_DELAY
 143         def_bool y
 144
 145 config ZONE_DMA
 146         def_bool y
 147
 148 config HAVE_GENERIC_RCU_GUP
 149         def_bool y
 150
 151 config ARCH_DMA_ADDR_T_64BIT
 152         def_bool y
 153
 154 config NEED_DMA_MAP_STATE
 155         def_bool y
 156
 157 config NEED_SG_DMA_LENGTH
 158         def_bool y
 159
 160 config SMP
 161         def_bool y
 162
 163 config SWIOTLB
 164         def_bool y
 165
 166 config IOMMU_HELPER
 167         def_bool SWIOTLB
 168
 169 config KERNEL_MODE_NEON
 170         def_bool y
 171
 172 config FIX_EARLYCON_MEM
 173         def_bool y
 174
 175 config PGTABLE_LEVELS
 176         int
 177         default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 178         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 179         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 180         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 181         default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 182         default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 183
 184 source "init/Kconfig"
 185
 186 source "kernel/Kconfig.freezer"
 187
 188 source "arch/arm64/Kconfig.platforms"
 189
 190 menu "Bus support"
 191
 192 config PCI
 193         bool "PCI support"
 194         help
 195           This feature enables support for PCI bus system. If you say Y
 196           here, the kernel will include drivers and infrastructure code
 197           to support PCI bus devices.
 198
 199 config PCI_DOMAINS
 200         def_bool PCI
 201
 202 config PCI_DOMAINS_GENERIC
 203         def_bool PCI
 204
 205 config PCI_SYSCALL
 206         def_bool PCI
 207
 208 source "drivers/pci/Kconfig"
 209 source "drivers/pci/pcie/Kconfig"
 210 source "drivers/pci/hotplug/Kconfig"
 211
 212 endmenu
 213
 214 menu "Kernel Features"
 215
 216 menu "ARM errata workarounds via the alternatives framework"
 217
 218 config ARM64_ERRATUM_826319
 219         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 220         default y
 221         help
 222           This option adds an alternative code sequence to work around ARM
 223           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 224           AXI master interface and an L2 cache.
 225
 226           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 227           and is unable to accept a certain write via this interface, it will
 228           not progress on read data presented on the read data channel and the
 229           system can deadlock.
 230
 231           The workaround promotes data cache clean instructions to
 232           data cache clean-and-invalidate.
 233           Please note that this does not necessarily enable the workaround,
 234           as it depends on the alternative framework, which will only patch
 235           the kernel if an affected CPU is detected.
 236
 237           If unsure, say Y.
 238
 239 config ARM64_ERRATUM_827319
 240         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 241         default y
 242         help
 243           This option adds an alternative code sequence to work around ARM
 244           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 245           master interface and an L2 cache.
 246
 247           Under certain conditions this erratum can cause a clean line eviction
 248           to occur at the same time as another transaction to the same address
 249           on the AMBA 5 CHI interface, which can cause data corruption if the
 250           interconnect reorders the two transactions.
 251
 252           The workaround promotes data cache clean instructions to
 253           data cache clean-and-invalidate.
 254           Please note that this does not necessarily enable the workaround,
 255           as it depends on the alternative framework, which will only patch
 256           the kernel if an affected CPU is detected.
 257
 258           If unsure, say Y.
 259
 260 config ARM64_ERRATUM_824069
 261         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 262         default y
 263         help
 264           This option adds an alternative code sequence to work around ARM
 265           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 266           to a coherent interconnect.
 267
 268           If a Cortex-A53 processor is executing a store or prefetch for
 269           write instruction at the same time as a processor in another
 270           cluster is executing a cache maintenance operation to the same
 271           address, then this erratum might cause a clean cache line to be
 272           incorrectly marked as dirty.
 273
 274           The workaround promotes data cache clean instructions to
 275           data cache clean-and-invalidate.
 276           Please note that this option does not necessarily enable the
 277           workaround, as it depends on the alternative framework, which will
 278           only patch the kernel if an affected CPU is detected.
 279
 280           If unsure, say Y.
 281
 282 config ARM64_ERRATUM_819472
 283         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 284         default y
 285         help
 286           This option adds an alternative code sequence to work around ARM
 287           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 288           present when it is connected to a coherent interconnect.
 289
 290           If the processor is executing a load and store exclusive sequence at
 291           the same time as a processor in another cluster is executing a cache
 292           maintenance operation to the same address, then this erratum might
 293           cause data corruption.
 294
 295           The workaround promotes data cache clean instructions to
 296           data cache clean-and-invalidate.
 297           Please note that this does not necessarily enable the workaround,
 298           as it depends on the alternative framework, which will only patch
 299           the kernel if an affected CPU is detected.
 300
 301           If unsure, say Y.
 302
 303 config ARM64_ERRATUM_832075
 304         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 305         default y
 306         help
 307           This option adds an alternative code sequence to work around ARM
 308           erratum 832075 on Cortex-A57 parts up to r1p2.
 309
 310           Affected Cortex-A57 parts might deadlock when exclusive load/store
 311           instructions to Write-Back memory are mixed with Device loads.
 312
 313           The workaround is to promote device loads to use Load-Acquire
 314           semantics.
 315           Please note that this does not necessarily enable the workaround,
 316           as it depends on the alternative framework, which will only patch
 317           the kernel if an affected CPU is detected.
 318
 319           If unsure, say Y.
 320
 321 config ARM64_ERRATUM_834220
 322         bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 323         depends on KVM
 324         default y
 325         help
 326           This option adds an alternative code sequence to work around ARM
 327           erratum 834220 on Cortex-A57 parts up to r1p2.
 328
 329           Affected Cortex-A57 parts might report a Stage 2 translation
 330           fault as the result of a Stage 1 fault for load crossing a
 331           page boundary when there is a permission or device memory
 332           alignment fault at Stage 1 and a translation fault at Stage 2.
 333
 334           The workaround is to verify that the Stage 1 translation
 335           doesn't generate a fault before handling the Stage 2 fault.
 336           Please note that this does not necessarily enable the workaround,
 337           as it depends on the alternative framework, which will only patch
 338           the kernel if an affected CPU is detected.
 339
 340           If unsure, say Y.
 341
 342 config ARM64_ERRATUM_845719
 343         bool "Cortex-A53: 845719: a load might read incorrect data"
 344         depends on COMPAT
 345         default y
 346         help
 347           This option adds an alternative code sequence to work around ARM
 348           erratum 845719 on Cortex-A53 parts up to r0p4.
 349
 350           When running a compat (AArch32) userspace on an affected Cortex-A53
 351           part, a load at EL0 from a virtual address that matches the bottom 32
 352           bits of the virtual address used by a recent load at (AArch64) EL1
 353           might return incorrect data.
 354
 355           The workaround is to write the contextidr_el1 register on exception
 356           return to a 32-bit task.
 357           Please note that this does not necessarily enable the workaround,
 358           as it depends on the alternative framework, which will only patch
 359           the kernel if an affected CPU is detected.
 360
 361           If unsure, say Y.
 362
 363 config ARM64_ERRATUM_843419
 364         bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 365         depends on MODULES
 366         default y
 367         help
 368           This option builds kernel modules using the large memory model in
 369           order to avoid the use of the ADRP instruction, which can cause
 370           a subsequent memory access to use an incorrect address on Cortex-A53
 371           parts up to r0p4.
 372
 373           Note that the kernel itself must be linked with a version of ld
 374           which fixes potentially affected ADRP instructions through the
 375           use of veneers.
 376
 377           If unsure, say Y.
 378
 379 config CAVIUM_ERRATUM_22375
 380         bool "Cavium erratum 22375, 24313"
 381         default y
 382         help
 383           Enable workaround for erratum 22375, 24313.
 384
 385           This implements two gicv3-its errata workarounds for ThunderX. Both
 386           with small impact affecting only ITS table allocation.
 387
 388             erratum 22375: only alloc 8MB table size
 389             erratum 24313: ignore memory access type
 390
 391           The fixes are in ITS initialization and basically ignore memory access
 392           type and table size provided by the TYPER and BASER registers.
 393
 394           If unsure, say Y.
 395
 396 config CAVIUM_ERRATUM_23154
 397         bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 398         default y
 399         help
 400           The gicv3 of ThunderX requires a modified version for
 401           reading the IAR status to ensure data synchronization
 402           (access to icc_iar1_el1 is not sync'ed before and after).
 403
 404           If unsure, say Y.
 405
 406 endmenu
 407
 408
 409 choice
 410         prompt "Page size"
 411         default ARM64_4K_PAGES
 412         help
 413           Page size (translation granule) configuration.
 414
 415 config ARM64_4K_PAGES
 416         bool "4KB"
 417         help
 418           This feature enables 4KB pages support.
 419
 420 config ARM64_16K_PAGES
 421         bool "16KB"
 422         help
 423           The system will use 16KB pages support. AArch32 emulation
 424           requires applications compiled with 16K (or a multiple of 16K)
 425           aligned segments.
 426
 427 config ARM64_64K_PAGES
 428         bool "64KB"
 429         help
 430           This feature enables 64KB pages support (4KB by default)
 431           allowing only two levels of page tables and faster TLB
 432           look-up. AArch32 emulation requires applications compiled
 433           with 64K aligned segments.
 434
 435 endchoice
 436
 437 choice
 438         prompt "Virtual address space size"
 439         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 440         default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 441         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 442         help
 443           Allows choosing one of multiple possible virtual address
 444           space sizes. The level of translation table is determined by
 445           a combination of page size and virtual address space size.
 446
 447 config ARM64_VA_BITS_36
 448         bool "36-bit" if EXPERT
 449         depends on ARM64_16K_PAGES
 450
 451 config ARM64_VA_BITS_39
 452         bool "39-bit"
 453         depends on ARM64_4K_PAGES
 454
 455 config ARM64_VA_BITS_42
 456         bool "42-bit"
 457         depends on ARM64_64K_PAGES
 458
 459 config ARM64_VA_BITS_47
 460         bool "47-bit"
 461         depends on ARM64_16K_PAGES
 462
 463 config ARM64_VA_BITS_48
 464         bool "48-bit"
 465
 466 endchoice
 467
 468 config ARM64_VA_BITS
 469         int
 470         default 36 if ARM64_VA_BITS_36
 471         default 39 if ARM64_VA_BITS_39
 472         default 42 if ARM64_VA_BITS_42
 473         default 47 if ARM64_VA_BITS_47
 474         default 48 if ARM64_VA_BITS_48
 475
 476 config CPU_BIG_ENDIAN
 477        bool "Build big-endian kernel"
 478        help
 479          Say Y if you plan on running a kernel in big-endian mode.
 480
 481 config SCHED_MC
 482         bool "Multi-core scheduler support"
 483         help
 484           Multi-core scheduler support improves the CPU scheduler's decision
 485           making when dealing with multi-core CPU chips at a cost of slightly
 486           increased overhead in some places. If unsure say N here.
 487
 488 config SCHED_SMT
 489         bool "SMT scheduler support"
 490         help
 491           Improves the CPU scheduler's decision making when dealing with
 492           MultiThreading at a cost of slightly increased overhead in some
 493           places. If unsure say N here.
 494
 495 config NR_CPUS
 496         int "Maximum number of CPUs (2-4096)"
 497         range 2 4096
 498         # These have to remain sorted largest to smallest
 499         default "64"
 500
 501 config HOTPLUG_CPU
 502         bool "Support for hot-pluggable CPUs"
 503         select GENERIC_IRQ_MIGRATION
 504         help
 505           Say Y here to experiment with turning CPUs off and on.  CPUs
 506           can be controlled through /sys/devices/system/cpu.
 507
 508 source kernel/Kconfig.preempt
 509 source kernel/Kconfig.hz
 510
 511 config ARCH_HAS_HOLES_MEMORYMODEL
 512         def_bool y if SPARSEMEM
 513
 514 config ARCH_SPARSEMEM_ENABLE
 515         def_bool y
 516         select SPARSEMEM_VMEMMAP_ENABLE
 517
 518 config ARCH_SPARSEMEM_DEFAULT
 519         def_bool ARCH_SPARSEMEM_ENABLE
 520
 521 config ARCH_SELECT_MEMORY_MODEL
 522         def_bool ARCH_SPARSEMEM_ENABLE
 523
 524 config HAVE_ARCH_PFN_VALID
 525         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 526
 527 config HW_PERF_EVENTS
 528         def_bool y
 529         depends on ARM_PMU
 530
 531 config SYS_SUPPORTS_HUGETLBFS
 532         def_bool y
 533
 534 config ARCH_WANT_HUGE_PMD_SHARE
 535         def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
 536
 537 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 538         def_bool y
 539
 540 config ARCH_HAS_CACHE_LINE_SIZE
 541         def_bool y
 542
 543 source "mm/Kconfig"
 544
 545 config SECCOMP
 546         bool "Enable seccomp to safely compute untrusted bytecode"
 547         ---help---
 548           This kernel feature is useful for number crunching applications
 549           that may need to compute untrusted bytecode during their
 550           execution. By using pipes or other transports made available to
 551           the process as file descriptors supporting the read/write
 552           syscalls, it's possible to isolate those applications in
 553           their own address space using seccomp. Once seccomp is
 554           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 555           and the task is only allowed to execute a few safe syscalls
 556           defined by each seccomp mode.
 557
 558 config PARAVIRT
 559         bool "Enable paravirtualization code"
 560         help
 561           This changes the kernel so it can modify itself when it is run
 562           under a hypervisor, potentially improving performance significantly
 563           over full virtualization.
 564
 565 config PARAVIRT_TIME_ACCOUNTING
 566         bool "Paravirtual steal time accounting"
 567         select PARAVIRT
 568         default n
 569         help
 570           Select this option to enable fine granularity task steal time
 571           accounting. Time spent executing other tasks in parallel with
 572           the current vCPU is discounted from the vCPU power. To account for
 573           that, there can be a small performance impact.
 574
 575           If in doubt, say N here.
 576
 577 config XEN_DOM0
 578         def_bool y
 579         depends on XEN
 580
 581 config XEN
 582         bool "Xen guest support on ARM64"
 583         depends on ARM64 && OF
 584         select SWIOTLB_XEN
 585         select PARAVIRT
 586         help
 587           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
 588
 589 config FORCE_MAX_ZONEORDER
 590         int
 591         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
 592         default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
 593         default "11"
 594         help
 595           The kernel memory allocator divides physically contiguous memory
 596           blocks into "zones", where each zone is a power of two number of
 597           pages.  This option selects the largest power of two that the kernel
 598           keeps in the memory allocator.  If you need to allocate very large
 599           blocks of physically contiguous memory, then you may need to
 600           increase this value.
 601
 602           This config option is actually maximum order plus one. For example,
 603           a value of 11 means that the largest free memory block is 2^10 pages.
 604
 605           We make sure that we can allocate upto a HugePage size for each configuration.
 606           Hence we have :
 607                 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
 608
 609           However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
 610           4M allocations matching the default size used by generic code.
 611
 612 menuconfig ARMV8_DEPRECATED
 613         bool "Emulate deprecated/obsolete ARMv8 instructions"
 614         depends on COMPAT
 615         help
 616           Legacy software support may require certain instructions
 617           that have been deprecated or obsoleted in the architecture.
 618
 619           Enable this config to enable selective emulation of these
 620           features.
 621
 622           If unsure, say Y
 623
 624 if ARMV8_DEPRECATED
 625
 626 config SWP_EMULATION
 627         bool "Emulate SWP/SWPB instructions"
 628         help
 629           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
 630           they are always undefined. Say Y here to enable software
 631           emulation of these instructions for userspace using LDXR/STXR.
 632
 633           In some older versions of glibc [<=2.8] SWP is used during futex
 634           trylock() operations with the assumption that the code will not
 635           be preempted. This invalid assumption may be more likely to fail
 636           with SWP emulation enabled, leading to deadlock of the user
 637           application.
 638
 639           NOTE: when accessing uncached shared regions, LDXR/STXR rely
 640           on an external transaction monitoring block called a global
 641           monitor to maintain update atomicity. If your system does not
 642           implement a global monitor, this option can cause programs that
 643           perform SWP operations to uncached memory to deadlock.
 644
 645           If unsure, say Y
 646
 647 config CP15_BARRIER_EMULATION
 648         bool "Emulate CP15 Barrier instructions"
 649         help
 650           The CP15 barrier instructions - CP15ISB, CP15DSB, and
 651           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
 652           strongly recommended to use the ISB, DSB, and DMB
 653           instructions instead.
 654
 655           Say Y here to enable software emulation of these
 656           instructions for AArch32 userspace code. When this option is
 657           enabled, CP15 barrier usage is traced which can help
 658           identify software that needs updating.
 659
 660           If unsure, say Y
 661
 662 config SETEND_EMULATION
 663         bool "Emulate SETEND instruction"
 664         help
 665           The SETEND instruction alters the data-endianness of the
 666           AArch32 EL0, and is deprecated in ARMv8.
 667
 668           Say Y here to enable software emulation of the instruction
 669           for AArch32 userspace code.
 670
 671           Note: All the cpus on the system must have mixed endian support at EL0
 672           for this feature to be enabled. If a new CPU - which doesn't support mixed
 673           endian - is hotplugged in after this feature has been enabled, there could
 674           be unexpected results in the applications.
 675
 676           If unsure, say Y
 677 endif
 678
 679 menu "ARMv8.1 architectural features"
 680
 681 config ARM64_HW_AFDBM
 682         bool "Support for hardware updates of the Access and Dirty page flags"
 683         default y
 684         help
 685           The ARMv8.1 architecture extensions introduce support for
 686           hardware updates of the access and dirty information in page
 687           table entries. When enabled in TCR_EL1 (HA and HD bits) on
 688           capable processors, accesses to pages with PTE_AF cleared will
 689           set this bit instead of raising an access flag fault.
 690           Similarly, writes to read-only pages with the DBM bit set will
 691           clear the read-only bit (AP[2]) instead of raising a
 692           permission fault.
 693
 694           Kernels built with this configuration option enabled continue
 695           to work on pre-ARMv8.1 hardware and the performance impact is
 696           minimal. If unsure, say Y.
 697
 698 config ARM64_PAN
 699         bool "Enable support for Privileged Access Never (PAN)"
 700         default y
 701         help
 702          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
 703          prevents the kernel or hypervisor from accessing user-space (EL0)
 704          memory directly.
 705
 706          Choosing this option will cause any unprotected (not using
 707          copy_to_user et al) memory access to fail with a permission fault.
 708
 709          The feature is detected at runtime, and will remain as a 'nop'
 710          instruction if the cpu does not implement the feature.
 711
 712 config ARM64_LSE_ATOMICS
 713         bool "Atomic instructions"
 714         help
 715           As part of the Large System Extensions, ARMv8.1 introduces new
 716           atomic instructions that are designed specifically to scale in
 717           very large systems.
 718
 719           Say Y here to make use of these instructions for the in-kernel
 720           atomic routines. This incurs a small overhead on CPUs that do
 721           not support these instructions and requires the kernel to be
 722           built with binutils >= 2.25.
 723
 724 endmenu
 725
 726 endmenu
 727
 728 menu "Boot options"
 729
 730 config CMDLINE
 731         string "Default kernel command string"
 732         default ""
 733         help
 734           Provide a set of default command-line options at build time by
 735           entering them here. As a minimum, you should specify the the
 736           root device (e.g. root=/dev/nfs).
 737
 738 config CMDLINE_FORCE
 739         bool "Always use the default kernel command string"
 740         help
 741           Always use the default kernel command string, even if the boot
 742           loader passes other arguments to the kernel.
 743           This is useful if you cannot or don't want to change the
 744           command-line options your boot loader passes to the kernel.
 745
 746 config EFI_STUB
 747         bool
 748
 749 config EFI
 750         bool "UEFI runtime support"
 751         depends on OF && !CPU_BIG_ENDIAN
 752         select LIBFDT
 753         select UCS2_STRING
 754         select EFI_PARAMS_FROM_FDT
 755         select EFI_RUNTIME_WRAPPERS
 756         select EFI_STUB
 757         select EFI_ARMSTUB
 758         default y
 759         help
 760           This option provides support for runtime services provided
 761           by UEFI firmware (such as non-volatile variables, realtime
 762           clock, and platform reset). A UEFI stub is also provided to
 763           allow the kernel to be booted as an EFI application. This
 764           is only useful on systems that have UEFI firmware.
 765
 766 config DMI
 767         bool "Enable support for SMBIOS (DMI) tables"
 768         depends on EFI
 769         default y
 770         help
 771           This enables SMBIOS/DMI feature for systems.
 772
 773           This option is only useful on systems that have UEFI firmware.
 774           However, even with this option, the resultant kernel should
 775           continue to boot on existing non-UEFI platforms.
 776
 777 endmenu
 778
 779 menu "Userspace binary formats"
 780
 781 source "fs/Kconfig.binfmt"
 782
 783 config COMPAT
 784         bool "Kernel support for 32-bit EL0"
 785         depends on ARM64_4K_PAGES || EXPERT
 786         select COMPAT_BINFMT_ELF
 787         select HAVE_UID16
 788         select OLD_SIGSUSPEND3
 789         select COMPAT_OLD_SIGACTION
 790         help
 791           This option enables support for a 32-bit EL0 running under a 64-bit
 792           kernel at EL1. AArch32-specific components such as system calls,
 793           the user helper functions, VFP support and the ptrace interface are
 794           handled appropriately by the kernel.
 795
 796           If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
 797           that you will only be able to execute AArch32 binaries that were compiled
 798           with page size aligned segments.
 799
 800           If you want to execute 32-bit userspace applications, say Y.
 801
 802 config SYSVIPC_COMPAT
 803         def_bool y
 804         depends on COMPAT && SYSVIPC
 805
 806 endmenu
 807
 808 menu "Power management options"
 809
 810 source "kernel/power/Kconfig"
 811
 812 config ARCH_SUSPEND_POSSIBLE
 813         def_bool y
 814
 815 endmenu
 816
 817 menu "CPU Power Management"
 818
 819 source "drivers/cpuidle/Kconfig"
 820
 821 source "drivers/cpufreq/Kconfig"
 822
 823 endmenu
 824
 825 source "net/Kconfig"
 826
 827 source "drivers/Kconfig"
 828
 829 source "drivers/firmware/Kconfig"
 830
 831 source "drivers/acpi/Kconfig"
 832
 833 source "fs/Kconfig"
 834
 835 source "arch/arm64/kvm/Kconfig"
 836
 837 source "arch/arm64/Kconfig.debug"
 838
 839 source "security/Kconfig"
 840
 841 source "crypto/Kconfig"
 842 if CRYPTO
 843 source "arch/arm64/crypto/Kconfig"
 844 endif
 845
 846 source "lib/Kconfig"