1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
15 select ARCH_ENABLE_MEMORY_HOTPLUG
16 select ARCH_ENABLE_MEMORY_HOTREMOVE
17 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
18 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
19 select ARCH_HAS_CACHE_LINE_SIZE
20 select ARCH_HAS_DEBUG_VIRTUAL
21 select ARCH_HAS_DEBUG_VM_PGTABLE
22 select ARCH_HAS_DMA_PREP_COHERENT
23 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
24 select ARCH_HAS_FAST_MULTIPLIER
25 select ARCH_HAS_FORTIFY_SOURCE
26 select ARCH_HAS_GCOV_PROFILE_ALL
27 select ARCH_HAS_GIGANTIC_PAGE
29 select ARCH_HAS_KEEPINITRD
30 select ARCH_HAS_MEMBARRIER_SYNC_CORE
31 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
32 select ARCH_HAS_PTE_DEVMAP
33 select ARCH_HAS_PTE_SPECIAL
34 select ARCH_HAS_SETUP_DMA_OPS
35 select ARCH_HAS_SET_DIRECT_MAP
36 select ARCH_HAS_SET_MEMORY
38 select ARCH_HAS_STRICT_KERNEL_RWX
39 select ARCH_HAS_STRICT_MODULE_RWX
40 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
41 select ARCH_HAS_SYNC_DMA_FOR_CPU
42 select ARCH_HAS_SYSCALL_WRAPPER
43 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
44 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
45 select ARCH_HAS_ZONE_DMA_SET if EXPERT
46 select ARCH_HAVE_ELF_PROT
47 select ARCH_HAVE_NMI_SAFE_CMPXCHG
48 select ARCH_INLINE_READ_LOCK if !PREEMPTION
49 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
52 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
56 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
70 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
74 select ARCH_KEEP_MEMBLOCK
75 select ARCH_USE_CMPXCHG_LOCKREF
76 select ARCH_USE_GNU_PROPERTY
77 select ARCH_USE_MEMTEST
78 select ARCH_USE_QUEUED_RWLOCKS
79 select ARCH_USE_QUEUED_SPINLOCKS
80 select ARCH_USE_SYM_ANNOTATIONS
81 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
82 select ARCH_SUPPORTS_HUGETLBFS
83 select ARCH_SUPPORTS_MEMORY_FAILURE
84 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
85 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
86 select ARCH_SUPPORTS_LTO_CLANG_THIN
87 select ARCH_SUPPORTS_CFI_CLANG
88 select ARCH_SUPPORTS_ATOMIC_RMW
89 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
90 select ARCH_SUPPORTS_NUMA_BALANCING
91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
92 select ARCH_WANT_DEFAULT_BPF_JIT
93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
94 select ARCH_WANT_FRAME_POINTERS
95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
96 select ARCH_WANT_LD_ORPHAN_WARN
97 select ARCH_WANTS_NO_INSTR
98 select ARCH_HAS_UBSAN_SANITIZE_ALL
100 select ARM_ARCH_TIMER
102 select AUDIT_ARCH_COMPAT_GENERIC
103 select ARM_GIC_V2M if PCI
105 select ARM_GIC_V3_ITS if PCI
107 select BUILDTIME_TABLE_SORT
108 select CLONE_BACKWARDS
110 select CPU_PM if (SUSPEND || CPU_IDLE)
112 select DCACHE_WORD_ACCESS
113 select DMA_DIRECT_REMAP
116 select GENERIC_ALLOCATOR
117 select GENERIC_ARCH_TOPOLOGY
118 select GENERIC_CLOCKEVENTS_BROADCAST
119 select GENERIC_CPU_AUTOPROBE
120 select GENERIC_CPU_VULNERABILITIES
121 select GENERIC_EARLY_IOREMAP
122 select GENERIC_FIND_FIRST_BIT
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_TIME_VSYSCALL
134 select GENERIC_GETTIMEOFDAY
135 select GENERIC_VDSO_TIME_NS
136 select HANDLE_DOMAIN_IRQ
137 select HARDIRQS_SW_RESEND
141 select HAVE_ACPI_APEI if (ACPI && EFI)
142 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
143 select HAVE_ARCH_AUDITSYSCALL
144 select HAVE_ARCH_BITREVERSE
145 select HAVE_ARCH_COMPILER_H
146 select HAVE_ARCH_HUGE_VMAP
147 select HAVE_ARCH_JUMP_LABEL
148 select HAVE_ARCH_JUMP_LABEL_RELATIVE
149 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
150 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
151 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
152 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
153 select HAVE_ARCH_KFENCE
154 select HAVE_ARCH_KGDB
155 select HAVE_ARCH_MMAP_RND_BITS
156 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
157 select HAVE_ARCH_PREL32_RELOCATIONS
158 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
159 select HAVE_ARCH_SECCOMP_FILTER
160 select HAVE_ARCH_STACKLEAK
161 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
162 select HAVE_ARCH_TRACEHOOK
163 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
164 select HAVE_ARCH_VMAP_STACK
165 select HAVE_ARM_SMCCC
166 select HAVE_ASM_MODVERSIONS
168 select HAVE_C_RECORDMCOUNT
169 select HAVE_CMPXCHG_DOUBLE
170 select HAVE_CMPXCHG_LOCAL
171 select HAVE_CONTEXT_TRACKING
172 select HAVE_DEBUG_KMEMLEAK
173 select HAVE_DMA_CONTIGUOUS
174 select HAVE_DYNAMIC_FTRACE
175 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
176 if $(cc-option,-fpatchable-function-entry=2)
177 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
178 if DYNAMIC_FTRACE_WITH_REGS
179 select HAVE_EFFICIENT_UNALIGNED_ACCESS
181 select HAVE_FTRACE_MCOUNT_RECORD
182 select HAVE_FUNCTION_TRACER
183 select HAVE_FUNCTION_ERROR_INJECTION
184 select HAVE_FUNCTION_GRAPH_TRACER
185 select HAVE_GCC_PLUGINS
186 select HAVE_HW_BREAKPOINT if PERF_EVENTS
187 select HAVE_IRQ_TIME_ACCOUNTING
189 select HAVE_PATA_PLATFORM
190 select HAVE_PERF_EVENTS
191 select HAVE_PERF_REGS
192 select HAVE_PERF_USER_STACK_DUMP
193 select HAVE_REGS_AND_STACK_ACCESS_API
194 select HAVE_FUNCTION_ARG_ACCESS_API
195 select HAVE_FUTEX_CMPXCHG if FUTEX
196 select MMU_GATHER_RCU_TABLE_FREE
198 select HAVE_STACKPROTECTOR
199 select HAVE_SYSCALL_TRACEPOINTS
201 select HAVE_KRETPROBES
202 select HAVE_GENERIC_VDSO
203 select IOMMU_DMA if IOMMU_SUPPORT
205 select IRQ_FORCED_THREADING
206 select KASAN_VMALLOC if KASAN_GENERIC
207 select MODULES_USE_ELF_RELA
208 select NEED_DMA_MAP_STATE
209 select NEED_SG_DMA_LENGTH
211 select OF_EARLY_FLATTREE
212 select PCI_DOMAINS_GENERIC if PCI
213 select PCI_ECAM if (ACPI && PCI)
214 select PCI_SYSCALL if PCI
219 select SYSCTL_EXCEPTION_TRACE
220 select THREAD_INFO_IN_TASK
221 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
222 select TRACE_IRQFLAGS_SUPPORT
224 ARM 64-bit (AArch64) Linux support.
232 config ARM64_PAGE_SHIFT
234 default 16 if ARM64_64K_PAGES
235 default 14 if ARM64_16K_PAGES
238 config ARM64_CONT_PTE_SHIFT
240 default 5 if ARM64_64K_PAGES
241 default 7 if ARM64_16K_PAGES
244 config ARM64_CONT_PMD_SHIFT
246 default 5 if ARM64_64K_PAGES
247 default 5 if ARM64_16K_PAGES
250 config ARCH_MMAP_RND_BITS_MIN
251 default 14 if ARM64_64K_PAGES
252 default 16 if ARM64_16K_PAGES
255 # max bits determined by the following formula:
256 # VA_BITS - PAGE_SHIFT - 3
257 config ARCH_MMAP_RND_BITS_MAX
258 default 19 if ARM64_VA_BITS=36
259 default 24 if ARM64_VA_BITS=39
260 default 27 if ARM64_VA_BITS=42
261 default 30 if ARM64_VA_BITS=47
262 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
263 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
264 default 33 if ARM64_VA_BITS=48
265 default 14 if ARM64_64K_PAGES
266 default 16 if ARM64_16K_PAGES
269 config ARCH_MMAP_RND_COMPAT_BITS_MIN
270 default 7 if ARM64_64K_PAGES
271 default 9 if ARM64_16K_PAGES
274 config ARCH_MMAP_RND_COMPAT_BITS_MAX
280 config STACKTRACE_SUPPORT
283 config ILLEGAL_POINTER_VALUE
285 default 0xdead000000000000
287 config LOCKDEP_SUPPORT
294 config GENERIC_BUG_RELATIVE_POINTERS
296 depends on GENERIC_BUG
298 config GENERIC_HWEIGHT
304 config GENERIC_CALIBRATE_DELAY
307 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
313 config KERNEL_MODE_NEON
316 config FIX_EARLYCON_MEM
319 config PGTABLE_LEVELS
321 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
322 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
323 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
324 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
325 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
326 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
328 config ARCH_SUPPORTS_UPROBES
331 config ARCH_PROC_KCORE_TEXT
334 config BROKEN_GAS_INST
335 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
337 config KASAN_SHADOW_OFFSET
339 depends on KASAN_GENERIC || KASAN_SW_TAGS
340 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
341 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
342 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
343 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
344 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
345 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
346 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
347 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
348 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
349 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
350 default 0xffffffffffffffff
352 source "arch/arm64/Kconfig.platforms"
354 menu "Kernel Features"
356 menu "ARM errata workarounds via the alternatives framework"
358 config ARM64_WORKAROUND_CLEAN_CACHE
361 config ARM64_ERRATUM_826319
362 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
364 select ARM64_WORKAROUND_CLEAN_CACHE
366 This option adds an alternative code sequence to work around ARM
367 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
368 AXI master interface and an L2 cache.
370 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
371 and is unable to accept a certain write via this interface, it will
372 not progress on read data presented on the read data channel and the
375 The workaround promotes data cache clean instructions to
376 data cache clean-and-invalidate.
377 Please note that this does not necessarily enable the workaround,
378 as it depends on the alternative framework, which will only patch
379 the kernel if an affected CPU is detected.
383 config ARM64_ERRATUM_827319
384 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
386 select ARM64_WORKAROUND_CLEAN_CACHE
388 This option adds an alternative code sequence to work around ARM
389 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
390 master interface and an L2 cache.
392 Under certain conditions this erratum can cause a clean line eviction
393 to occur at the same time as another transaction to the same address
394 on the AMBA 5 CHI interface, which can cause data corruption if the
395 interconnect reorders the two transactions.
397 The workaround promotes data cache clean instructions to
398 data cache clean-and-invalidate.
399 Please note that this does not necessarily enable the workaround,
400 as it depends on the alternative framework, which will only patch
401 the kernel if an affected CPU is detected.
405 config ARM64_ERRATUM_824069
406 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
408 select ARM64_WORKAROUND_CLEAN_CACHE
410 This option adds an alternative code sequence to work around ARM
411 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
412 to a coherent interconnect.
414 If a Cortex-A53 processor is executing a store or prefetch for
415 write instruction at the same time as a processor in another
416 cluster is executing a cache maintenance operation to the same
417 address, then this erratum might cause a clean cache line to be
418 incorrectly marked as dirty.
420 The workaround promotes data cache clean instructions to
421 data cache clean-and-invalidate.
422 Please note that this option does not necessarily enable the
423 workaround, as it depends on the alternative framework, which will
424 only patch the kernel if an affected CPU is detected.
428 config ARM64_ERRATUM_819472
429 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
431 select ARM64_WORKAROUND_CLEAN_CACHE
433 This option adds an alternative code sequence to work around ARM
434 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
435 present when it is connected to a coherent interconnect.
437 If the processor is executing a load and store exclusive sequence at
438 the same time as a processor in another cluster is executing a cache
439 maintenance operation to the same address, then this erratum might
440 cause data corruption.
442 The workaround promotes data cache clean instructions to
443 data cache clean-and-invalidate.
444 Please note that this does not necessarily enable the workaround,
445 as it depends on the alternative framework, which will only patch
446 the kernel if an affected CPU is detected.
450 config ARM64_ERRATUM_832075
451 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
454 This option adds an alternative code sequence to work around ARM
455 erratum 832075 on Cortex-A57 parts up to r1p2.
457 Affected Cortex-A57 parts might deadlock when exclusive load/store
458 instructions to Write-Back memory are mixed with Device loads.
460 The workaround is to promote device loads to use Load-Acquire
462 Please note that this does not necessarily enable the workaround,
463 as it depends on the alternative framework, which will only patch
464 the kernel if an affected CPU is detected.
468 config ARM64_ERRATUM_834220
469 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
473 This option adds an alternative code sequence to work around ARM
474 erratum 834220 on Cortex-A57 parts up to r1p2.
476 Affected Cortex-A57 parts might report a Stage 2 translation
477 fault as the result of a Stage 1 fault for load crossing a
478 page boundary when there is a permission or device memory
479 alignment fault at Stage 1 and a translation fault at Stage 2.
481 The workaround is to verify that the Stage 1 translation
482 doesn't generate a fault before handling the Stage 2 fault.
483 Please note that this does not necessarily enable the workaround,
484 as it depends on the alternative framework, which will only patch
485 the kernel if an affected CPU is detected.
489 config ARM64_ERRATUM_845719
490 bool "Cortex-A53: 845719: a load might read incorrect data"
494 This option adds an alternative code sequence to work around ARM
495 erratum 845719 on Cortex-A53 parts up to r0p4.
497 When running a compat (AArch32) userspace on an affected Cortex-A53
498 part, a load at EL0 from a virtual address that matches the bottom 32
499 bits of the virtual address used by a recent load at (AArch64) EL1
500 might return incorrect data.
502 The workaround is to write the contextidr_el1 register on exception
503 return to a 32-bit task.
504 Please note that this does not necessarily enable the workaround,
505 as it depends on the alternative framework, which will only patch
506 the kernel if an affected CPU is detected.
510 config ARM64_ERRATUM_843419
511 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
513 select ARM64_MODULE_PLTS if MODULES
515 This option links the kernel with '--fix-cortex-a53-843419' and
516 enables PLT support to replace certain ADRP instructions, which can
517 cause subsequent memory accesses to use an incorrect address on
518 Cortex-A53 parts up to r0p4.
522 config ARM64_LD_HAS_FIX_ERRATUM_843419
523 def_bool $(ld-option,--fix-cortex-a53-843419)
525 config ARM64_ERRATUM_1024718
526 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
529 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
531 Affected Cortex-A55 cores (all revisions) could cause incorrect
532 update of the hardware dirty bit when the DBM/AP bits are updated
533 without a break-before-make. The workaround is to disable the usage
534 of hardware DBM locally on the affected cores. CPUs not affected by
535 this erratum will continue to use the feature.
539 config ARM64_ERRATUM_1418040
540 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
544 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
545 errata 1188873 and 1418040.
547 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
548 cause register corruption when accessing the timer registers
549 from AArch32 userspace.
553 config ARM64_WORKAROUND_SPECULATIVE_AT
556 config ARM64_ERRATUM_1165522
557 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
559 select ARM64_WORKAROUND_SPECULATIVE_AT
561 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
563 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
564 corrupted TLBs by speculating an AT instruction during a guest
569 config ARM64_ERRATUM_1319367
570 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
572 select ARM64_WORKAROUND_SPECULATIVE_AT
574 This option adds work arounds for ARM Cortex-A57 erratum 1319537
575 and A72 erratum 1319367
577 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
578 speculating an AT instruction during a guest context switch.
582 config ARM64_ERRATUM_1530923
583 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
585 select ARM64_WORKAROUND_SPECULATIVE_AT
587 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
589 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
590 corrupted TLBs by speculating an AT instruction during a guest
595 config ARM64_WORKAROUND_REPEAT_TLBI
598 config ARM64_ERRATUM_1286807
599 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
601 select ARM64_WORKAROUND_REPEAT_TLBI
603 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
605 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
606 address for a cacheable mapping of a location is being
607 accessed by a core while another core is remapping the virtual
608 address to a new physical page using the recommended
609 break-before-make sequence, then under very rare circumstances
610 TLBI+DSB completes before a read using the translation being
611 invalidated has been observed by other observers. The
612 workaround repeats the TLBI+DSB operation.
614 config ARM64_ERRATUM_1463225
615 bool "Cortex-A76: Software Step might prevent interrupt recognition"
618 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
620 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
621 of a system call instruction (SVC) can prevent recognition of
622 subsequent interrupts when software stepping is disabled in the
623 exception handler of the system call and either kernel debugging
624 is enabled or VHE is in use.
626 Work around the erratum by triggering a dummy step exception
627 when handling a system call from a task that is being stepped
628 in a VHE configuration of the kernel.
632 config ARM64_ERRATUM_1542419
633 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
636 This option adds a workaround for ARM Neoverse-N1 erratum
639 Affected Neoverse-N1 cores could execute a stale instruction when
640 modified by another CPU. The workaround depends on a firmware
643 Workaround the issue by hiding the DIC feature from EL0. This
644 forces user-space to perform cache maintenance.
648 config ARM64_ERRATUM_1508412
649 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
652 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
654 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
655 of a store-exclusive or read of PAR_EL1 and a load with device or
656 non-cacheable memory attributes. The workaround depends on a firmware
659 KVM guests must also have the workaround implemented or they can
662 Work around the issue by inserting DMB SY barriers around PAR_EL1
663 register reads and warning KVM users. The DMB barrier is sufficient
664 to prevent a speculative PAR_EL1 read.
668 config CAVIUM_ERRATUM_22375
669 bool "Cavium erratum 22375, 24313"
672 Enable workaround for errata 22375 and 24313.
674 This implements two gicv3-its errata workarounds for ThunderX. Both
675 with a small impact affecting only ITS table allocation.
677 erratum 22375: only alloc 8MB table size
678 erratum 24313: ignore memory access type
680 The fixes are in ITS initialization and basically ignore memory access
681 type and table size provided by the TYPER and BASER registers.
685 config CAVIUM_ERRATUM_23144
686 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
690 ITS SYNC command hang for cross node io and collections/cpu mapping.
694 config CAVIUM_ERRATUM_23154
695 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
698 The gicv3 of ThunderX requires a modified version for
699 reading the IAR status to ensure data synchronization
700 (access to icc_iar1_el1 is not sync'ed before and after).
704 config CAVIUM_ERRATUM_27456
705 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
708 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
709 instructions may cause the icache to become corrupted if it
710 contains data for a non-current ASID. The fix is to
711 invalidate the icache when changing the mm context.
715 config CAVIUM_ERRATUM_30115
716 bool "Cavium erratum 30115: Guest may disable interrupts in host"
719 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
720 1.2, and T83 Pass 1.0, KVM guest execution may disable
721 interrupts in host. Trapping both GICv3 group-0 and group-1
722 accesses sidesteps the issue.
726 config CAVIUM_TX2_ERRATUM_219
727 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
730 On Cavium ThunderX2, a load, store or prefetch instruction between a
731 TTBR update and the corresponding context synchronizing operation can
732 cause a spurious Data Abort to be delivered to any hardware thread in
735 Work around the issue by avoiding the problematic code sequence and
736 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
737 trap handler performs the corresponding register access, skips the
738 instruction and ensures context synchronization by virtue of the
743 config FUJITSU_ERRATUM_010001
744 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
747 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
748 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
749 accesses may cause undefined fault (Data abort, DFSC=0b111111).
750 This fault occurs under a specific hardware condition when a
751 load/store instruction performs an address translation using:
752 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
753 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
754 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
755 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
757 The workaround is to ensure these bits are clear in TCR_ELx.
758 The workaround only affects the Fujitsu-A64FX.
762 config HISILICON_ERRATUM_161600802
763 bool "Hip07 161600802: Erroneous redistributor VLPI base"
766 The HiSilicon Hip07 SoC uses the wrong redistributor base
767 when issued ITS commands such as VMOVP and VMAPP, and requires
768 a 128kB offset to be applied to the target address in this commands.
772 config QCOM_FALKOR_ERRATUM_1003
773 bool "Falkor E1003: Incorrect translation due to ASID change"
776 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
777 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
778 in TTBR1_EL1, this situation only occurs in the entry trampoline and
779 then only for entries in the walk cache, since the leaf translation
780 is unchanged. Work around the erratum by invalidating the walk cache
781 entries for the trampoline before entering the kernel proper.
783 config QCOM_FALKOR_ERRATUM_1009
784 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
786 select ARM64_WORKAROUND_REPEAT_TLBI
788 On Falkor v1, the CPU may prematurely complete a DSB following a
789 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
790 one more time to fix the issue.
794 config QCOM_QDF2400_ERRATUM_0065
795 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
798 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
799 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
800 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
804 config QCOM_FALKOR_ERRATUM_E1041
805 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
808 Falkor CPU may speculatively fetch instructions from an improper
809 memory location when MMU translation is changed from SCTLR_ELn[M]=1
810 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
814 config NVIDIA_CARMEL_CNP_ERRATUM
815 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
818 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
819 invalidate shared TLB entries installed by a different core, as it would
820 on standard ARM cores.
824 config SOCIONEXT_SYNQUACER_PREITS
825 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
828 Socionext Synquacer SoCs implement a separate h/w block to generate
829 MSI doorbell writes with non-zero values for the device ID.
838 default ARM64_4K_PAGES
840 Page size (translation granule) configuration.
842 config ARM64_4K_PAGES
845 This feature enables 4KB pages support.
847 config ARM64_16K_PAGES
850 The system will use 16KB pages support. AArch32 emulation
851 requires applications compiled with 16K (or a multiple of 16K)
854 config ARM64_64K_PAGES
857 This feature enables 64KB pages support (4KB by default)
858 allowing only two levels of page tables and faster TLB
859 look-up. AArch32 emulation requires applications compiled
860 with 64K aligned segments.
865 prompt "Virtual address space size"
866 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
867 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
868 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
870 Allows choosing one of multiple possible virtual address
871 space sizes. The level of translation table is determined by
872 a combination of page size and virtual address space size.
874 config ARM64_VA_BITS_36
875 bool "36-bit" if EXPERT
876 depends on ARM64_16K_PAGES
878 config ARM64_VA_BITS_39
880 depends on ARM64_4K_PAGES
882 config ARM64_VA_BITS_42
884 depends on ARM64_64K_PAGES
886 config ARM64_VA_BITS_47
888 depends on ARM64_16K_PAGES
890 config ARM64_VA_BITS_48
893 config ARM64_VA_BITS_52
895 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
897 Enable 52-bit virtual addressing for userspace when explicitly
898 requested via a hint to mmap(). The kernel will also use 52-bit
899 virtual addresses for its own mappings (provided HW support for
900 this feature is available, otherwise it reverts to 48-bit).
902 NOTE: Enabling 52-bit virtual addressing in conjunction with
903 ARMv8.3 Pointer Authentication will result in the PAC being
904 reduced from 7 bits to 3 bits, which may have a significant
905 impact on its susceptibility to brute-force attacks.
907 If unsure, select 48-bit virtual addressing instead.
911 config ARM64_FORCE_52BIT
912 bool "Force 52-bit virtual addresses for userspace"
913 depends on ARM64_VA_BITS_52 && EXPERT
915 For systems with 52-bit userspace VAs enabled, the kernel will attempt
916 to maintain compatibility with older software by providing 48-bit VAs
917 unless a hint is supplied to mmap.
919 This configuration option disables the 48-bit compatibility logic, and
920 forces all userspace addresses to be 52-bit on HW that supports it. One
921 should only enable this configuration option for stress testing userspace
922 memory management code. If unsure say N here.
926 default 36 if ARM64_VA_BITS_36
927 default 39 if ARM64_VA_BITS_39
928 default 42 if ARM64_VA_BITS_42
929 default 47 if ARM64_VA_BITS_47
930 default 48 if ARM64_VA_BITS_48
931 default 52 if ARM64_VA_BITS_52
934 prompt "Physical address space size"
935 default ARM64_PA_BITS_48
937 Choose the maximum physical address range that the kernel will
940 config ARM64_PA_BITS_48
943 config ARM64_PA_BITS_52
944 bool "52-bit (ARMv8.2)"
945 depends on ARM64_64K_PAGES
946 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
948 Enable support for a 52-bit physical address space, introduced as
949 part of the ARMv8.2-LPA extension.
951 With this enabled, the kernel will also continue to work on CPUs that
952 do not support ARMv8.2-LPA, but with some added memory overhead (and
953 minor performance overhead).
959 default 48 if ARM64_PA_BITS_48
960 default 52 if ARM64_PA_BITS_52
964 default CPU_LITTLE_ENDIAN
966 Select the endianness of data accesses performed by the CPU. Userspace
967 applications will need to be compiled and linked for the endianness
968 that is selected here.
970 config CPU_BIG_ENDIAN
971 bool "Build big-endian kernel"
972 depends on !LD_IS_LLD || LLD_VERSION >= 130000
974 Say Y if you plan on running a kernel with a big-endian userspace.
976 config CPU_LITTLE_ENDIAN
977 bool "Build little-endian kernel"
979 Say Y if you plan on running a kernel with a little-endian userspace.
980 This is usually the case for distributions targeting arm64.
985 bool "Multi-core scheduler support"
987 Multi-core scheduler support improves the CPU scheduler's decision
988 making when dealing with multi-core CPU chips at a cost of slightly
989 increased overhead in some places. If unsure say N here.
992 bool "SMT scheduler support"
994 Improves the CPU scheduler's decision making when dealing with
995 MultiThreading at a cost of slightly increased overhead in some
996 places. If unsure say N here.
999 int "Maximum number of CPUs (2-4096)"
1004 bool "Support for hot-pluggable CPUs"
1005 select GENERIC_IRQ_MIGRATION
1007 Say Y here to experiment with turning CPUs off and on. CPUs
1008 can be controlled through /sys/devices/system/cpu.
1010 # Common NUMA Features
1012 bool "NUMA Memory Allocation and Scheduler Support"
1013 select GENERIC_ARCH_NUMA
1014 select ACPI_NUMA if ACPI
1017 Enable NUMA (Non-Uniform Memory Access) support.
1019 The kernel will try to allocate memory used by a CPU on the
1020 local memory of the CPU and add some more
1021 NUMA awareness to the kernel.
1024 int "Maximum NUMA Nodes (as a power of 2)"
1029 Specify the maximum number of NUMA Nodes available on the target
1030 system. Increases memory reserved to accommodate various tables.
1032 config USE_PERCPU_NUMA_NODE_ID
1036 config HAVE_SETUP_PER_CPU_AREA
1040 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1044 source "kernel/Kconfig.hz"
1046 config ARCH_SPARSEMEM_ENABLE
1048 select SPARSEMEM_VMEMMAP_ENABLE
1049 select SPARSEMEM_VMEMMAP
1051 config HW_PERF_EVENTS
1055 # Supported by clang >= 7.0
1056 config CC_HAVE_SHADOW_CALL_STACK
1057 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1060 bool "Enable paravirtualization code"
1062 This changes the kernel so it can modify itself when it is run
1063 under a hypervisor, potentially improving performance significantly
1064 over full virtualization.
1066 config PARAVIRT_TIME_ACCOUNTING
1067 bool "Paravirtual steal time accounting"
1070 Select this option to enable fine granularity task steal time
1071 accounting. Time spent executing other tasks in parallel with
1072 the current vCPU is discounted from the vCPU power. To account for
1073 that, there can be a small performance impact.
1075 If in doubt, say N here.
1078 depends on PM_SLEEP_SMP
1080 bool "kexec system call"
1082 kexec is a system call that implements the ability to shutdown your
1083 current kernel, and to start another kernel. It is like a reboot
1084 but it is independent of the system firmware. And like a reboot
1085 you can start any kernel with it, not just Linux.
1088 bool "kexec file based system call"
1090 select HAVE_IMA_KEXEC if IMA
1092 This is new version of kexec system call. This system call is
1093 file based and takes file descriptors as system call argument
1094 for kernel and initramfs as opposed to list of segments as
1095 accepted by previous system call.
1098 bool "Verify kernel signature during kexec_file_load() syscall"
1099 depends on KEXEC_FILE
1101 Select this option to verify a signature with loaded kernel
1102 image. If configured, any attempt of loading a image without
1103 valid signature will fail.
1105 In addition to that option, you need to enable signature
1106 verification for the corresponding kernel image type being
1107 loaded in order for this to work.
1109 config KEXEC_IMAGE_VERIFY_SIG
1110 bool "Enable Image signature verification support"
1112 depends on KEXEC_SIG
1113 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1115 Enable Image signature verification support.
1117 comment "Support for PE file signature verification disabled"
1118 depends on KEXEC_SIG
1119 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1122 bool "Build kdump crash kernel"
1124 Generate crash dump after being started by kexec. This should
1125 be normally only set in special crash dump kernels which are
1126 loaded in the main kernel with kexec-tools into a specially
1127 reserved region and then later executed after a crash by
1130 For more details see Documentation/admin-guide/kdump/kdump.rst
1134 depends on HIBERNATION
1141 bool "Xen guest support on ARM64"
1142 depends on ARM64 && OF
1146 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1148 config FORCE_MAX_ZONEORDER
1150 default "14" if ARM64_64K_PAGES
1151 default "13" if (ARCH_THUNDER && ARM64_4K_PAGES)
1152 default "12" if ARM64_16K_PAGES
1155 The kernel memory allocator divides physically contiguous memory
1156 blocks into "zones", where each zone is a power of two number of
1157 pages. This option selects the largest power of two that the kernel
1158 keeps in the memory allocator. If you need to allocate very large
1159 blocks of physically contiguous memory, then you may need to
1160 increase this value.
1162 This config option is actually maximum order plus one. For example,
1163 a value of 11 means that the largest free memory block is 2^10 pages.
1165 We make sure that we can allocate upto a HugePage size for each configuration.
1167 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1169 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1170 4M allocations matching the default size used by generic code.
1172 config UNMAP_KERNEL_AT_EL0
1173 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1176 Speculation attacks against some high-performance processors can
1177 be used to bypass MMU permission checks and leak kernel data to
1178 userspace. This can be defended against by unmapping the kernel
1179 when running in userspace, mapping it back in on exception entry
1180 via a trampoline page in the vector table.
1184 config MITIGATE_SPECTRE_BRANCH_HISTORY
1185 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1188 Speculation attacks against some high-performance processors can
1189 make use of branch history to influence future speculation.
1190 When taking an exception from user-space, a sequence of branches
1191 or a firmware call overwrites the branch history.
1193 config RODATA_FULL_DEFAULT_ENABLED
1194 bool "Apply r/o permissions of VM areas also to their linear aliases"
1197 Apply read-only attributes of VM areas to the linear alias of
1198 the backing pages as well. This prevents code or read-only data
1199 from being modified (inadvertently or intentionally) via another
1200 mapping of the same memory page. This additional enhancement can
1201 be turned off at runtime by passing rodata=[off|on] (and turned on
1202 with rodata=full if this option is set to 'n')
1204 This requires the linear region to be mapped down to pages,
1205 which may adversely affect performance in some cases.
1207 config ARM64_SW_TTBR0_PAN
1208 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1210 Enabling this option prevents the kernel from accessing
1211 user-space memory directly by pointing TTBR0_EL1 to a reserved
1212 zeroed area and reserved ASID. The user access routines
1213 restore the valid TTBR0_EL1 temporarily.
1215 config ARM64_TAGGED_ADDR_ABI
1216 bool "Enable the tagged user addresses syscall ABI"
1219 When this option is enabled, user applications can opt in to a
1220 relaxed ABI via prctl() allowing tagged addresses to be passed
1221 to system calls as pointer arguments. For details, see
1222 Documentation/arm64/tagged-address-abi.rst.
1225 bool "Kernel support for 32-bit EL0"
1226 depends on ARM64_4K_PAGES || EXPERT
1228 select OLD_SIGSUSPEND3
1229 select COMPAT_OLD_SIGACTION
1231 This option enables support for a 32-bit EL0 running under a 64-bit
1232 kernel at EL1. AArch32-specific components such as system calls,
1233 the user helper functions, VFP support and the ptrace interface are
1234 handled appropriately by the kernel.
1236 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1237 that you will only be able to execute AArch32 binaries that were compiled
1238 with page size aligned segments.
1240 If you want to execute 32-bit userspace applications, say Y.
1244 config KUSER_HELPERS
1245 bool "Enable kuser helpers page for 32-bit applications"
1248 Warning: disabling this option may break 32-bit user programs.
1250 Provide kuser helpers to compat tasks. The kernel provides
1251 helper code to userspace in read only form at a fixed location
1252 to allow userspace to be independent of the CPU type fitted to
1253 the system. This permits binaries to be run on ARMv4 through
1254 to ARMv8 without modification.
1256 See Documentation/arm/kernel_user_helpers.rst for details.
1258 However, the fixed address nature of these helpers can be used
1259 by ROP (return orientated programming) authors when creating
1262 If all of the binaries and libraries which run on your platform
1263 are built specifically for your platform, and make no use of
1264 these helpers, then you can turn this option off to hinder
1265 such exploits. However, in that case, if a binary or library
1266 relying on those helpers is run, it will not function correctly.
1268 Say N here only if you are absolutely certain that you do not
1269 need these helpers; otherwise, the safe option is to say Y.
1272 bool "Enable vDSO for 32-bit applications"
1273 depends on !CPU_BIG_ENDIAN
1274 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1275 select GENERIC_COMPAT_VDSO
1278 Place in the process address space of 32-bit applications an
1279 ELF shared object providing fast implementations of gettimeofday
1282 You must have a 32-bit build of glibc 2.22 or later for programs
1283 to seamlessly take advantage of this.
1285 config THUMB2_COMPAT_VDSO
1286 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1287 depends on COMPAT_VDSO
1290 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1291 otherwise with '-marm'.
1293 menuconfig ARMV8_DEPRECATED
1294 bool "Emulate deprecated/obsolete ARMv8 instructions"
1297 Legacy software support may require certain instructions
1298 that have been deprecated or obsoleted in the architecture.
1300 Enable this config to enable selective emulation of these
1307 config SWP_EMULATION
1308 bool "Emulate SWP/SWPB instructions"
1310 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1311 they are always undefined. Say Y here to enable software
1312 emulation of these instructions for userspace using LDXR/STXR.
1313 This feature can be controlled at runtime with the abi.swp
1314 sysctl which is disabled by default.
1316 In some older versions of glibc [<=2.8] SWP is used during futex
1317 trylock() operations with the assumption that the code will not
1318 be preempted. This invalid assumption may be more likely to fail
1319 with SWP emulation enabled, leading to deadlock of the user
1322 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1323 on an external transaction monitoring block called a global
1324 monitor to maintain update atomicity. If your system does not
1325 implement a global monitor, this option can cause programs that
1326 perform SWP operations to uncached memory to deadlock.
1330 config CP15_BARRIER_EMULATION
1331 bool "Emulate CP15 Barrier instructions"
1333 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1334 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1335 strongly recommended to use the ISB, DSB, and DMB
1336 instructions instead.
1338 Say Y here to enable software emulation of these
1339 instructions for AArch32 userspace code. When this option is
1340 enabled, CP15 barrier usage is traced which can help
1341 identify software that needs updating. This feature can be
1342 controlled at runtime with the abi.cp15_barrier sysctl.
1346 config SETEND_EMULATION
1347 bool "Emulate SETEND instruction"
1349 The SETEND instruction alters the data-endianness of the
1350 AArch32 EL0, and is deprecated in ARMv8.
1352 Say Y here to enable software emulation of the instruction
1353 for AArch32 userspace code. This feature can be controlled
1354 at runtime with the abi.setend sysctl.
1356 Note: All the cpus on the system must have mixed endian support at EL0
1357 for this feature to be enabled. If a new CPU - which doesn't support mixed
1358 endian - is hotplugged in after this feature has been enabled, there could
1359 be unexpected results in the applications.
1366 menu "ARMv8.1 architectural features"
1368 config ARM64_HW_AFDBM
1369 bool "Support for hardware updates of the Access and Dirty page flags"
1372 The ARMv8.1 architecture extensions introduce support for
1373 hardware updates of the access and dirty information in page
1374 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1375 capable processors, accesses to pages with PTE_AF cleared will
1376 set this bit instead of raising an access flag fault.
1377 Similarly, writes to read-only pages with the DBM bit set will
1378 clear the read-only bit (AP[2]) instead of raising a
1381 Kernels built with this configuration option enabled continue
1382 to work on pre-ARMv8.1 hardware and the performance impact is
1383 minimal. If unsure, say Y.
1386 bool "Enable support for Privileged Access Never (PAN)"
1389 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1390 prevents the kernel or hypervisor from accessing user-space (EL0)
1393 Choosing this option will cause any unprotected (not using
1394 copy_to_user et al) memory access to fail with a permission fault.
1396 The feature is detected at runtime, and will remain as a 'nop'
1397 instruction if the cpu does not implement the feature.
1400 def_bool $(as-instr,.arch_extension rcpc)
1402 config AS_HAS_LSE_ATOMICS
1403 def_bool $(as-instr,.arch_extension lse)
1405 config ARM64_LSE_ATOMICS
1407 default ARM64_USE_LSE_ATOMICS
1408 depends on AS_HAS_LSE_ATOMICS
1410 config ARM64_USE_LSE_ATOMICS
1411 bool "Atomic instructions"
1412 depends on JUMP_LABEL
1415 As part of the Large System Extensions, ARMv8.1 introduces new
1416 atomic instructions that are designed specifically to scale in
1419 Say Y here to make use of these instructions for the in-kernel
1420 atomic routines. This incurs a small overhead on CPUs that do
1421 not support these instructions and requires the kernel to be
1422 built with binutils >= 2.25 in order for the new instructions
1427 menu "ARMv8.2 architectural features"
1430 bool "Enable support for persistent memory"
1431 select ARCH_HAS_PMEM_API
1432 select ARCH_HAS_UACCESS_FLUSHCACHE
1434 Say Y to enable support for the persistent memory API based on the
1435 ARMv8.2 DCPoP feature.
1437 The feature is detected at runtime, and the kernel will use DC CVAC
1438 operations if DC CVAP is not supported (following the behaviour of
1439 DC CVAP itself if the system does not define a point of persistence).
1441 config ARM64_RAS_EXTN
1442 bool "Enable support for RAS CPU Extensions"
1445 CPUs that support the Reliability, Availability and Serviceability
1446 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1447 errors, classify them and report them to software.
1449 On CPUs with these extensions system software can use additional
1450 barriers to determine if faults are pending and read the
1451 classification from a new set of registers.
1453 Selecting this feature will allow the kernel to use these barriers
1454 and access the new registers if the system supports the extension.
1455 Platform RAS features may additionally depend on firmware support.
1458 bool "Enable support for Common Not Private (CNP) translations"
1460 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1462 Common Not Private (CNP) allows translation table entries to
1463 be shared between different PEs in the same inner shareable
1464 domain, so the hardware can use this fact to optimise the
1465 caching of such entries in the TLB.
1467 Selecting this option allows the CNP feature to be detected
1468 at runtime, and does not affect PEs that do not implement
1473 menu "ARMv8.3 architectural features"
1475 config ARM64_PTR_AUTH
1476 bool "Enable support for pointer authentication"
1479 Pointer authentication (part of the ARMv8.3 Extensions) provides
1480 instructions for signing and authenticating pointers against secret
1481 keys, which can be used to mitigate Return Oriented Programming (ROP)
1484 This option enables these instructions at EL0 (i.e. for userspace).
1485 Choosing this option will cause the kernel to initialise secret keys
1486 for each process at exec() time, with these keys being
1487 context-switched along with the process.
1489 The feature is detected at runtime. If the feature is not present in
1490 hardware it will not be advertised to userspace/KVM guest nor will it
1493 If the feature is present on the boot CPU but not on a late CPU, then
1494 the late CPU will be parked. Also, if the boot CPU does not have
1495 address auth and the late CPU has then the late CPU will still boot
1496 but with the feature disabled. On such a system, this option should
1499 config ARM64_PTR_AUTH_KERNEL
1500 bool "Use pointer authentication for kernel"
1502 depends on ARM64_PTR_AUTH
1503 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1504 # Modern compilers insert a .note.gnu.property section note for PAC
1505 # which is only understood by binutils starting with version 2.33.1.
1506 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1507 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1508 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1510 If the compiler supports the -mbranch-protection or
1511 -msign-return-address flag (e.g. GCC 7 or later), then this option
1512 will cause the kernel itself to be compiled with return address
1513 protection. In this case, and if the target hardware is known to
1514 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1515 disabled with minimal loss of protection.
1517 This feature works with FUNCTION_GRAPH_TRACER option only if
1518 DYNAMIC_FTRACE_WITH_REGS is enabled.
1520 config CC_HAS_BRANCH_PROT_PAC_RET
1521 # GCC 9 or later, clang 8 or later
1522 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1524 config CC_HAS_SIGN_RETURN_ADDRESS
1526 def_bool $(cc-option,-msign-return-address=all)
1529 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1531 config AS_HAS_CFI_NEGATE_RA_STATE
1532 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1536 menu "ARMv8.4 architectural features"
1538 config ARM64_AMU_EXTN
1539 bool "Enable support for the Activity Monitors Unit CPU extension"
1542 The activity monitors extension is an optional extension introduced
1543 by the ARMv8.4 CPU architecture. This enables support for version 1
1544 of the activity monitors architecture, AMUv1.
1546 To enable the use of this extension on CPUs that implement it, say Y.
1548 Note that for architectural reasons, firmware _must_ implement AMU
1549 support when running on CPUs that present the activity monitors
1550 extension. The required support is present in:
1551 * Version 1.5 and later of the ARM Trusted Firmware
1553 For kernels that have this configuration enabled but boot with broken
1554 firmware, you may need to say N here until the firmware is fixed.
1555 Otherwise you may experience firmware panics or lockups when
1556 accessing the counter registers. Even if you are not observing these
1557 symptoms, the values returned by the register reads might not
1558 correctly reflect reality. Most commonly, the value read will be 0,
1559 indicating that the counter is not enabled.
1561 config AS_HAS_ARMV8_4
1562 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1564 config ARM64_TLB_RANGE
1565 bool "Enable support for tlbi range feature"
1567 depends on AS_HAS_ARMV8_4
1569 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1570 range of input addresses.
1572 The feature introduces new assembly instructions, and they were
1573 support when binutils >= 2.30.
1577 menu "ARMv8.5 architectural features"
1579 config AS_HAS_ARMV8_5
1580 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1583 bool "Branch Target Identification support"
1586 Branch Target Identification (part of the ARMv8.5 Extensions)
1587 provides a mechanism to limit the set of locations to which computed
1588 branch instructions such as BR or BLR can jump.
1590 To make use of BTI on CPUs that support it, say Y.
1592 BTI is intended to provide complementary protection to other control
1593 flow integrity protection mechanisms, such as the Pointer
1594 authentication mechanism provided as part of the ARMv8.3 Extensions.
1595 For this reason, it does not make sense to enable this option without
1596 also enabling support for pointer authentication. Thus, when
1597 enabling this option you should also select ARM64_PTR_AUTH=y.
1599 Userspace binaries must also be specifically compiled to make use of
1600 this mechanism. If you say N here or the hardware does not support
1601 BTI, such binaries can still run, but you get no additional
1602 enforcement of branch destinations.
1604 config ARM64_BTI_KERNEL
1605 bool "Use Branch Target Identification for kernel"
1607 depends on ARM64_BTI
1608 depends on ARM64_PTR_AUTH_KERNEL
1609 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1610 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1611 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1612 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1613 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1614 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1616 Build the kernel with Branch Target Identification annotations
1617 and enable enforcement of this for kernel code. When this option
1618 is enabled and the system supports BTI all kernel code including
1619 modular code must have BTI enabled.
1621 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1622 # GCC 9 or later, clang 8 or later
1623 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1626 bool "Enable support for E0PD"
1629 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1630 that EL0 accesses made via TTBR1 always fault in constant time,
1631 providing similar benefits to KASLR as those provided by KPTI, but
1632 with lower overhead and without disrupting legitimate access to
1633 kernel memory such as SPE.
1635 This option enables E0PD for TTBR1 where available.
1638 bool "Enable support for random number generation"
1641 Random number generation (part of the ARMv8.5 Extensions)
1642 provides a high bandwidth, cryptographically secure
1643 hardware random number generator.
1645 config ARM64_AS_HAS_MTE
1646 # Initial support for MTE went in binutils 2.32.0, checked with
1647 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1648 # as a late addition to the final architecture spec (LDGM/STGM)
1649 # is only supported in the newer 2.32.x and 2.33 binutils
1650 # versions, hence the extra "stgm" instruction check below.
1651 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1654 bool "Memory Tagging Extension support"
1656 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1657 depends on AS_HAS_ARMV8_5
1658 depends on AS_HAS_LSE_ATOMICS
1659 # Required for tag checking in the uaccess routines
1660 depends on ARM64_PAN
1661 select ARCH_USES_HIGH_VMA_FLAGS
1663 Memory Tagging (part of the ARMv8.5 Extensions) provides
1664 architectural support for run-time, always-on detection of
1665 various classes of memory error to aid with software debugging
1666 to eliminate vulnerabilities arising from memory-unsafe
1669 This option enables the support for the Memory Tagging
1670 Extension at EL0 (i.e. for userspace).
1672 Selecting this option allows the feature to be detected at
1673 runtime. Any secondary CPU not implementing this feature will
1674 not be allowed a late bring-up.
1676 Userspace binaries that want to use this feature must
1677 explicitly opt in. The mechanism for the userspace is
1680 Documentation/arm64/memory-tagging-extension.rst.
1684 menu "ARMv8.7 architectural features"
1687 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1689 depends on ARM64_PAN
1691 Enhanced Privileged Access Never (EPAN) allows Privileged
1692 Access Never to be used with Execute-only mappings.
1694 The feature is detected at runtime, and will remain disabled
1695 if the cpu does not implement the feature.
1699 bool "ARM Scalable Vector Extension support"
1702 The Scalable Vector Extension (SVE) is an extension to the AArch64
1703 execution state which complements and extends the SIMD functionality
1704 of the base architecture to support much larger vectors and to enable
1705 additional vectorisation opportunities.
1707 To enable use of this extension on CPUs that implement it, say Y.
1709 On CPUs that support the SVE2 extensions, this option will enable
1712 Note that for architectural reasons, firmware _must_ implement SVE
1713 support when running on SVE capable hardware. The required support
1716 * version 1.5 and later of the ARM Trusted Firmware
1717 * the AArch64 boot wrapper since commit 5e1261e08abf
1718 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1720 For other firmware implementations, consult the firmware documentation
1723 If you need the kernel to boot on SVE-capable hardware with broken
1724 firmware, you may need to say N here until you get your firmware
1725 fixed. Otherwise, you may experience firmware panics or lockups when
1726 booting the kernel. If unsure and you are not observing these
1727 symptoms, you should assume that it is safe to say Y.
1729 config ARM64_MODULE_PLTS
1730 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1732 select HAVE_MOD_ARCH_SPECIFIC
1734 Allocate PLTs when loading modules so that jumps and calls whose
1735 targets are too far away for their relative offsets to be encoded
1736 in the instructions themselves can be bounced via veneers in the
1737 module's PLT. This allows modules to be allocated in the generic
1738 vmalloc area after the dedicated module memory area has been
1741 When running with address space randomization (KASLR), the module
1742 region itself may be too far away for ordinary relative jumps and
1743 calls, and so in that case, module PLTs are required and cannot be
1746 Specific errata workaround(s) might also force module PLTs to be
1747 enabled (ARM64_ERRATUM_843419).
1749 config ARM64_PSEUDO_NMI
1750 bool "Support for NMI-like interrupts"
1753 Adds support for mimicking Non-Maskable Interrupts through the use of
1754 GIC interrupt priority. This support requires version 3 or later of
1757 This high priority configuration for interrupts needs to be
1758 explicitly enabled by setting the kernel parameter
1759 "irqchip.gicv3_pseudo_nmi" to 1.
1764 config ARM64_DEBUG_PRIORITY_MASKING
1765 bool "Debug interrupt priority masking"
1767 This adds runtime checks to functions enabling/disabling
1768 interrupts when using priority masking. The additional checks verify
1769 the validity of ICC_PMR_EL1 when calling concerned functions.
1775 bool "Build a relocatable kernel image" if EXPERT
1776 select ARCH_HAS_RELR
1779 This builds the kernel as a Position Independent Executable (PIE),
1780 which retains all relocation metadata required to relocate the
1781 kernel binary at runtime to a different virtual address than the
1782 address it was linked at.
1783 Since AArch64 uses the RELA relocation format, this requires a
1784 relocation pass at runtime even if the kernel is loaded at the
1785 same address it was linked at.
1787 config RANDOMIZE_BASE
1788 bool "Randomize the address of the kernel image"
1789 select ARM64_MODULE_PLTS if MODULES
1792 Randomizes the virtual address at which the kernel image is
1793 loaded, as a security feature that deters exploit attempts
1794 relying on knowledge of the location of kernel internals.
1796 It is the bootloader's job to provide entropy, by passing a
1797 random u64 value in /chosen/kaslr-seed at kernel entry.
1799 When booting via the UEFI stub, it will invoke the firmware's
1800 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1801 to the kernel proper. In addition, it will randomise the physical
1802 location of the kernel Image as well.
1806 config RANDOMIZE_MODULE_REGION_FULL
1807 bool "Randomize the module region over a 2 GB range"
1808 depends on RANDOMIZE_BASE
1811 Randomizes the location of the module region inside a 2 GB window
1812 covering the core kernel. This way, it is less likely for modules
1813 to leak information about the location of core kernel data structures
1814 but it does imply that function calls between modules and the core
1815 kernel will need to be resolved via veneers in the module PLT.
1817 When this option is not set, the module region will be randomized over
1818 a limited range that contains the [_stext, _etext] interval of the
1819 core kernel, so branch relocations are almost always in range unless
1820 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1821 particular case of region exhaustion, modules might be able to fall
1822 back to a larger 2GB area.
1824 config CC_HAVE_STACKPROTECTOR_SYSREG
1825 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1827 config STACKPROTECTOR_PER_TASK
1829 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1835 config ARM64_ACPI_PARKING_PROTOCOL
1836 bool "Enable support for the ARM64 ACPI parking protocol"
1839 Enable support for the ARM64 ACPI parking protocol. If disabled
1840 the kernel will not allow booting through the ARM64 ACPI parking
1841 protocol even if the corresponding data is present in the ACPI
1845 string "Default kernel command string"
1848 Provide a set of default command-line options at build time by
1849 entering them here. As a minimum, you should specify the the
1850 root device (e.g. root=/dev/nfs).
1853 prompt "Kernel command line type" if CMDLINE != ""
1854 default CMDLINE_FROM_BOOTLOADER
1856 Choose how the kernel will handle the provided default kernel
1857 command line string.
1859 config CMDLINE_FROM_BOOTLOADER
1860 bool "Use bootloader kernel arguments if available"
1862 Uses the command-line options passed by the boot loader. If
1863 the boot loader doesn't provide any, the default kernel command
1864 string provided in CMDLINE will be used.
1866 config CMDLINE_FORCE
1867 bool "Always use the default kernel command string"
1869 Always use the default kernel command string, even if the boot
1870 loader passes other arguments to the kernel.
1871 This is useful if you cannot or don't want to change the
1872 command-line options your boot loader passes to the kernel.
1880 bool "UEFI runtime support"
1881 depends on OF && !CPU_BIG_ENDIAN
1882 depends on KERNEL_MODE_NEON
1883 select ARCH_SUPPORTS_ACPI
1886 select EFI_PARAMS_FROM_FDT
1887 select EFI_RUNTIME_WRAPPERS
1889 select EFI_GENERIC_STUB
1890 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1893 This option provides support for runtime services provided
1894 by UEFI firmware (such as non-volatile variables, realtime
1895 clock, and platform reset). A UEFI stub is also provided to
1896 allow the kernel to be booted as an EFI application. This
1897 is only useful on systems that have UEFI firmware.
1900 bool "Enable support for SMBIOS (DMI) tables"
1904 This enables SMBIOS/DMI feature for systems.
1906 This option is only useful on systems that have UEFI firmware.
1907 However, even with this option, the resultant kernel should
1908 continue to boot on existing non-UEFI platforms.
1912 config SYSVIPC_COMPAT
1914 depends on COMPAT && SYSVIPC
1916 menu "Power management options"
1918 source "kernel/power/Kconfig"
1920 config ARCH_HIBERNATION_POSSIBLE
1924 config ARCH_HIBERNATION_HEADER
1926 depends on HIBERNATION
1928 config ARCH_SUSPEND_POSSIBLE
1933 menu "CPU Power Management"
1935 source "drivers/cpuidle/Kconfig"
1937 source "drivers/cpufreq/Kconfig"
1941 source "drivers/acpi/Kconfig"
1943 source "arch/arm64/kvm/Kconfig"
1946 source "arch/arm64/crypto/Kconfig"