3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
25 select ARCH_INLINE_READ_LOCK if !PREEMPT
26 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
27 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
28 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
29 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
30 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
31 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
32 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
33 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
34 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
35 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
37 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
38 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
39 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
41 select ARCH_USE_CMPXCHG_LOCKREF
42 select ARCH_USE_QUEUED_RWLOCKS
43 select ARCH_SUPPORTS_MEMORY_FAILURE
44 select ARCH_SUPPORTS_ATOMIC_RMW
45 select ARCH_SUPPORTS_NUMA_BALANCING
46 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
47 select ARCH_WANT_FRAME_POINTERS
48 select ARCH_HAS_UBSAN_SANITIZE_ALL
52 select AUDIT_ARCH_COMPAT_GENERIC
53 select ARM_GIC_V2M if PCI
55 select ARM_GIC_V3_ITS if PCI
57 select BUILDTIME_EXTABLE_SORT
58 select CLONE_BACKWARDS
60 select CPU_PM if (SUSPEND || CPU_IDLE)
61 select DCACHE_WORD_ACCESS
64 select GENERIC_ALLOCATOR
65 select GENERIC_ARCH_TOPOLOGY
66 select GENERIC_CLOCKEVENTS
67 select GENERIC_CLOCKEVENTS_BROADCAST
68 select GENERIC_CPU_AUTOPROBE
69 select GENERIC_EARLY_IOREMAP
70 select GENERIC_IDLE_POLL_SETUP
71 select GENERIC_IRQ_PROBE
72 select GENERIC_IRQ_SHOW
73 select GENERIC_IRQ_SHOW_LEVEL
74 select GENERIC_PCI_IOMAP
75 select GENERIC_SCHED_CLOCK
76 select GENERIC_SMP_IDLE_THREAD
77 select GENERIC_STRNCPY_FROM_USER
78 select GENERIC_STRNLEN_USER
79 select GENERIC_TIME_VSYSCALL
80 select HANDLE_DOMAIN_IRQ
81 select HARDIRQS_SW_RESEND
82 select HAVE_ACPI_APEI if (ACPI && EFI)
83 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
84 select HAVE_ARCH_AUDITSYSCALL
85 select HAVE_ARCH_BITREVERSE
86 select HAVE_ARCH_HUGE_VMAP
87 select HAVE_ARCH_JUMP_LABEL
88 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
90 select HAVE_ARCH_MMAP_RND_BITS
91 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
92 select HAVE_ARCH_SECCOMP_FILTER
93 select HAVE_ARCH_TRACEHOOK
94 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
97 select HAVE_C_RECORDMCOUNT
98 select HAVE_CC_STACKPROTECTOR
99 select HAVE_CMPXCHG_DOUBLE
100 select HAVE_CMPXCHG_LOCAL
101 select HAVE_CONTEXT_TRACKING
102 select HAVE_DEBUG_BUGVERBOSE
103 select HAVE_DEBUG_KMEMLEAK
104 select HAVE_DMA_API_DEBUG
105 select HAVE_DMA_CONTIGUOUS
106 select HAVE_DYNAMIC_FTRACE
107 select HAVE_EFFICIENT_UNALIGNED_ACCESS
108 select HAVE_FTRACE_MCOUNT_RECORD
109 select HAVE_FUNCTION_TRACER
110 select HAVE_FUNCTION_GRAPH_TRACER
111 select HAVE_GCC_PLUGINS
112 select HAVE_GENERIC_DMA_COHERENT
113 select HAVE_HW_BREAKPOINT if PERF_EVENTS
114 select HAVE_IRQ_TIME_ACCOUNTING
116 select HAVE_MEMBLOCK_NODE_MAP if NUMA
117 select HAVE_NMI if ACPI_APEI_SEA
118 select HAVE_PATA_PLATFORM
119 select HAVE_PERF_EVENTS
120 select HAVE_PERF_REGS
121 select HAVE_PERF_USER_STACK_DUMP
122 select HAVE_REGS_AND_STACK_ACCESS_API
123 select HAVE_RCU_TABLE_FREE
124 select HAVE_SYSCALL_TRACEPOINTS
126 select HAVE_KRETPROBES
127 select IOMMU_DMA if IOMMU_SUPPORT
129 select IRQ_FORCED_THREADING
130 select MODULES_USE_ELF_RELA
133 select OF_EARLY_FLATTREE
134 select OF_RESERVED_MEM
135 select PCI_ECAM if ACPI
139 select SYSCTL_EXCEPTION_TRACE
140 select THREAD_INFO_IN_TASK
142 ARM 64-bit (AArch64) Linux support.
147 config ARCH_PHYS_ADDR_T_64BIT
153 config ARM64_PAGE_SHIFT
155 default 16 if ARM64_64K_PAGES
156 default 14 if ARM64_16K_PAGES
159 config ARM64_CONT_SHIFT
161 default 5 if ARM64_64K_PAGES
162 default 7 if ARM64_16K_PAGES
165 config ARCH_MMAP_RND_BITS_MIN
166 default 14 if ARM64_64K_PAGES
167 default 16 if ARM64_16K_PAGES
170 # max bits determined by the following formula:
171 # VA_BITS - PAGE_SHIFT - 3
172 config ARCH_MMAP_RND_BITS_MAX
173 default 19 if ARM64_VA_BITS=36
174 default 24 if ARM64_VA_BITS=39
175 default 27 if ARM64_VA_BITS=42
176 default 30 if ARM64_VA_BITS=47
177 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
178 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
179 default 33 if ARM64_VA_BITS=48
180 default 14 if ARM64_64K_PAGES
181 default 16 if ARM64_16K_PAGES
184 config ARCH_MMAP_RND_COMPAT_BITS_MIN
185 default 7 if ARM64_64K_PAGES
186 default 9 if ARM64_16K_PAGES
189 config ARCH_MMAP_RND_COMPAT_BITS_MAX
195 config STACKTRACE_SUPPORT
198 config ILLEGAL_POINTER_VALUE
200 default 0xdead000000000000
202 config LOCKDEP_SUPPORT
205 config TRACE_IRQFLAGS_SUPPORT
208 config RWSEM_XCHGADD_ALGORITHM
215 config GENERIC_BUG_RELATIVE_POINTERS
217 depends on GENERIC_BUG
219 config GENERIC_HWEIGHT
225 config GENERIC_CALIBRATE_DELAY
231 config HAVE_GENERIC_GUP
234 config ARCH_DMA_ADDR_T_64BIT
237 config NEED_DMA_MAP_STATE
240 config NEED_SG_DMA_LENGTH
252 config KERNEL_MODE_NEON
255 config FIX_EARLYCON_MEM
258 config PGTABLE_LEVELS
260 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
261 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
262 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
263 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
264 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
265 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
267 config ARCH_SUPPORTS_UPROBES
270 config ARCH_PROC_KCORE_TEXT
273 source "init/Kconfig"
275 source "kernel/Kconfig.freezer"
277 source "arch/arm64/Kconfig.platforms"
284 This feature enables support for PCI bus system. If you say Y
285 here, the kernel will include drivers and infrastructure code
286 to support PCI bus devices.
291 config PCI_DOMAINS_GENERIC
297 source "drivers/pci/Kconfig"
301 menu "Kernel Features"
303 menu "ARM errata workarounds via the alternatives framework"
305 config ARM64_ERRATUM_826319
306 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
309 This option adds an alternative code sequence to work around ARM
310 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
311 AXI master interface and an L2 cache.
313 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
314 and is unable to accept a certain write via this interface, it will
315 not progress on read data presented on the read data channel and the
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this does not necessarily enable the workaround,
321 as it depends on the alternative framework, which will only patch
322 the kernel if an affected CPU is detected.
326 config ARM64_ERRATUM_827319
327 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
330 This option adds an alternative code sequence to work around ARM
331 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
332 master interface and an L2 cache.
334 Under certain conditions this erratum can cause a clean line eviction
335 to occur at the same time as another transaction to the same address
336 on the AMBA 5 CHI interface, which can cause data corruption if the
337 interconnect reorders the two transactions.
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_824069
348 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
351 This option adds an alternative code sequence to work around ARM
352 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
353 to a coherent interconnect.
355 If a Cortex-A53 processor is executing a store or prefetch for
356 write instruction at the same time as a processor in another
357 cluster is executing a cache maintenance operation to the same
358 address, then this erratum might cause a clean cache line to be
359 incorrectly marked as dirty.
361 The workaround promotes data cache clean instructions to
362 data cache clean-and-invalidate.
363 Please note that this option does not necessarily enable the
364 workaround, as it depends on the alternative framework, which will
365 only patch the kernel if an affected CPU is detected.
369 config ARM64_ERRATUM_819472
370 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
373 This option adds an alternative code sequence to work around ARM
374 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
375 present when it is connected to a coherent interconnect.
377 If the processor is executing a load and store exclusive sequence at
378 the same time as a processor in another cluster is executing a cache
379 maintenance operation to the same address, then this erratum might
380 cause data corruption.
382 The workaround promotes data cache clean instructions to
383 data cache clean-and-invalidate.
384 Please note that this does not necessarily enable the workaround,
385 as it depends on the alternative framework, which will only patch
386 the kernel if an affected CPU is detected.
390 config ARM64_ERRATUM_832075
391 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
394 This option adds an alternative code sequence to work around ARM
395 erratum 832075 on Cortex-A57 parts up to r1p2.
397 Affected Cortex-A57 parts might deadlock when exclusive load/store
398 instructions to Write-Back memory are mixed with Device loads.
400 The workaround is to promote device loads to use Load-Acquire
402 Please note that this does not necessarily enable the workaround,
403 as it depends on the alternative framework, which will only patch
404 the kernel if an affected CPU is detected.
408 config ARM64_ERRATUM_834220
409 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
413 This option adds an alternative code sequence to work around ARM
414 erratum 834220 on Cortex-A57 parts up to r1p2.
416 Affected Cortex-A57 parts might report a Stage 2 translation
417 fault as the result of a Stage 1 fault for load crossing a
418 page boundary when there is a permission or device memory
419 alignment fault at Stage 1 and a translation fault at Stage 2.
421 The workaround is to verify that the Stage 1 translation
422 doesn't generate a fault before handling the Stage 2 fault.
423 Please note that this does not necessarily enable the workaround,
424 as it depends on the alternative framework, which will only patch
425 the kernel if an affected CPU is detected.
429 config ARM64_ERRATUM_845719
430 bool "Cortex-A53: 845719: a load might read incorrect data"
434 This option adds an alternative code sequence to work around ARM
435 erratum 845719 on Cortex-A53 parts up to r0p4.
437 When running a compat (AArch32) userspace on an affected Cortex-A53
438 part, a load at EL0 from a virtual address that matches the bottom 32
439 bits of the virtual address used by a recent load at (AArch64) EL1
440 might return incorrect data.
442 The workaround is to write the contextidr_el1 register on exception
443 return to a 32-bit task.
444 Please note that this does not necessarily enable the workaround,
445 as it depends on the alternative framework, which will only patch
446 the kernel if an affected CPU is detected.
450 config ARM64_ERRATUM_843419
451 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
453 select ARM64_MODULE_CMODEL_LARGE if MODULES
455 This option links the kernel with '--fix-cortex-a53-843419' and
456 builds modules using the large memory model in order to avoid the use
457 of the ADRP instruction, which can cause a subsequent memory access
458 to use an incorrect address on Cortex-A53 parts up to r0p4.
462 config CAVIUM_ERRATUM_22375
463 bool "Cavium erratum 22375, 24313"
466 Enable workaround for erratum 22375, 24313.
468 This implements two gicv3-its errata workarounds for ThunderX. Both
469 with small impact affecting only ITS table allocation.
471 erratum 22375: only alloc 8MB table size
472 erratum 24313: ignore memory access type
474 The fixes are in ITS initialization and basically ignore memory access
475 type and table size provided by the TYPER and BASER registers.
479 config CAVIUM_ERRATUM_23144
480 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
484 ITS SYNC command hang for cross node io and collections/cpu mapping.
488 config CAVIUM_ERRATUM_23154
489 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
492 The gicv3 of ThunderX requires a modified version for
493 reading the IAR status to ensure data synchronization
494 (access to icc_iar1_el1 is not sync'ed before and after).
498 config CAVIUM_ERRATUM_27456
499 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
502 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
503 instructions may cause the icache to become corrupted if it
504 contains data for a non-current ASID. The fix is to
505 invalidate the icache when changing the mm context.
509 config CAVIUM_ERRATUM_30115
510 bool "Cavium erratum 30115: Guest may disable interrupts in host"
513 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
514 1.2, and T83 Pass 1.0, KVM guest execution may disable
515 interrupts in host. Trapping both GICv3 group-0 and group-1
516 accesses sidesteps the issue.
520 config QCOM_FALKOR_ERRATUM_1003
521 bool "Falkor E1003: Incorrect translation due to ASID change"
523 select ARM64_PAN if ARM64_SW_TTBR0_PAN
525 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
526 and BADDR are changed together in TTBRx_EL1. The workaround for this
527 issue is to use a reserved ASID in cpu_do_switch_mm() before
528 switching to the new ASID. Saying Y here selects ARM64_PAN if
529 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
530 maintaining the E1003 workaround in the software PAN emulation code
531 would be an unnecessary complication. The affected Falkor v1 CPU
532 implements ARMv8.1 hardware PAN support and using hardware PAN
533 support versus software PAN emulation is mutually exclusive at
538 config QCOM_FALKOR_ERRATUM_1009
539 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
542 On Falkor v1, the CPU may prematurely complete a DSB following a
543 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
544 one more time to fix the issue.
548 config QCOM_QDF2400_ERRATUM_0065
549 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
552 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
553 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
554 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
558 config QCOM_FALKOR_ERRATUM_E1041
559 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
562 Falkor CPU may speculatively fetch instructions from an improper
563 memory location when MMU translation is changed from SCTLR_ELn[M]=1
564 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
573 default ARM64_4K_PAGES
575 Page size (translation granule) configuration.
577 config ARM64_4K_PAGES
580 This feature enables 4KB pages support.
582 config ARM64_16K_PAGES
585 The system will use 16KB pages support. AArch32 emulation
586 requires applications compiled with 16K (or a multiple of 16K)
589 config ARM64_64K_PAGES
592 This feature enables 64KB pages support (4KB by default)
593 allowing only two levels of page tables and faster TLB
594 look-up. AArch32 emulation requires applications compiled
595 with 64K aligned segments.
600 prompt "Virtual address space size"
601 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
602 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
603 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
605 Allows choosing one of multiple possible virtual address
606 space sizes. The level of translation table is determined by
607 a combination of page size and virtual address space size.
609 config ARM64_VA_BITS_36
610 bool "36-bit" if EXPERT
611 depends on ARM64_16K_PAGES
613 config ARM64_VA_BITS_39
615 depends on ARM64_4K_PAGES
617 config ARM64_VA_BITS_42
619 depends on ARM64_64K_PAGES
621 config ARM64_VA_BITS_47
623 depends on ARM64_16K_PAGES
625 config ARM64_VA_BITS_48
632 default 36 if ARM64_VA_BITS_36
633 default 39 if ARM64_VA_BITS_39
634 default 42 if ARM64_VA_BITS_42
635 default 47 if ARM64_VA_BITS_47
636 default 48 if ARM64_VA_BITS_48
638 config CPU_BIG_ENDIAN
639 bool "Build big-endian kernel"
641 Say Y if you plan on running a kernel in big-endian mode.
644 bool "Multi-core scheduler support"
646 Multi-core scheduler support improves the CPU scheduler's decision
647 making when dealing with multi-core CPU chips at a cost of slightly
648 increased overhead in some places. If unsure say N here.
651 bool "SMT scheduler support"
653 Improves the CPU scheduler's decision making when dealing with
654 MultiThreading at a cost of slightly increased overhead in some
655 places. If unsure say N here.
658 int "Maximum number of CPUs (2-4096)"
660 # These have to remain sorted largest to smallest
664 bool "Support for hot-pluggable CPUs"
665 select GENERIC_IRQ_MIGRATION
667 Say Y here to experiment with turning CPUs off and on. CPUs
668 can be controlled through /sys/devices/system/cpu.
670 # Common NUMA Features
672 bool "Numa Memory Allocation and Scheduler Support"
673 select ACPI_NUMA if ACPI
676 Enable NUMA (Non Uniform Memory Access) support.
678 The kernel will try to allocate memory used by a CPU on the
679 local memory of the CPU and add some more
680 NUMA awareness to the kernel.
683 int "Maximum NUMA Nodes (as a power of 2)"
686 depends on NEED_MULTIPLE_NODES
688 Specify the maximum number of NUMA Nodes available on the target
689 system. Increases memory reserved to accommodate various tables.
691 config USE_PERCPU_NUMA_NODE_ID
695 config HAVE_SETUP_PER_CPU_AREA
699 config NEED_PER_CPU_EMBED_FIRST_CHUNK
707 source kernel/Kconfig.preempt
708 source kernel/Kconfig.hz
710 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
713 config ARCH_HAS_HOLES_MEMORYMODEL
714 def_bool y if SPARSEMEM
716 config ARCH_SPARSEMEM_ENABLE
718 select SPARSEMEM_VMEMMAP_ENABLE
720 config ARCH_SPARSEMEM_DEFAULT
721 def_bool ARCH_SPARSEMEM_ENABLE
723 config ARCH_SELECT_MEMORY_MODEL
724 def_bool ARCH_SPARSEMEM_ENABLE
726 config HAVE_ARCH_PFN_VALID
727 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
729 config HW_PERF_EVENTS
733 config SYS_SUPPORTS_HUGETLBFS
736 config ARCH_WANT_HUGE_PMD_SHARE
737 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
739 config ARCH_HAS_CACHE_LINE_SIZE
745 bool "Enable seccomp to safely compute untrusted bytecode"
747 This kernel feature is useful for number crunching applications
748 that may need to compute untrusted bytecode during their
749 execution. By using pipes or other transports made available to
750 the process as file descriptors supporting the read/write
751 syscalls, it's possible to isolate those applications in
752 their own address space using seccomp. Once seccomp is
753 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
754 and the task is only allowed to execute a few safe syscalls
755 defined by each seccomp mode.
758 bool "Enable paravirtualization code"
760 This changes the kernel so it can modify itself when it is run
761 under a hypervisor, potentially improving performance significantly
762 over full virtualization.
764 config PARAVIRT_TIME_ACCOUNTING
765 bool "Paravirtual steal time accounting"
769 Select this option to enable fine granularity task steal time
770 accounting. Time spent executing other tasks in parallel with
771 the current vCPU is discounted from the vCPU power. To account for
772 that, there can be a small performance impact.
774 If in doubt, say N here.
777 depends on PM_SLEEP_SMP
779 bool "kexec system call"
781 kexec is a system call that implements the ability to shutdown your
782 current kernel, and to start another kernel. It is like a reboot
783 but it is independent of the system firmware. And like a reboot
784 you can start any kernel with it, not just Linux.
787 bool "Build kdump crash kernel"
789 Generate crash dump after being started by kexec. This should
790 be normally only set in special crash dump kernels which are
791 loaded in the main kernel with kexec-tools into a specially
792 reserved region and then later executed after a crash by
795 For more details see Documentation/kdump/kdump.txt
802 bool "Xen guest support on ARM64"
803 depends on ARM64 && OF
807 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
809 config FORCE_MAX_ZONEORDER
811 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
812 default "13" if (ARCH_THUNDER && ARM64_4K_PAGES)
813 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
816 The kernel memory allocator divides physically contiguous memory
817 blocks into "zones", where each zone is a power of two number of
818 pages. This option selects the largest power of two that the kernel
819 keeps in the memory allocator. If you need to allocate very large
820 blocks of physically contiguous memory, then you may need to
823 This config option is actually maximum order plus one. For example,
824 a value of 11 means that the largest free memory block is 2^10 pages.
826 We make sure that we can allocate upto a HugePage size for each configuration.
828 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
830 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
831 4M allocations matching the default size used by generic code.
833 menuconfig ARMV8_DEPRECATED
834 bool "Emulate deprecated/obsolete ARMv8 instructions"
837 Legacy software support may require certain instructions
838 that have been deprecated or obsoleted in the architecture.
840 Enable this config to enable selective emulation of these
848 bool "Emulate SWP/SWPB instructions"
850 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
851 they are always undefined. Say Y here to enable software
852 emulation of these instructions for userspace using LDXR/STXR.
854 In some older versions of glibc [<=2.8] SWP is used during futex
855 trylock() operations with the assumption that the code will not
856 be preempted. This invalid assumption may be more likely to fail
857 with SWP emulation enabled, leading to deadlock of the user
860 NOTE: when accessing uncached shared regions, LDXR/STXR rely
861 on an external transaction monitoring block called a global
862 monitor to maintain update atomicity. If your system does not
863 implement a global monitor, this option can cause programs that
864 perform SWP operations to uncached memory to deadlock.
868 config CP15_BARRIER_EMULATION
869 bool "Emulate CP15 Barrier instructions"
871 The CP15 barrier instructions - CP15ISB, CP15DSB, and
872 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
873 strongly recommended to use the ISB, DSB, and DMB
874 instructions instead.
876 Say Y here to enable software emulation of these
877 instructions for AArch32 userspace code. When this option is
878 enabled, CP15 barrier usage is traced which can help
879 identify software that needs updating.
883 config SETEND_EMULATION
884 bool "Emulate SETEND instruction"
886 The SETEND instruction alters the data-endianness of the
887 AArch32 EL0, and is deprecated in ARMv8.
889 Say Y here to enable software emulation of the instruction
890 for AArch32 userspace code.
892 Note: All the cpus on the system must have mixed endian support at EL0
893 for this feature to be enabled. If a new CPU - which doesn't support mixed
894 endian - is hotplugged in after this feature has been enabled, there could
895 be unexpected results in the applications.
900 config ARM64_SW_TTBR0_PAN
901 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
903 Enabling this option prevents the kernel from accessing
904 user-space memory directly by pointing TTBR0_EL1 to a reserved
905 zeroed area and reserved ASID. The user access routines
906 restore the valid TTBR0_EL1 temporarily.
908 menu "ARMv8.1 architectural features"
910 config ARM64_HW_AFDBM
911 bool "Support for hardware updates of the Access and Dirty page flags"
914 The ARMv8.1 architecture extensions introduce support for
915 hardware updates of the access and dirty information in page
916 table entries. When enabled in TCR_EL1 (HA and HD bits) on
917 capable processors, accesses to pages with PTE_AF cleared will
918 set this bit instead of raising an access flag fault.
919 Similarly, writes to read-only pages with the DBM bit set will
920 clear the read-only bit (AP[2]) instead of raising a
923 Kernels built with this configuration option enabled continue
924 to work on pre-ARMv8.1 hardware and the performance impact is
925 minimal. If unsure, say Y.
928 bool "Enable support for Privileged Access Never (PAN)"
931 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
932 prevents the kernel or hypervisor from accessing user-space (EL0)
935 Choosing this option will cause any unprotected (not using
936 copy_to_user et al) memory access to fail with a permission fault.
938 The feature is detected at runtime, and will remain as a 'nop'
939 instruction if the cpu does not implement the feature.
941 config ARM64_LSE_ATOMICS
942 bool "Atomic instructions"
944 As part of the Large System Extensions, ARMv8.1 introduces new
945 atomic instructions that are designed specifically to scale in
948 Say Y here to make use of these instructions for the in-kernel
949 atomic routines. This incurs a small overhead on CPUs that do
950 not support these instructions and requires the kernel to be
951 built with binutils >= 2.25.
954 bool "Enable support for Virtualization Host Extensions (VHE)"
957 Virtualization Host Extensions (VHE) allow the kernel to run
958 directly at EL2 (instead of EL1) on processors that support
959 it. This leads to better performance for KVM, as they reduce
960 the cost of the world switch.
962 Selecting this option allows the VHE feature to be detected
963 at runtime, and does not affect processors that do not
964 implement this feature.
968 menu "ARMv8.2 architectural features"
971 bool "Enable support for User Access Override (UAO)"
974 User Access Override (UAO; part of the ARMv8.2 Extensions)
975 causes the 'unprivileged' variant of the load/store instructions to
976 be overriden to be privileged.
978 This option changes get_user() and friends to use the 'unprivileged'
979 variant of the load/store instructions. This ensures that user-space
980 really did have access to the supplied memory. When addr_limit is
981 set to kernel memory the UAO bit will be set, allowing privileged
982 access to kernel memory.
984 Choosing this option will cause copy_to_user() et al to use user-space
987 The feature is detected at runtime, the kernel will use the
988 regular load/store instructions if the cpu does not implement the
993 config ARM64_MODULE_CMODEL_LARGE
996 config ARM64_MODULE_PLTS
998 select ARM64_MODULE_CMODEL_LARGE
999 select HAVE_MOD_ARCH_SPECIFIC
1004 This builds the kernel as a Position Independent Executable (PIE),
1005 which retains all relocation metadata required to relocate the
1006 kernel binary at runtime to a different virtual address than the
1007 address it was linked at.
1008 Since AArch64 uses the RELA relocation format, this requires a
1009 relocation pass at runtime even if the kernel is loaded at the
1010 same address it was linked at.
1012 config RANDOMIZE_BASE
1013 bool "Randomize the address of the kernel image"
1014 select ARM64_MODULE_PLTS if MODULES
1017 Randomizes the virtual address at which the kernel image is
1018 loaded, as a security feature that deters exploit attempts
1019 relying on knowledge of the location of kernel internals.
1021 It is the bootloader's job to provide entropy, by passing a
1022 random u64 value in /chosen/kaslr-seed at kernel entry.
1024 When booting via the UEFI stub, it will invoke the firmware's
1025 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1026 to the kernel proper. In addition, it will randomise the physical
1027 location of the kernel Image as well.
1031 config RANDOMIZE_MODULE_REGION_FULL
1032 bool "Randomize the module region independently from the core kernel"
1033 depends on RANDOMIZE_BASE
1036 Randomizes the location of the module region without considering the
1037 location of the core kernel. This way, it is impossible for modules
1038 to leak information about the location of core kernel data structures
1039 but it does imply that function calls between modules and the core
1040 kernel will need to be resolved via veneers in the module PLT.
1042 When this option is not set, the module region will be randomized over
1043 a limited range that contains the [_stext, _etext] interval of the
1044 core kernel, so branch relocations are always in range.
1050 config ARM64_ACPI_PARKING_PROTOCOL
1051 bool "Enable support for the ARM64 ACPI parking protocol"
1054 Enable support for the ARM64 ACPI parking protocol. If disabled
1055 the kernel will not allow booting through the ARM64 ACPI parking
1056 protocol even if the corresponding data is present in the ACPI
1060 string "Default kernel command string"
1063 Provide a set of default command-line options at build time by
1064 entering them here. As a minimum, you should specify the the
1065 root device (e.g. root=/dev/nfs).
1067 config CMDLINE_FORCE
1068 bool "Always use the default kernel command string"
1070 Always use the default kernel command string, even if the boot
1071 loader passes other arguments to the kernel.
1072 This is useful if you cannot or don't want to change the
1073 command-line options your boot loader passes to the kernel.
1079 bool "UEFI runtime support"
1080 depends on OF && !CPU_BIG_ENDIAN
1083 select EFI_PARAMS_FROM_FDT
1084 select EFI_RUNTIME_WRAPPERS
1089 This option provides support for runtime services provided
1090 by UEFI firmware (such as non-volatile variables, realtime
1091 clock, and platform reset). A UEFI stub is also provided to
1092 allow the kernel to be booted as an EFI application. This
1093 is only useful on systems that have UEFI firmware.
1096 bool "Enable support for SMBIOS (DMI) tables"
1100 This enables SMBIOS/DMI feature for systems.
1102 This option is only useful on systems that have UEFI firmware.
1103 However, even with this option, the resultant kernel should
1104 continue to boot on existing non-UEFI platforms.
1108 menu "Userspace binary formats"
1110 source "fs/Kconfig.binfmt"
1113 bool "Kernel support for 32-bit EL0"
1114 depends on ARM64_4K_PAGES || EXPERT
1115 select COMPAT_BINFMT_ELF if BINFMT_ELF
1117 select OLD_SIGSUSPEND3
1118 select COMPAT_OLD_SIGACTION
1120 This option enables support for a 32-bit EL0 running under a 64-bit
1121 kernel at EL1. AArch32-specific components such as system calls,
1122 the user helper functions, VFP support and the ptrace interface are
1123 handled appropriately by the kernel.
1125 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1126 that you will only be able to execute AArch32 binaries that were compiled
1127 with page size aligned segments.
1129 If you want to execute 32-bit userspace applications, say Y.
1131 config SYSVIPC_COMPAT
1133 depends on COMPAT && SYSVIPC
1137 menu "Power management options"
1139 source "kernel/power/Kconfig"
1141 config ARCH_HIBERNATION_POSSIBLE
1145 config ARCH_HIBERNATION_HEADER
1147 depends on HIBERNATION
1149 config ARCH_SUSPEND_POSSIBLE
1154 menu "CPU Power Management"
1156 source "drivers/cpuidle/Kconfig"
1158 source "drivers/cpufreq/Kconfig"
1162 source "net/Kconfig"
1164 source "drivers/Kconfig"
1166 source "ubuntu/Kconfig"
1168 source "drivers/firmware/Kconfig"
1170 source "drivers/acpi/Kconfig"
1174 source "arch/arm64/kvm/Kconfig"
1176 source "arch/arm64/Kconfig.debug"
1178 source "security/Kconfig"
1180 source "crypto/Kconfig"
1182 source "arch/arm64/crypto/Kconfig"
1185 source "lib/Kconfig"