3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
25 select ARCH_USE_CMPXCHG_LOCKREF
26 select ARCH_SUPPORTS_MEMORY_FAILURE
27 select ARCH_SUPPORTS_ATOMIC_RMW
28 select ARCH_SUPPORTS_NUMA_BALANCING
29 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
30 select ARCH_WANT_FRAME_POINTERS
31 select ARCH_HAS_UBSAN_SANITIZE_ALL
35 select AUDIT_ARCH_COMPAT_GENERIC
36 select ARM_GIC_V2M if PCI
38 select ARM_GIC_V3_ITS if PCI
40 select BUILDTIME_EXTABLE_SORT
41 select CLONE_BACKWARDS
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select DCACHE_WORD_ACCESS
47 select GENERIC_ALLOCATOR
48 select GENERIC_ARCH_TOPOLOGY
49 select GENERIC_CLOCKEVENTS
50 select GENERIC_CLOCKEVENTS_BROADCAST
51 select GENERIC_CPU_AUTOPROBE
52 select GENERIC_EARLY_IOREMAP
53 select GENERIC_IDLE_POLL_SETUP
54 select GENERIC_IRQ_PROBE
55 select GENERIC_IRQ_SHOW
56 select GENERIC_IRQ_SHOW_LEVEL
57 select GENERIC_PCI_IOMAP
58 select GENERIC_SCHED_CLOCK
59 select GENERIC_SMP_IDLE_THREAD
60 select GENERIC_STRNCPY_FROM_USER
61 select GENERIC_STRNLEN_USER
62 select GENERIC_TIME_VSYSCALL
63 select HANDLE_DOMAIN_IRQ
64 select HARDIRQS_SW_RESEND
65 select HAVE_ACPI_APEI if (ACPI && EFI)
66 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
67 select HAVE_ARCH_AUDITSYSCALL
68 select HAVE_ARCH_BITREVERSE
69 select HAVE_ARCH_HUGE_VMAP
70 select HAVE_ARCH_JUMP_LABEL
71 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
73 select HAVE_ARCH_MMAP_RND_BITS
74 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
75 select HAVE_ARCH_SECCOMP_FILTER
76 select HAVE_ARCH_TRACEHOOK
77 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
80 select HAVE_C_RECORDMCOUNT
81 select HAVE_CC_STACKPROTECTOR
82 select HAVE_CMPXCHG_DOUBLE
83 select HAVE_CMPXCHG_LOCAL
84 select HAVE_CONTEXT_TRACKING
85 select HAVE_DEBUG_BUGVERBOSE
86 select HAVE_DEBUG_KMEMLEAK
87 select HAVE_DMA_API_DEBUG
88 select HAVE_DMA_CONTIGUOUS
89 select HAVE_DYNAMIC_FTRACE
90 select HAVE_EFFICIENT_UNALIGNED_ACCESS
91 select HAVE_FTRACE_MCOUNT_RECORD
92 select HAVE_FUNCTION_TRACER
93 select HAVE_FUNCTION_GRAPH_TRACER
94 select HAVE_GCC_PLUGINS
95 select HAVE_GENERIC_DMA_COHERENT
96 select HAVE_HW_BREAKPOINT if PERF_EVENTS
97 select HAVE_IRQ_TIME_ACCOUNTING
99 select HAVE_MEMBLOCK_NODE_MAP if NUMA
100 select HAVE_NMI if ACPI_APEI_SEA
101 select HAVE_PATA_PLATFORM
102 select HAVE_PERF_EVENTS
103 select HAVE_PERF_REGS
104 select HAVE_PERF_USER_STACK_DUMP
105 select HAVE_REGS_AND_STACK_ACCESS_API
106 select HAVE_RCU_TABLE_FREE
107 select HAVE_SYSCALL_TRACEPOINTS
109 select HAVE_KRETPROBES
110 select IOMMU_DMA if IOMMU_SUPPORT
112 select IRQ_FORCED_THREADING
113 select MODULES_USE_ELF_RELA
116 select OF_EARLY_FLATTREE
117 select OF_RESERVED_MEM
118 select PCI_ECAM if ACPI
122 select SYSCTL_EXCEPTION_TRACE
123 select THREAD_INFO_IN_TASK
125 ARM 64-bit (AArch64) Linux support.
130 config ARCH_PHYS_ADDR_T_64BIT
136 config ARM64_PAGE_SHIFT
138 default 16 if ARM64_64K_PAGES
139 default 14 if ARM64_16K_PAGES
142 config ARM64_CONT_SHIFT
144 default 5 if ARM64_64K_PAGES
145 default 7 if ARM64_16K_PAGES
148 config ARCH_MMAP_RND_BITS_MIN
149 default 14 if ARM64_64K_PAGES
150 default 16 if ARM64_16K_PAGES
153 # max bits determined by the following formula:
154 # VA_BITS - PAGE_SHIFT - 3
155 config ARCH_MMAP_RND_BITS_MAX
156 default 19 if ARM64_VA_BITS=36
157 default 24 if ARM64_VA_BITS=39
158 default 27 if ARM64_VA_BITS=42
159 default 30 if ARM64_VA_BITS=47
160 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
161 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
162 default 33 if ARM64_VA_BITS=48
163 default 14 if ARM64_64K_PAGES
164 default 16 if ARM64_16K_PAGES
167 config ARCH_MMAP_RND_COMPAT_BITS_MIN
168 default 7 if ARM64_64K_PAGES
169 default 9 if ARM64_16K_PAGES
172 config ARCH_MMAP_RND_COMPAT_BITS_MAX
178 config STACKTRACE_SUPPORT
181 config ILLEGAL_POINTER_VALUE
183 default 0xdead000000000000
185 config LOCKDEP_SUPPORT
188 config TRACE_IRQFLAGS_SUPPORT
191 config RWSEM_XCHGADD_ALGORITHM
198 config GENERIC_BUG_RELATIVE_POINTERS
200 depends on GENERIC_BUG
202 config GENERIC_HWEIGHT
208 config GENERIC_CALIBRATE_DELAY
214 config HAVE_GENERIC_GUP
217 config ARCH_DMA_ADDR_T_64BIT
220 config NEED_DMA_MAP_STATE
223 config NEED_SG_DMA_LENGTH
235 config KERNEL_MODE_NEON
238 config FIX_EARLYCON_MEM
241 config PGTABLE_LEVELS
243 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
244 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
245 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
246 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
247 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
248 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
250 config ARCH_SUPPORTS_UPROBES
253 config ARCH_PROC_KCORE_TEXT
256 source "init/Kconfig"
258 source "kernel/Kconfig.freezer"
260 source "arch/arm64/Kconfig.platforms"
267 This feature enables support for PCI bus system. If you say Y
268 here, the kernel will include drivers and infrastructure code
269 to support PCI bus devices.
274 config PCI_DOMAINS_GENERIC
280 source "drivers/pci/Kconfig"
284 menu "Kernel Features"
286 menu "ARM errata workarounds via the alternatives framework"
288 config ARM64_ERRATUM_826319
289 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
292 This option adds an alternative code sequence to work around ARM
293 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
294 AXI master interface and an L2 cache.
296 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
297 and is unable to accept a certain write via this interface, it will
298 not progress on read data presented on the read data channel and the
301 The workaround promotes data cache clean instructions to
302 data cache clean-and-invalidate.
303 Please note that this does not necessarily enable the workaround,
304 as it depends on the alternative framework, which will only patch
305 the kernel if an affected CPU is detected.
309 config ARM64_ERRATUM_827319
310 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
313 This option adds an alternative code sequence to work around ARM
314 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
315 master interface and an L2 cache.
317 Under certain conditions this erratum can cause a clean line eviction
318 to occur at the same time as another transaction to the same address
319 on the AMBA 5 CHI interface, which can cause data corruption if the
320 interconnect reorders the two transactions.
322 The workaround promotes data cache clean instructions to
323 data cache clean-and-invalidate.
324 Please note that this does not necessarily enable the workaround,
325 as it depends on the alternative framework, which will only patch
326 the kernel if an affected CPU is detected.
330 config ARM64_ERRATUM_824069
331 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
334 This option adds an alternative code sequence to work around ARM
335 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
336 to a coherent interconnect.
338 If a Cortex-A53 processor is executing a store or prefetch for
339 write instruction at the same time as a processor in another
340 cluster is executing a cache maintenance operation to the same
341 address, then this erratum might cause a clean cache line to be
342 incorrectly marked as dirty.
344 The workaround promotes data cache clean instructions to
345 data cache clean-and-invalidate.
346 Please note that this option does not necessarily enable the
347 workaround, as it depends on the alternative framework, which will
348 only patch the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_819472
353 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
356 This option adds an alternative code sequence to work around ARM
357 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
358 present when it is connected to a coherent interconnect.
360 If the processor is executing a load and store exclusive sequence at
361 the same time as a processor in another cluster is executing a cache
362 maintenance operation to the same address, then this erratum might
363 cause data corruption.
365 The workaround promotes data cache clean instructions to
366 data cache clean-and-invalidate.
367 Please note that this does not necessarily enable the workaround,
368 as it depends on the alternative framework, which will only patch
369 the kernel if an affected CPU is detected.
373 config ARM64_ERRATUM_832075
374 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
377 This option adds an alternative code sequence to work around ARM
378 erratum 832075 on Cortex-A57 parts up to r1p2.
380 Affected Cortex-A57 parts might deadlock when exclusive load/store
381 instructions to Write-Back memory are mixed with Device loads.
383 The workaround is to promote device loads to use Load-Acquire
385 Please note that this does not necessarily enable the workaround,
386 as it depends on the alternative framework, which will only patch
387 the kernel if an affected CPU is detected.
391 config ARM64_ERRATUM_834220
392 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
396 This option adds an alternative code sequence to work around ARM
397 erratum 834220 on Cortex-A57 parts up to r1p2.
399 Affected Cortex-A57 parts might report a Stage 2 translation
400 fault as the result of a Stage 1 fault for load crossing a
401 page boundary when there is a permission or device memory
402 alignment fault at Stage 1 and a translation fault at Stage 2.
404 The workaround is to verify that the Stage 1 translation
405 doesn't generate a fault before handling the Stage 2 fault.
406 Please note that this does not necessarily enable the workaround,
407 as it depends on the alternative framework, which will only patch
408 the kernel if an affected CPU is detected.
412 config ARM64_ERRATUM_845719
413 bool "Cortex-A53: 845719: a load might read incorrect data"
417 This option adds an alternative code sequence to work around ARM
418 erratum 845719 on Cortex-A53 parts up to r0p4.
420 When running a compat (AArch32) userspace on an affected Cortex-A53
421 part, a load at EL0 from a virtual address that matches the bottom 32
422 bits of the virtual address used by a recent load at (AArch64) EL1
423 might return incorrect data.
425 The workaround is to write the contextidr_el1 register on exception
426 return to a 32-bit task.
427 Please note that this does not necessarily enable the workaround,
428 as it depends on the alternative framework, which will only patch
429 the kernel if an affected CPU is detected.
433 config ARM64_ERRATUM_843419
434 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
436 select ARM64_MODULE_CMODEL_LARGE if MODULES
438 This option links the kernel with '--fix-cortex-a53-843419' and
439 builds modules using the large memory model in order to avoid the use
440 of the ADRP instruction, which can cause a subsequent memory access
441 to use an incorrect address on Cortex-A53 parts up to r0p4.
445 config CAVIUM_ERRATUM_22375
446 bool "Cavium erratum 22375, 24313"
449 Enable workaround for erratum 22375, 24313.
451 This implements two gicv3-its errata workarounds for ThunderX. Both
452 with small impact affecting only ITS table allocation.
454 erratum 22375: only alloc 8MB table size
455 erratum 24313: ignore memory access type
457 The fixes are in ITS initialization and basically ignore memory access
458 type and table size provided by the TYPER and BASER registers.
462 config CAVIUM_ERRATUM_23144
463 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
467 ITS SYNC command hang for cross node io and collections/cpu mapping.
471 config CAVIUM_ERRATUM_23154
472 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
475 The gicv3 of ThunderX requires a modified version for
476 reading the IAR status to ensure data synchronization
477 (access to icc_iar1_el1 is not sync'ed before and after).
481 config CAVIUM_ERRATUM_27456
482 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
485 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
486 instructions may cause the icache to become corrupted if it
487 contains data for a non-current ASID. The fix is to
488 invalidate the icache when changing the mm context.
492 config CAVIUM_ERRATUM_30115
493 bool "Cavium erratum 30115: Guest may disable interrupts in host"
496 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
497 1.2, and T83 Pass 1.0, KVM guest execution may disable
498 interrupts in host. Trapping both GICv3 group-0 and group-1
499 accesses sidesteps the issue.
503 config QCOM_FALKOR_ERRATUM_1003
504 bool "Falkor E1003: Incorrect translation due to ASID change"
506 select ARM64_PAN if ARM64_SW_TTBR0_PAN
508 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
509 and BADDR are changed together in TTBRx_EL1. The workaround for this
510 issue is to use a reserved ASID in cpu_do_switch_mm() before
511 switching to the new ASID. Saying Y here selects ARM64_PAN if
512 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
513 maintaining the E1003 workaround in the software PAN emulation code
514 would be an unnecessary complication. The affected Falkor v1 CPU
515 implements ARMv8.1 hardware PAN support and using hardware PAN
516 support versus software PAN emulation is mutually exclusive at
521 config QCOM_FALKOR_ERRATUM_1009
522 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
525 On Falkor v1, the CPU may prematurely complete a DSB following a
526 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
527 one more time to fix the issue.
531 config QCOM_QDF2400_ERRATUM_0065
532 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
535 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
536 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
537 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
546 default ARM64_4K_PAGES
548 Page size (translation granule) configuration.
550 config ARM64_4K_PAGES
553 This feature enables 4KB pages support.
555 config ARM64_16K_PAGES
558 The system will use 16KB pages support. AArch32 emulation
559 requires applications compiled with 16K (or a multiple of 16K)
562 config ARM64_64K_PAGES
565 This feature enables 64KB pages support (4KB by default)
566 allowing only two levels of page tables and faster TLB
567 look-up. AArch32 emulation requires applications compiled
568 with 64K aligned segments.
573 prompt "Virtual address space size"
574 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
575 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
576 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
578 Allows choosing one of multiple possible virtual address
579 space sizes. The level of translation table is determined by
580 a combination of page size and virtual address space size.
582 config ARM64_VA_BITS_36
583 bool "36-bit" if EXPERT
584 depends on ARM64_16K_PAGES
586 config ARM64_VA_BITS_39
588 depends on ARM64_4K_PAGES
590 config ARM64_VA_BITS_42
592 depends on ARM64_64K_PAGES
594 config ARM64_VA_BITS_47
596 depends on ARM64_16K_PAGES
598 config ARM64_VA_BITS_48
605 default 36 if ARM64_VA_BITS_36
606 default 39 if ARM64_VA_BITS_39
607 default 42 if ARM64_VA_BITS_42
608 default 47 if ARM64_VA_BITS_47
609 default 48 if ARM64_VA_BITS_48
611 config CPU_BIG_ENDIAN
612 bool "Build big-endian kernel"
614 Say Y if you plan on running a kernel in big-endian mode.
617 bool "Multi-core scheduler support"
619 Multi-core scheduler support improves the CPU scheduler's decision
620 making when dealing with multi-core CPU chips at a cost of slightly
621 increased overhead in some places. If unsure say N here.
624 bool "SMT scheduler support"
626 Improves the CPU scheduler's decision making when dealing with
627 MultiThreading at a cost of slightly increased overhead in some
628 places. If unsure say N here.
631 int "Maximum number of CPUs (2-4096)"
633 # These have to remain sorted largest to smallest
637 bool "Support for hot-pluggable CPUs"
638 select GENERIC_IRQ_MIGRATION
640 Say Y here to experiment with turning CPUs off and on. CPUs
641 can be controlled through /sys/devices/system/cpu.
643 # Common NUMA Features
645 bool "Numa Memory Allocation and Scheduler Support"
646 select ACPI_NUMA if ACPI
649 Enable NUMA (Non Uniform Memory Access) support.
651 The kernel will try to allocate memory used by a CPU on the
652 local memory of the CPU and add some more
653 NUMA awareness to the kernel.
656 int "Maximum NUMA Nodes (as a power of 2)"
659 depends on NEED_MULTIPLE_NODES
661 Specify the maximum number of NUMA Nodes available on the target
662 system. Increases memory reserved to accommodate various tables.
664 config USE_PERCPU_NUMA_NODE_ID
668 config HAVE_SETUP_PER_CPU_AREA
672 config NEED_PER_CPU_EMBED_FIRST_CHUNK
680 source kernel/Kconfig.preempt
681 source kernel/Kconfig.hz
683 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
686 config ARCH_HAS_HOLES_MEMORYMODEL
687 def_bool y if SPARSEMEM
689 config ARCH_SPARSEMEM_ENABLE
691 select SPARSEMEM_VMEMMAP_ENABLE
693 config ARCH_SPARSEMEM_DEFAULT
694 def_bool ARCH_SPARSEMEM_ENABLE
696 config ARCH_SELECT_MEMORY_MODEL
697 def_bool ARCH_SPARSEMEM_ENABLE
699 config HAVE_ARCH_PFN_VALID
700 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
702 config HW_PERF_EVENTS
706 config SYS_SUPPORTS_HUGETLBFS
709 config ARCH_WANT_HUGE_PMD_SHARE
710 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
712 config ARCH_HAS_CACHE_LINE_SIZE
718 bool "Enable seccomp to safely compute untrusted bytecode"
720 This kernel feature is useful for number crunching applications
721 that may need to compute untrusted bytecode during their
722 execution. By using pipes or other transports made available to
723 the process as file descriptors supporting the read/write
724 syscalls, it's possible to isolate those applications in
725 their own address space using seccomp. Once seccomp is
726 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
727 and the task is only allowed to execute a few safe syscalls
728 defined by each seccomp mode.
731 bool "Enable paravirtualization code"
733 This changes the kernel so it can modify itself when it is run
734 under a hypervisor, potentially improving performance significantly
735 over full virtualization.
737 config PARAVIRT_TIME_ACCOUNTING
738 bool "Paravirtual steal time accounting"
742 Select this option to enable fine granularity task steal time
743 accounting. Time spent executing other tasks in parallel with
744 the current vCPU is discounted from the vCPU power. To account for
745 that, there can be a small performance impact.
747 If in doubt, say N here.
750 depends on PM_SLEEP_SMP
752 bool "kexec system call"
754 kexec is a system call that implements the ability to shutdown your
755 current kernel, and to start another kernel. It is like a reboot
756 but it is independent of the system firmware. And like a reboot
757 you can start any kernel with it, not just Linux.
760 bool "Build kdump crash kernel"
762 Generate crash dump after being started by kexec. This should
763 be normally only set in special crash dump kernels which are
764 loaded in the main kernel with kexec-tools into a specially
765 reserved region and then later executed after a crash by
768 For more details see Documentation/kdump/kdump.txt
775 bool "Xen guest support on ARM64"
776 depends on ARM64 && OF
780 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
782 config FORCE_MAX_ZONEORDER
784 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
785 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
788 The kernel memory allocator divides physically contiguous memory
789 blocks into "zones", where each zone is a power of two number of
790 pages. This option selects the largest power of two that the kernel
791 keeps in the memory allocator. If you need to allocate very large
792 blocks of physically contiguous memory, then you may need to
795 This config option is actually maximum order plus one. For example,
796 a value of 11 means that the largest free memory block is 2^10 pages.
798 We make sure that we can allocate upto a HugePage size for each configuration.
800 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
802 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
803 4M allocations matching the default size used by generic code.
805 menuconfig ARMV8_DEPRECATED
806 bool "Emulate deprecated/obsolete ARMv8 instructions"
809 Legacy software support may require certain instructions
810 that have been deprecated or obsoleted in the architecture.
812 Enable this config to enable selective emulation of these
820 bool "Emulate SWP/SWPB instructions"
822 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
823 they are always undefined. Say Y here to enable software
824 emulation of these instructions for userspace using LDXR/STXR.
826 In some older versions of glibc [<=2.8] SWP is used during futex
827 trylock() operations with the assumption that the code will not
828 be preempted. This invalid assumption may be more likely to fail
829 with SWP emulation enabled, leading to deadlock of the user
832 NOTE: when accessing uncached shared regions, LDXR/STXR rely
833 on an external transaction monitoring block called a global
834 monitor to maintain update atomicity. If your system does not
835 implement a global monitor, this option can cause programs that
836 perform SWP operations to uncached memory to deadlock.
840 config CP15_BARRIER_EMULATION
841 bool "Emulate CP15 Barrier instructions"
843 The CP15 barrier instructions - CP15ISB, CP15DSB, and
844 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
845 strongly recommended to use the ISB, DSB, and DMB
846 instructions instead.
848 Say Y here to enable software emulation of these
849 instructions for AArch32 userspace code. When this option is
850 enabled, CP15 barrier usage is traced which can help
851 identify software that needs updating.
855 config SETEND_EMULATION
856 bool "Emulate SETEND instruction"
858 The SETEND instruction alters the data-endianness of the
859 AArch32 EL0, and is deprecated in ARMv8.
861 Say Y here to enable software emulation of the instruction
862 for AArch32 userspace code.
864 Note: All the cpus on the system must have mixed endian support at EL0
865 for this feature to be enabled. If a new CPU - which doesn't support mixed
866 endian - is hotplugged in after this feature has been enabled, there could
867 be unexpected results in the applications.
872 config ARM64_SW_TTBR0_PAN
873 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
875 Enabling this option prevents the kernel from accessing
876 user-space memory directly by pointing TTBR0_EL1 to a reserved
877 zeroed area and reserved ASID. The user access routines
878 restore the valid TTBR0_EL1 temporarily.
880 menu "ARMv8.1 architectural features"
882 config ARM64_HW_AFDBM
883 bool "Support for hardware updates of the Access and Dirty page flags"
886 The ARMv8.1 architecture extensions introduce support for
887 hardware updates of the access and dirty information in page
888 table entries. When enabled in TCR_EL1 (HA and HD bits) on
889 capable processors, accesses to pages with PTE_AF cleared will
890 set this bit instead of raising an access flag fault.
891 Similarly, writes to read-only pages with the DBM bit set will
892 clear the read-only bit (AP[2]) instead of raising a
895 Kernels built with this configuration option enabled continue
896 to work on pre-ARMv8.1 hardware and the performance impact is
897 minimal. If unsure, say Y.
900 bool "Enable support for Privileged Access Never (PAN)"
903 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
904 prevents the kernel or hypervisor from accessing user-space (EL0)
907 Choosing this option will cause any unprotected (not using
908 copy_to_user et al) memory access to fail with a permission fault.
910 The feature is detected at runtime, and will remain as a 'nop'
911 instruction if the cpu does not implement the feature.
913 config ARM64_LSE_ATOMICS
914 bool "Atomic instructions"
916 As part of the Large System Extensions, ARMv8.1 introduces new
917 atomic instructions that are designed specifically to scale in
920 Say Y here to make use of these instructions for the in-kernel
921 atomic routines. This incurs a small overhead on CPUs that do
922 not support these instructions and requires the kernel to be
923 built with binutils >= 2.25.
926 bool "Enable support for Virtualization Host Extensions (VHE)"
929 Virtualization Host Extensions (VHE) allow the kernel to run
930 directly at EL2 (instead of EL1) on processors that support
931 it. This leads to better performance for KVM, as they reduce
932 the cost of the world switch.
934 Selecting this option allows the VHE feature to be detected
935 at runtime, and does not affect processors that do not
936 implement this feature.
940 menu "ARMv8.2 architectural features"
943 bool "Enable support for User Access Override (UAO)"
946 User Access Override (UAO; part of the ARMv8.2 Extensions)
947 causes the 'unprivileged' variant of the load/store instructions to
948 be overriden to be privileged.
950 This option changes get_user() and friends to use the 'unprivileged'
951 variant of the load/store instructions. This ensures that user-space
952 really did have access to the supplied memory. When addr_limit is
953 set to kernel memory the UAO bit will be set, allowing privileged
954 access to kernel memory.
956 Choosing this option will cause copy_to_user() et al to use user-space
959 The feature is detected at runtime, the kernel will use the
960 regular load/store instructions if the cpu does not implement the
965 config ARM64_MODULE_CMODEL_LARGE
968 config ARM64_MODULE_PLTS
970 select ARM64_MODULE_CMODEL_LARGE
971 select HAVE_MOD_ARCH_SPECIFIC
976 This builds the kernel as a Position Independent Executable (PIE),
977 which retains all relocation metadata required to relocate the
978 kernel binary at runtime to a different virtual address than the
979 address it was linked at.
980 Since AArch64 uses the RELA relocation format, this requires a
981 relocation pass at runtime even if the kernel is loaded at the
982 same address it was linked at.
984 config RANDOMIZE_BASE
985 bool "Randomize the address of the kernel image"
986 select ARM64_MODULE_PLTS if MODULES
989 Randomizes the virtual address at which the kernel image is
990 loaded, as a security feature that deters exploit attempts
991 relying on knowledge of the location of kernel internals.
993 It is the bootloader's job to provide entropy, by passing a
994 random u64 value in /chosen/kaslr-seed at kernel entry.
996 When booting via the UEFI stub, it will invoke the firmware's
997 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
998 to the kernel proper. In addition, it will randomise the physical
999 location of the kernel Image as well.
1003 config RANDOMIZE_MODULE_REGION_FULL
1004 bool "Randomize the module region independently from the core kernel"
1005 depends on RANDOMIZE_BASE
1008 Randomizes the location of the module region without considering the
1009 location of the core kernel. This way, it is impossible for modules
1010 to leak information about the location of core kernel data structures
1011 but it does imply that function calls between modules and the core
1012 kernel will need to be resolved via veneers in the module PLT.
1014 When this option is not set, the module region will be randomized over
1015 a limited range that contains the [_stext, _etext] interval of the
1016 core kernel, so branch relocations are always in range.
1022 config ARM64_ACPI_PARKING_PROTOCOL
1023 bool "Enable support for the ARM64 ACPI parking protocol"
1026 Enable support for the ARM64 ACPI parking protocol. If disabled
1027 the kernel will not allow booting through the ARM64 ACPI parking
1028 protocol even if the corresponding data is present in the ACPI
1032 string "Default kernel command string"
1035 Provide a set of default command-line options at build time by
1036 entering them here. As a minimum, you should specify the the
1037 root device (e.g. root=/dev/nfs).
1039 config CMDLINE_FORCE
1040 bool "Always use the default kernel command string"
1042 Always use the default kernel command string, even if the boot
1043 loader passes other arguments to the kernel.
1044 This is useful if you cannot or don't want to change the
1045 command-line options your boot loader passes to the kernel.
1051 bool "UEFI runtime support"
1052 depends on OF && !CPU_BIG_ENDIAN
1055 select EFI_PARAMS_FROM_FDT
1056 select EFI_RUNTIME_WRAPPERS
1061 This option provides support for runtime services provided
1062 by UEFI firmware (such as non-volatile variables, realtime
1063 clock, and platform reset). A UEFI stub is also provided to
1064 allow the kernel to be booted as an EFI application. This
1065 is only useful on systems that have UEFI firmware.
1068 bool "Enable support for SMBIOS (DMI) tables"
1072 This enables SMBIOS/DMI feature for systems.
1074 This option is only useful on systems that have UEFI firmware.
1075 However, even with this option, the resultant kernel should
1076 continue to boot on existing non-UEFI platforms.
1080 menu "Userspace binary formats"
1082 source "fs/Kconfig.binfmt"
1085 bool "Kernel support for 32-bit EL0"
1086 depends on ARM64_4K_PAGES || EXPERT
1087 select COMPAT_BINFMT_ELF if BINFMT_ELF
1089 select OLD_SIGSUSPEND3
1090 select COMPAT_OLD_SIGACTION
1092 This option enables support for a 32-bit EL0 running under a 64-bit
1093 kernel at EL1. AArch32-specific components such as system calls,
1094 the user helper functions, VFP support and the ptrace interface are
1095 handled appropriately by the kernel.
1097 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1098 that you will only be able to execute AArch32 binaries that were compiled
1099 with page size aligned segments.
1101 If you want to execute 32-bit userspace applications, say Y.
1103 config SYSVIPC_COMPAT
1105 depends on COMPAT && SYSVIPC
1109 menu "Power management options"
1111 source "kernel/power/Kconfig"
1113 config ARCH_HIBERNATION_POSSIBLE
1117 config ARCH_HIBERNATION_HEADER
1119 depends on HIBERNATION
1121 config ARCH_SUSPEND_POSSIBLE
1126 menu "CPU Power Management"
1128 source "drivers/cpuidle/Kconfig"
1130 source "drivers/cpufreq/Kconfig"
1134 source "net/Kconfig"
1136 source "drivers/Kconfig"
1138 source "drivers/firmware/Kconfig"
1140 source "drivers/acpi/Kconfig"
1144 source "arch/arm64/kvm/Kconfig"
1146 source "arch/arm64/Kconfig.debug"
1148 source "security/Kconfig"
1150 source "crypto/Kconfig"
1152 source "arch/arm64/crypto/Kconfig"
1155 source "lib/Kconfig"