3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
25 select ARCH_INLINE_READ_LOCK if !PREEMPT
26 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
27 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
28 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
29 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
30 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
31 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
32 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
33 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
34 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
35 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
37 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
38 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
39 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
41 select ARCH_USE_CMPXCHG_LOCKREF
42 select ARCH_USE_QUEUED_RWLOCKS
43 select ARCH_SUPPORTS_MEMORY_FAILURE
44 select ARCH_SUPPORTS_ATOMIC_RMW
45 select ARCH_SUPPORTS_NUMA_BALANCING
46 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
47 select ARCH_WANT_FRAME_POINTERS
48 select ARCH_HAS_UBSAN_SANITIZE_ALL
52 select AUDIT_ARCH_COMPAT_GENERIC
53 select ARM_GIC_V2M if PCI
55 select ARM_GIC_V3_ITS if PCI
57 select BUILDTIME_EXTABLE_SORT
58 select CLONE_BACKWARDS
60 select CPU_PM if (SUSPEND || CPU_IDLE)
61 select DCACHE_WORD_ACCESS
64 select GENERIC_ALLOCATOR
65 select GENERIC_ARCH_TOPOLOGY
66 select GENERIC_CLOCKEVENTS
67 select GENERIC_CLOCKEVENTS_BROADCAST
68 select GENERIC_CPU_AUTOPROBE
69 select GENERIC_EARLY_IOREMAP
70 select GENERIC_IDLE_POLL_SETUP
71 select GENERIC_IRQ_PROBE
72 select GENERIC_IRQ_SHOW
73 select GENERIC_IRQ_SHOW_LEVEL
74 select GENERIC_PCI_IOMAP
75 select GENERIC_SCHED_CLOCK
76 select GENERIC_SMP_IDLE_THREAD
77 select GENERIC_STRNCPY_FROM_USER
78 select GENERIC_STRNLEN_USER
79 select GENERIC_TIME_VSYSCALL
80 select HANDLE_DOMAIN_IRQ
81 select HARDIRQS_SW_RESEND
82 select HAVE_ACPI_APEI if (ACPI && EFI)
83 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
84 select HAVE_ARCH_AUDITSYSCALL
85 select HAVE_ARCH_BITREVERSE
86 select HAVE_ARCH_HUGE_VMAP
87 select HAVE_ARCH_JUMP_LABEL
88 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
90 select HAVE_ARCH_MMAP_RND_BITS
91 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
92 select HAVE_ARCH_SECCOMP_FILTER
93 select HAVE_ARCH_TRACEHOOK
94 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
95 select HAVE_ARCH_VMAP_STACK
98 select HAVE_C_RECORDMCOUNT
99 select HAVE_CC_STACKPROTECTOR
100 select HAVE_CMPXCHG_DOUBLE
101 select HAVE_CMPXCHG_LOCAL
102 select HAVE_CONTEXT_TRACKING
103 select HAVE_DEBUG_BUGVERBOSE
104 select HAVE_DEBUG_KMEMLEAK
105 select HAVE_DMA_API_DEBUG
106 select HAVE_DMA_CONTIGUOUS
107 select HAVE_DYNAMIC_FTRACE
108 select HAVE_EFFICIENT_UNALIGNED_ACCESS
109 select HAVE_FTRACE_MCOUNT_RECORD
110 select HAVE_FUNCTION_TRACER
111 select HAVE_FUNCTION_GRAPH_TRACER
112 select HAVE_GCC_PLUGINS
113 select HAVE_GENERIC_DMA_COHERENT
114 select HAVE_HW_BREAKPOINT if PERF_EVENTS
115 select HAVE_IRQ_TIME_ACCOUNTING
117 select HAVE_MEMBLOCK_NODE_MAP if NUMA
118 select HAVE_NMI if ACPI_APEI_SEA
119 select HAVE_PATA_PLATFORM
120 select HAVE_PERF_EVENTS
121 select HAVE_PERF_REGS
122 select HAVE_PERF_USER_STACK_DUMP
123 select HAVE_REGS_AND_STACK_ACCESS_API
124 select HAVE_RCU_TABLE_FREE
125 select HAVE_SYSCALL_TRACEPOINTS
127 select HAVE_KRETPROBES
128 select IOMMU_DMA if IOMMU_SUPPORT
130 select IRQ_FORCED_THREADING
131 select MODULES_USE_ELF_RELA
134 select OF_EARLY_FLATTREE
135 select OF_RESERVED_MEM
136 select PCI_ECAM if ACPI
140 select SYSCTL_EXCEPTION_TRACE
141 select THREAD_INFO_IN_TASK
143 ARM 64-bit (AArch64) Linux support.
148 config ARCH_PHYS_ADDR_T_64BIT
154 config ARM64_PAGE_SHIFT
156 default 16 if ARM64_64K_PAGES
157 default 14 if ARM64_16K_PAGES
160 config ARM64_CONT_SHIFT
162 default 5 if ARM64_64K_PAGES
163 default 7 if ARM64_16K_PAGES
166 config ARCH_MMAP_RND_BITS_MIN
167 default 14 if ARM64_64K_PAGES
168 default 16 if ARM64_16K_PAGES
171 # max bits determined by the following formula:
172 # VA_BITS - PAGE_SHIFT - 3
173 config ARCH_MMAP_RND_BITS_MAX
174 default 19 if ARM64_VA_BITS=36
175 default 24 if ARM64_VA_BITS=39
176 default 27 if ARM64_VA_BITS=42
177 default 30 if ARM64_VA_BITS=47
178 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
179 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
180 default 33 if ARM64_VA_BITS=48
181 default 14 if ARM64_64K_PAGES
182 default 16 if ARM64_16K_PAGES
185 config ARCH_MMAP_RND_COMPAT_BITS_MIN
186 default 7 if ARM64_64K_PAGES
187 default 9 if ARM64_16K_PAGES
190 config ARCH_MMAP_RND_COMPAT_BITS_MAX
196 config STACKTRACE_SUPPORT
199 config ILLEGAL_POINTER_VALUE
201 default 0xdead000000000000
203 config LOCKDEP_SUPPORT
206 config TRACE_IRQFLAGS_SUPPORT
209 config RWSEM_XCHGADD_ALGORITHM
216 config GENERIC_BUG_RELATIVE_POINTERS
218 depends on GENERIC_BUG
220 config GENERIC_HWEIGHT
226 config GENERIC_CALIBRATE_DELAY
232 config HAVE_GENERIC_GUP
235 config ARCH_DMA_ADDR_T_64BIT
238 config NEED_DMA_MAP_STATE
241 config NEED_SG_DMA_LENGTH
253 config KERNEL_MODE_NEON
256 config FIX_EARLYCON_MEM
259 config PGTABLE_LEVELS
261 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
262 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
263 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
264 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
265 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
266 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
268 config ARCH_SUPPORTS_UPROBES
271 config ARCH_PROC_KCORE_TEXT
274 source "init/Kconfig"
276 source "kernel/Kconfig.freezer"
278 source "arch/arm64/Kconfig.platforms"
285 This feature enables support for PCI bus system. If you say Y
286 here, the kernel will include drivers and infrastructure code
287 to support PCI bus devices.
292 config PCI_DOMAINS_GENERIC
298 source "drivers/pci/Kconfig"
302 menu "Kernel Features"
304 menu "ARM errata workarounds via the alternatives framework"
306 config ARM64_ERRATUM_826319
307 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
310 This option adds an alternative code sequence to work around ARM
311 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
312 AXI master interface and an L2 cache.
314 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
315 and is unable to accept a certain write via this interface, it will
316 not progress on read data presented on the read data channel and the
319 The workaround promotes data cache clean instructions to
320 data cache clean-and-invalidate.
321 Please note that this does not necessarily enable the workaround,
322 as it depends on the alternative framework, which will only patch
323 the kernel if an affected CPU is detected.
327 config ARM64_ERRATUM_827319
328 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
331 This option adds an alternative code sequence to work around ARM
332 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
333 master interface and an L2 cache.
335 Under certain conditions this erratum can cause a clean line eviction
336 to occur at the same time as another transaction to the same address
337 on the AMBA 5 CHI interface, which can cause data corruption if the
338 interconnect reorders the two transactions.
340 The workaround promotes data cache clean instructions to
341 data cache clean-and-invalidate.
342 Please note that this does not necessarily enable the workaround,
343 as it depends on the alternative framework, which will only patch
344 the kernel if an affected CPU is detected.
348 config ARM64_ERRATUM_824069
349 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
352 This option adds an alternative code sequence to work around ARM
353 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
354 to a coherent interconnect.
356 If a Cortex-A53 processor is executing a store or prefetch for
357 write instruction at the same time as a processor in another
358 cluster is executing a cache maintenance operation to the same
359 address, then this erratum might cause a clean cache line to be
360 incorrectly marked as dirty.
362 The workaround promotes data cache clean instructions to
363 data cache clean-and-invalidate.
364 Please note that this option does not necessarily enable the
365 workaround, as it depends on the alternative framework, which will
366 only patch the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_819472
371 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
374 This option adds an alternative code sequence to work around ARM
375 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
376 present when it is connected to a coherent interconnect.
378 If the processor is executing a load and store exclusive sequence at
379 the same time as a processor in another cluster is executing a cache
380 maintenance operation to the same address, then this erratum might
381 cause data corruption.
383 The workaround promotes data cache clean instructions to
384 data cache clean-and-invalidate.
385 Please note that this does not necessarily enable the workaround,
386 as it depends on the alternative framework, which will only patch
387 the kernel if an affected CPU is detected.
391 config ARM64_ERRATUM_832075
392 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
395 This option adds an alternative code sequence to work around ARM
396 erratum 832075 on Cortex-A57 parts up to r1p2.
398 Affected Cortex-A57 parts might deadlock when exclusive load/store
399 instructions to Write-Back memory are mixed with Device loads.
401 The workaround is to promote device loads to use Load-Acquire
403 Please note that this does not necessarily enable the workaround,
404 as it depends on the alternative framework, which will only patch
405 the kernel if an affected CPU is detected.
409 config ARM64_ERRATUM_834220
410 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
414 This option adds an alternative code sequence to work around ARM
415 erratum 834220 on Cortex-A57 parts up to r1p2.
417 Affected Cortex-A57 parts might report a Stage 2 translation
418 fault as the result of a Stage 1 fault for load crossing a
419 page boundary when there is a permission or device memory
420 alignment fault at Stage 1 and a translation fault at Stage 2.
422 The workaround is to verify that the Stage 1 translation
423 doesn't generate a fault before handling the Stage 2 fault.
424 Please note that this does not necessarily enable the workaround,
425 as it depends on the alternative framework, which will only patch
426 the kernel if an affected CPU is detected.
430 config ARM64_ERRATUM_845719
431 bool "Cortex-A53: 845719: a load might read incorrect data"
435 This option adds an alternative code sequence to work around ARM
436 erratum 845719 on Cortex-A53 parts up to r0p4.
438 When running a compat (AArch32) userspace on an affected Cortex-A53
439 part, a load at EL0 from a virtual address that matches the bottom 32
440 bits of the virtual address used by a recent load at (AArch64) EL1
441 might return incorrect data.
443 The workaround is to write the contextidr_el1 register on exception
444 return to a 32-bit task.
445 Please note that this does not necessarily enable the workaround,
446 as it depends on the alternative framework, which will only patch
447 the kernel if an affected CPU is detected.
451 config ARM64_ERRATUM_843419
452 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
454 select ARM64_MODULE_CMODEL_LARGE if MODULES
456 This option links the kernel with '--fix-cortex-a53-843419' and
457 builds modules using the large memory model in order to avoid the use
458 of the ADRP instruction, which can cause a subsequent memory access
459 to use an incorrect address on Cortex-A53 parts up to r0p4.
463 config CAVIUM_ERRATUM_22375
464 bool "Cavium erratum 22375, 24313"
467 Enable workaround for erratum 22375, 24313.
469 This implements two gicv3-its errata workarounds for ThunderX. Both
470 with small impact affecting only ITS table allocation.
472 erratum 22375: only alloc 8MB table size
473 erratum 24313: ignore memory access type
475 The fixes are in ITS initialization and basically ignore memory access
476 type and table size provided by the TYPER and BASER registers.
480 config CAVIUM_ERRATUM_23144
481 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
485 ITS SYNC command hang for cross node io and collections/cpu mapping.
489 config CAVIUM_ERRATUM_23154
490 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
493 The gicv3 of ThunderX requires a modified version for
494 reading the IAR status to ensure data synchronization
495 (access to icc_iar1_el1 is not sync'ed before and after).
499 config CAVIUM_ERRATUM_27456
500 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
503 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
504 instructions may cause the icache to become corrupted if it
505 contains data for a non-current ASID. The fix is to
506 invalidate the icache when changing the mm context.
510 config CAVIUM_ERRATUM_30115
511 bool "Cavium erratum 30115: Guest may disable interrupts in host"
514 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
515 1.2, and T83 Pass 1.0, KVM guest execution may disable
516 interrupts in host. Trapping both GICv3 group-0 and group-1
517 accesses sidesteps the issue.
521 config QCOM_FALKOR_ERRATUM_1003
522 bool "Falkor E1003: Incorrect translation due to ASID change"
525 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
526 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
527 in TTBR1_EL1, this situation only occurs in the entry trampoline and
528 then only for entries in the walk cache, since the leaf translation
529 is unchanged. Work around the erratum by invalidating the walk cache
530 entries for the trampoline before entering the kernel proper.
532 config QCOM_FALKOR_ERRATUM_1009
533 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
536 On Falkor v1, the CPU may prematurely complete a DSB following a
537 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
538 one more time to fix the issue.
542 config QCOM_QDF2400_ERRATUM_0065
543 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
546 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
547 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
548 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
552 config QCOM_FALKOR_ERRATUM_E1041
553 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
556 Falkor CPU may speculatively fetch instructions from an improper
557 memory location when MMU translation is changed from SCTLR_ELn[M]=1
558 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
567 default ARM64_4K_PAGES
569 Page size (translation granule) configuration.
571 config ARM64_4K_PAGES
574 This feature enables 4KB pages support.
576 config ARM64_16K_PAGES
579 The system will use 16KB pages support. AArch32 emulation
580 requires applications compiled with 16K (or a multiple of 16K)
583 config ARM64_64K_PAGES
586 This feature enables 64KB pages support (4KB by default)
587 allowing only two levels of page tables and faster TLB
588 look-up. AArch32 emulation requires applications compiled
589 with 64K aligned segments.
594 prompt "Virtual address space size"
595 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
596 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
597 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
599 Allows choosing one of multiple possible virtual address
600 space sizes. The level of translation table is determined by
601 a combination of page size and virtual address space size.
603 config ARM64_VA_BITS_36
604 bool "36-bit" if EXPERT
605 depends on ARM64_16K_PAGES
607 config ARM64_VA_BITS_39
609 depends on ARM64_4K_PAGES
611 config ARM64_VA_BITS_42
613 depends on ARM64_64K_PAGES
615 config ARM64_VA_BITS_47
617 depends on ARM64_16K_PAGES
619 config ARM64_VA_BITS_48
626 default 36 if ARM64_VA_BITS_36
627 default 39 if ARM64_VA_BITS_39
628 default 42 if ARM64_VA_BITS_42
629 default 47 if ARM64_VA_BITS_47
630 default 48 if ARM64_VA_BITS_48
632 config CPU_BIG_ENDIAN
633 bool "Build big-endian kernel"
635 Say Y if you plan on running a kernel in big-endian mode.
638 bool "Multi-core scheduler support"
640 Multi-core scheduler support improves the CPU scheduler's decision
641 making when dealing with multi-core CPU chips at a cost of slightly
642 increased overhead in some places. If unsure say N here.
645 bool "SMT scheduler support"
647 Improves the CPU scheduler's decision making when dealing with
648 MultiThreading at a cost of slightly increased overhead in some
649 places. If unsure say N here.
652 int "Maximum number of CPUs (2-4096)"
654 # These have to remain sorted largest to smallest
658 bool "Support for hot-pluggable CPUs"
659 select GENERIC_IRQ_MIGRATION
661 Say Y here to experiment with turning CPUs off and on. CPUs
662 can be controlled through /sys/devices/system/cpu.
664 # Common NUMA Features
666 bool "Numa Memory Allocation and Scheduler Support"
667 select ACPI_NUMA if ACPI
670 Enable NUMA (Non Uniform Memory Access) support.
672 The kernel will try to allocate memory used by a CPU on the
673 local memory of the CPU and add some more
674 NUMA awareness to the kernel.
677 int "Maximum NUMA Nodes (as a power of 2)"
680 depends on NEED_MULTIPLE_NODES
682 Specify the maximum number of NUMA Nodes available on the target
683 system. Increases memory reserved to accommodate various tables.
685 config USE_PERCPU_NUMA_NODE_ID
689 config HAVE_SETUP_PER_CPU_AREA
693 config NEED_PER_CPU_EMBED_FIRST_CHUNK
701 source kernel/Kconfig.preempt
702 source kernel/Kconfig.hz
704 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
707 config ARCH_HAS_HOLES_MEMORYMODEL
708 def_bool y if SPARSEMEM
710 config ARCH_SPARSEMEM_ENABLE
712 select SPARSEMEM_VMEMMAP_ENABLE
714 config ARCH_SPARSEMEM_DEFAULT
715 def_bool ARCH_SPARSEMEM_ENABLE
717 config ARCH_SELECT_MEMORY_MODEL
718 def_bool ARCH_SPARSEMEM_ENABLE
720 config HAVE_ARCH_PFN_VALID
721 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
723 config HW_PERF_EVENTS
727 config SYS_SUPPORTS_HUGETLBFS
730 config ARCH_WANT_HUGE_PMD_SHARE
731 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
733 config ARCH_HAS_CACHE_LINE_SIZE
739 bool "Enable seccomp to safely compute untrusted bytecode"
741 This kernel feature is useful for number crunching applications
742 that may need to compute untrusted bytecode during their
743 execution. By using pipes or other transports made available to
744 the process as file descriptors supporting the read/write
745 syscalls, it's possible to isolate those applications in
746 their own address space using seccomp. Once seccomp is
747 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
748 and the task is only allowed to execute a few safe syscalls
749 defined by each seccomp mode.
752 bool "Enable paravirtualization code"
754 This changes the kernel so it can modify itself when it is run
755 under a hypervisor, potentially improving performance significantly
756 over full virtualization.
758 config PARAVIRT_TIME_ACCOUNTING
759 bool "Paravirtual steal time accounting"
763 Select this option to enable fine granularity task steal time
764 accounting. Time spent executing other tasks in parallel with
765 the current vCPU is discounted from the vCPU power. To account for
766 that, there can be a small performance impact.
768 If in doubt, say N here.
771 depends on PM_SLEEP_SMP
773 bool "kexec system call"
775 kexec is a system call that implements the ability to shutdown your
776 current kernel, and to start another kernel. It is like a reboot
777 but it is independent of the system firmware. And like a reboot
778 you can start any kernel with it, not just Linux.
781 bool "Build kdump crash kernel"
783 Generate crash dump after being started by kexec. This should
784 be normally only set in special crash dump kernels which are
785 loaded in the main kernel with kexec-tools into a specially
786 reserved region and then later executed after a crash by
789 For more details see Documentation/kdump/kdump.txt
796 bool "Xen guest support on ARM64"
797 depends on ARM64 && OF
801 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
803 config FORCE_MAX_ZONEORDER
805 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
806 default "13" if (ARCH_THUNDER && ARM64_4K_PAGES)
807 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
810 The kernel memory allocator divides physically contiguous memory
811 blocks into "zones", where each zone is a power of two number of
812 pages. This option selects the largest power of two that the kernel
813 keeps in the memory allocator. If you need to allocate very large
814 blocks of physically contiguous memory, then you may need to
817 This config option is actually maximum order plus one. For example,
818 a value of 11 means that the largest free memory block is 2^10 pages.
820 We make sure that we can allocate upto a HugePage size for each configuration.
822 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
824 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
825 4M allocations matching the default size used by generic code.
827 config UNMAP_KERNEL_AT_EL0
828 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
831 Speculation attacks against some high-performance processors can
832 be used to bypass MMU permission checks and leak kernel data to
833 userspace. This can be defended against by unmapping the kernel
834 when running in userspace, mapping it back in on exception entry
835 via a trampoline page in the vector table.
839 menuconfig ARMV8_DEPRECATED
840 bool "Emulate deprecated/obsolete ARMv8 instructions"
843 Legacy software support may require certain instructions
844 that have been deprecated or obsoleted in the architecture.
846 Enable this config to enable selective emulation of these
854 bool "Emulate SWP/SWPB instructions"
856 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
857 they are always undefined. Say Y here to enable software
858 emulation of these instructions for userspace using LDXR/STXR.
860 In some older versions of glibc [<=2.8] SWP is used during futex
861 trylock() operations with the assumption that the code will not
862 be preempted. This invalid assumption may be more likely to fail
863 with SWP emulation enabled, leading to deadlock of the user
866 NOTE: when accessing uncached shared regions, LDXR/STXR rely
867 on an external transaction monitoring block called a global
868 monitor to maintain update atomicity. If your system does not
869 implement a global monitor, this option can cause programs that
870 perform SWP operations to uncached memory to deadlock.
874 config CP15_BARRIER_EMULATION
875 bool "Emulate CP15 Barrier instructions"
877 The CP15 barrier instructions - CP15ISB, CP15DSB, and
878 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
879 strongly recommended to use the ISB, DSB, and DMB
880 instructions instead.
882 Say Y here to enable software emulation of these
883 instructions for AArch32 userspace code. When this option is
884 enabled, CP15 barrier usage is traced which can help
885 identify software that needs updating.
889 config SETEND_EMULATION
890 bool "Emulate SETEND instruction"
892 The SETEND instruction alters the data-endianness of the
893 AArch32 EL0, and is deprecated in ARMv8.
895 Say Y here to enable software emulation of the instruction
896 for AArch32 userspace code.
898 Note: All the cpus on the system must have mixed endian support at EL0
899 for this feature to be enabled. If a new CPU - which doesn't support mixed
900 endian - is hotplugged in after this feature has been enabled, there could
901 be unexpected results in the applications.
906 config ARM64_SW_TTBR0_PAN
907 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
909 Enabling this option prevents the kernel from accessing
910 user-space memory directly by pointing TTBR0_EL1 to a reserved
911 zeroed area and reserved ASID. The user access routines
912 restore the valid TTBR0_EL1 temporarily.
914 menu "ARMv8.1 architectural features"
916 config ARM64_HW_AFDBM
917 bool "Support for hardware updates of the Access and Dirty page flags"
920 The ARMv8.1 architecture extensions introduce support for
921 hardware updates of the access and dirty information in page
922 table entries. When enabled in TCR_EL1 (HA and HD bits) on
923 capable processors, accesses to pages with PTE_AF cleared will
924 set this bit instead of raising an access flag fault.
925 Similarly, writes to read-only pages with the DBM bit set will
926 clear the read-only bit (AP[2]) instead of raising a
929 Kernels built with this configuration option enabled continue
930 to work on pre-ARMv8.1 hardware and the performance impact is
931 minimal. If unsure, say Y.
934 bool "Enable support for Privileged Access Never (PAN)"
937 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
938 prevents the kernel or hypervisor from accessing user-space (EL0)
941 Choosing this option will cause any unprotected (not using
942 copy_to_user et al) memory access to fail with a permission fault.
944 The feature is detected at runtime, and will remain as a 'nop'
945 instruction if the cpu does not implement the feature.
947 config ARM64_LSE_ATOMICS
948 bool "Atomic instructions"
950 As part of the Large System Extensions, ARMv8.1 introduces new
951 atomic instructions that are designed specifically to scale in
954 Say Y here to make use of these instructions for the in-kernel
955 atomic routines. This incurs a small overhead on CPUs that do
956 not support these instructions and requires the kernel to be
957 built with binutils >= 2.25.
960 bool "Enable support for Virtualization Host Extensions (VHE)"
963 Virtualization Host Extensions (VHE) allow the kernel to run
964 directly at EL2 (instead of EL1) on processors that support
965 it. This leads to better performance for KVM, as they reduce
966 the cost of the world switch.
968 Selecting this option allows the VHE feature to be detected
969 at runtime, and does not affect processors that do not
970 implement this feature.
974 menu "ARMv8.2 architectural features"
977 bool "Enable support for User Access Override (UAO)"
980 User Access Override (UAO; part of the ARMv8.2 Extensions)
981 causes the 'unprivileged' variant of the load/store instructions to
982 be overriden to be privileged.
984 This option changes get_user() and friends to use the 'unprivileged'
985 variant of the load/store instructions. This ensures that user-space
986 really did have access to the supplied memory. When addr_limit is
987 set to kernel memory the UAO bit will be set, allowing privileged
988 access to kernel memory.
990 Choosing this option will cause copy_to_user() et al to use user-space
993 The feature is detected at runtime, the kernel will use the
994 regular load/store instructions if the cpu does not implement the
998 bool "Enable support for persistent memory"
999 select ARCH_HAS_PMEM_API
1000 select ARCH_HAS_UACCESS_FLUSHCACHE
1002 Say Y to enable support for the persistent memory API based on the
1003 ARMv8.2 DCPoP feature.
1005 The feature is detected at runtime, and the kernel will use DC CVAC
1006 operations if DC CVAP is not supported (following the behaviour of
1007 DC CVAP itself if the system does not define a point of persistence).
1011 config ARM64_MODULE_CMODEL_LARGE
1014 config ARM64_MODULE_PLTS
1016 select ARM64_MODULE_CMODEL_LARGE
1017 select HAVE_MOD_ARCH_SPECIFIC
1022 This builds the kernel as a Position Independent Executable (PIE),
1023 which retains all relocation metadata required to relocate the
1024 kernel binary at runtime to a different virtual address than the
1025 address it was linked at.
1026 Since AArch64 uses the RELA relocation format, this requires a
1027 relocation pass at runtime even if the kernel is loaded at the
1028 same address it was linked at.
1030 config RANDOMIZE_BASE
1031 bool "Randomize the address of the kernel image"
1032 select ARM64_MODULE_PLTS if MODULES
1035 Randomizes the virtual address at which the kernel image is
1036 loaded, as a security feature that deters exploit attempts
1037 relying on knowledge of the location of kernel internals.
1039 It is the bootloader's job to provide entropy, by passing a
1040 random u64 value in /chosen/kaslr-seed at kernel entry.
1042 When booting via the UEFI stub, it will invoke the firmware's
1043 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1044 to the kernel proper. In addition, it will randomise the physical
1045 location of the kernel Image as well.
1049 config RANDOMIZE_MODULE_REGION_FULL
1050 bool "Randomize the module region independently from the core kernel"
1051 depends on RANDOMIZE_BASE
1054 Randomizes the location of the module region without considering the
1055 location of the core kernel. This way, it is impossible for modules
1056 to leak information about the location of core kernel data structures
1057 but it does imply that function calls between modules and the core
1058 kernel will need to be resolved via veneers in the module PLT.
1060 When this option is not set, the module region will be randomized over
1061 a limited range that contains the [_stext, _etext] interval of the
1062 core kernel, so branch relocations are always in range.
1068 config ARM64_ACPI_PARKING_PROTOCOL
1069 bool "Enable support for the ARM64 ACPI parking protocol"
1072 Enable support for the ARM64 ACPI parking protocol. If disabled
1073 the kernel will not allow booting through the ARM64 ACPI parking
1074 protocol even if the corresponding data is present in the ACPI
1078 string "Default kernel command string"
1081 Provide a set of default command-line options at build time by
1082 entering them here. As a minimum, you should specify the the
1083 root device (e.g. root=/dev/nfs).
1085 config CMDLINE_FORCE
1086 bool "Always use the default kernel command string"
1088 Always use the default kernel command string, even if the boot
1089 loader passes other arguments to the kernel.
1090 This is useful if you cannot or don't want to change the
1091 command-line options your boot loader passes to the kernel.
1097 bool "UEFI runtime support"
1098 depends on OF && !CPU_BIG_ENDIAN
1101 select EFI_PARAMS_FROM_FDT
1102 select EFI_RUNTIME_WRAPPERS
1107 This option provides support for runtime services provided
1108 by UEFI firmware (such as non-volatile variables, realtime
1109 clock, and platform reset). A UEFI stub is also provided to
1110 allow the kernel to be booted as an EFI application. This
1111 is only useful on systems that have UEFI firmware.
1114 bool "Enable support for SMBIOS (DMI) tables"
1118 This enables SMBIOS/DMI feature for systems.
1120 This option is only useful on systems that have UEFI firmware.
1121 However, even with this option, the resultant kernel should
1122 continue to boot on existing non-UEFI platforms.
1126 menu "Userspace binary formats"
1128 source "fs/Kconfig.binfmt"
1131 bool "Kernel support for 32-bit EL0"
1132 depends on ARM64_4K_PAGES || EXPERT
1133 select COMPAT_BINFMT_ELF if BINFMT_ELF
1135 select OLD_SIGSUSPEND3
1136 select COMPAT_OLD_SIGACTION
1138 This option enables support for a 32-bit EL0 running under a 64-bit
1139 kernel at EL1. AArch32-specific components such as system calls,
1140 the user helper functions, VFP support and the ptrace interface are
1141 handled appropriately by the kernel.
1143 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1144 that you will only be able to execute AArch32 binaries that were compiled
1145 with page size aligned segments.
1147 If you want to execute 32-bit userspace applications, say Y.
1149 config SYSVIPC_COMPAT
1151 depends on COMPAT && SYSVIPC
1155 menu "Power management options"
1157 source "kernel/power/Kconfig"
1159 config ARCH_HIBERNATION_POSSIBLE
1163 config ARCH_HIBERNATION_HEADER
1165 depends on HIBERNATION
1167 config ARCH_SUSPEND_POSSIBLE
1172 menu "CPU Power Management"
1174 source "drivers/cpuidle/Kconfig"
1176 source "drivers/cpufreq/Kconfig"
1180 source "net/Kconfig"
1182 source "drivers/Kconfig"
1184 source "ubuntu/Kconfig"
1186 source "drivers/firmware/Kconfig"
1188 source "drivers/acpi/Kconfig"
1192 source "arch/arm64/kvm/Kconfig"
1194 source "arch/arm64/Kconfig.debug"
1196 source "security/Kconfig"
1198 source "crypto/Kconfig"
1200 source "arch/arm64/crypto/Kconfig"
1203 source "lib/Kconfig"