3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_BITREVERSE
43 select HAVE_ARCH_JUMP_LABEL
45 select HAVE_ARCH_SECCOMP_FILTER
46 select HAVE_ARCH_TRACEHOOK
48 select HAVE_C_RECORDMCOUNT
49 select HAVE_CC_STACKPROTECTOR
50 select HAVE_CMPXCHG_DOUBLE
51 select HAVE_DEBUG_BUGVERBOSE
52 select HAVE_DEBUG_KMEMLEAK
53 select HAVE_DMA_API_DEBUG
55 select HAVE_DMA_CONTIGUOUS
56 select HAVE_DYNAMIC_FTRACE
57 select HAVE_EFFICIENT_UNALIGNED_ACCESS
58 select HAVE_FTRACE_MCOUNT_RECORD
59 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
61 select HAVE_GENERIC_DMA_COHERENT
62 select HAVE_HW_BREAKPOINT if PERF_EVENTS
64 select HAVE_PATA_PLATFORM
65 select HAVE_PERF_EVENTS
67 select HAVE_PERF_USER_STACK_DUMP
68 select HAVE_RCU_TABLE_FREE
69 select HAVE_SYSCALL_TRACEPOINTS
71 select MODULES_USE_ELF_RELA
74 select OF_EARLY_FLATTREE
75 select OF_RESERVED_MEM
76 select PERF_USE_VMALLOC
81 select SYSCTL_EXCEPTION_TRACE
82 select HAVE_CONTEXT_TRACKING
84 ARM 64-bit (AArch64) Linux support.
89 config ARCH_PHYS_ADDR_T_64BIT
98 config STACKTRACE_SUPPORT
101 config LOCKDEP_SUPPORT
104 config TRACE_IRQFLAGS_SUPPORT
107 config RWSEM_XCHGADD_ALGORITHM
110 config GENERIC_HWEIGHT
116 config GENERIC_CALIBRATE_DELAY
122 config HAVE_GENERIC_RCU_GUP
125 config ARCH_DMA_ADDR_T_64BIT
128 config NEED_DMA_MAP_STATE
131 config NEED_SG_DMA_LENGTH
140 config KERNEL_MODE_NEON
143 config FIX_EARLYCON_MEM
146 source "init/Kconfig"
148 source "kernel/Kconfig.freezer"
150 menu "Platform selection"
153 bool "AMD Seattle SoC Family"
155 This enables support for AMD Seattle SOC Family
158 bool "Cavium Inc. Thunder SoC Family"
160 This enables support for Cavium's Thunder Family of SoCs.
163 bool "ARMv8 software model (Versatile Express)"
164 select ARCH_REQUIRE_GPIOLIB
165 select COMMON_CLK_VERSATILE
166 select POWER_RESET_VEXPRESS
167 select VEXPRESS_CONFIG
169 This enables support for the ARMv8 software model (Versatile
173 bool "AppliedMicro X-Gene SOC Family"
175 This enables support for AppliedMicro X-Gene SOC Family
184 This feature enables support for PCI bus system. If you say Y
185 here, the kernel will include drivers and infrastructure code
186 to support PCI bus devices.
191 config PCI_DOMAINS_GENERIC
197 source "drivers/pci/Kconfig"
198 source "drivers/pci/pcie/Kconfig"
199 source "drivers/pci/hotplug/Kconfig"
203 menu "Kernel Features"
205 menu "ARM errata workarounds via the alternatives framework"
207 config ARM64_ERRATUM_826319
208 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
211 This option adds an alternative code sequence to work around ARM
212 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
213 AXI master interface and an L2 cache.
215 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
216 and is unable to accept a certain write via this interface, it will
217 not progress on read data presented on the read data channel and the
220 The workaround promotes data cache clean instructions to
221 data cache clean-and-invalidate.
222 Please note that this does not necessarily enable the workaround,
223 as it depends on the alternative framework, which will only patch
224 the kernel if an affected CPU is detected.
228 config ARM64_ERRATUM_827319
229 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
232 This option adds an alternative code sequence to work around ARM
233 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
234 master interface and an L2 cache.
236 Under certain conditions this erratum can cause a clean line eviction
237 to occur at the same time as another transaction to the same address
238 on the AMBA 5 CHI interface, which can cause data corruption if the
239 interconnect reorders the two transactions.
241 The workaround promotes data cache clean instructions to
242 data cache clean-and-invalidate.
243 Please note that this does not necessarily enable the workaround,
244 as it depends on the alternative framework, which will only patch
245 the kernel if an affected CPU is detected.
249 config ARM64_ERRATUM_824069
250 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
253 This option adds an alternative code sequence to work around ARM
254 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
255 to a coherent interconnect.
257 If a Cortex-A53 processor is executing a store or prefetch for
258 write instruction at the same time as a processor in another
259 cluster is executing a cache maintenance operation to the same
260 address, then this erratum might cause a clean cache line to be
261 incorrectly marked as dirty.
263 The workaround promotes data cache clean instructions to
264 data cache clean-and-invalidate.
265 Please note that this option does not necessarily enable the
266 workaround, as it depends on the alternative framework, which will
267 only patch the kernel if an affected CPU is detected.
271 config ARM64_ERRATUM_819472
272 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
275 This option adds an alternative code sequence to work around ARM
276 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
277 present when it is connected to a coherent interconnect.
279 If the processor is executing a load and store exclusive sequence at
280 the same time as a processor in another cluster is executing a cache
281 maintenance operation to the same address, then this erratum might
282 cause data corruption.
284 The workaround promotes data cache clean instructions to
285 data cache clean-and-invalidate.
286 Please note that this does not necessarily enable the workaround,
287 as it depends on the alternative framework, which will only patch
288 the kernel if an affected CPU is detected.
292 config ARM64_ERRATUM_832075
293 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
296 This option adds an alternative code sequence to work around ARM
297 erratum 832075 on Cortex-A57 parts up to r1p2.
299 Affected Cortex-A57 parts might deadlock when exclusive load/store
300 instructions to Write-Back memory are mixed with Device loads.
302 The workaround is to promote device loads to use Load-Acquire
304 Please note that this does not necessarily enable the workaround,
305 as it depends on the alternative framework, which will only patch
306 the kernel if an affected CPU is detected.
315 default ARM64_4K_PAGES
317 Page size (translation granule) configuration.
319 config ARM64_4K_PAGES
322 This feature enables 4KB pages support.
324 config ARM64_64K_PAGES
327 This feature enables 64KB pages support (4KB by default)
328 allowing only two levels of page tables and faster TLB
329 look-up. AArch32 emulation is not available when this feature
335 prompt "Virtual address space size"
336 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
337 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
339 Allows choosing one of multiple possible virtual address
340 space sizes. The level of translation table is determined by
341 a combination of page size and virtual address space size.
343 config ARM64_VA_BITS_39
345 depends on ARM64_4K_PAGES
347 config ARM64_VA_BITS_42
349 depends on ARM64_64K_PAGES
351 config ARM64_VA_BITS_48
359 default 39 if ARM64_VA_BITS_39
360 default 42 if ARM64_VA_BITS_42
361 default 48 if ARM64_VA_BITS_48
363 config ARM64_PGTABLE_LEVELS
365 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
366 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
367 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
368 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
370 config CPU_BIG_ENDIAN
371 bool "Build big-endian kernel"
373 Say Y if you plan on running a kernel in big-endian mode.
376 bool "Symmetric Multi-Processing"
378 This enables support for systems with more than one CPU. If
379 you say N here, the kernel will run on single and
380 multiprocessor machines, but will use only one CPU of a
381 multiprocessor machine. If you say Y here, the kernel will run
382 on many, but not all, single processor machines. On a single
383 processor machine, the kernel will run faster if you say N
386 If you don't know what to do here, say N.
389 bool "Multi-core scheduler support"
392 Multi-core scheduler support improves the CPU scheduler's decision
393 making when dealing with multi-core CPU chips at a cost of slightly
394 increased overhead in some places. If unsure say N here.
397 bool "SMT scheduler support"
400 Improves the CPU scheduler's decision making when dealing with
401 MultiThreading at a cost of slightly increased overhead in some
402 places. If unsure say N here.
405 int "Maximum number of CPUs (2-64)"
408 # These have to remain sorted largest to smallest
412 bool "Support for hot-pluggable CPUs"
415 Say Y here to experiment with turning CPUs off and on. CPUs
416 can be controlled through /sys/devices/system/cpu.
418 source kernel/Kconfig.preempt
424 config ARCH_HAS_HOLES_MEMORYMODEL
425 def_bool y if SPARSEMEM
427 config ARCH_SPARSEMEM_ENABLE
429 select SPARSEMEM_VMEMMAP_ENABLE
431 config ARCH_SPARSEMEM_DEFAULT
432 def_bool ARCH_SPARSEMEM_ENABLE
434 config ARCH_SELECT_MEMORY_MODEL
435 def_bool ARCH_SPARSEMEM_ENABLE
437 config HAVE_ARCH_PFN_VALID
438 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
440 config HW_PERF_EVENTS
441 bool "Enable hardware performance counter support for perf events"
442 depends on PERF_EVENTS
445 Enable hardware performance counter support for perf events. If
446 disabled, perf events will use software events only.
448 config SYS_SUPPORTS_HUGETLBFS
451 config ARCH_WANT_GENERAL_HUGETLB
454 config ARCH_WANT_HUGE_PMD_SHARE
455 def_bool y if !ARM64_64K_PAGES
457 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
460 config ARCH_HAS_CACHE_LINE_SIZE
466 bool "Enable seccomp to safely compute untrusted bytecode"
468 This kernel feature is useful for number crunching applications
469 that may need to compute untrusted bytecode during their
470 execution. By using pipes or other transports made available to
471 the process as file descriptors supporting the read/write
472 syscalls, it's possible to isolate those applications in
473 their own address space using seccomp. Once seccomp is
474 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
475 and the task is only allowed to execute a few safe syscalls
476 defined by each seccomp mode.
483 bool "Xen guest support on ARM64"
484 depends on ARM64 && OF
487 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
489 config FORCE_MAX_ZONEORDER
491 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
494 menuconfig ARMV8_DEPRECATED
495 bool "Emulate deprecated/obsolete ARMv8 instructions"
498 Legacy software support may require certain instructions
499 that have been deprecated or obsoleted in the architecture.
501 Enable this config to enable selective emulation of these
509 bool "Emulate SWP/SWPB instructions"
511 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
512 they are always undefined. Say Y here to enable software
513 emulation of these instructions for userspace using LDXR/STXR.
515 In some older versions of glibc [<=2.8] SWP is used during futex
516 trylock() operations with the assumption that the code will not
517 be preempted. This invalid assumption may be more likely to fail
518 with SWP emulation enabled, leading to deadlock of the user
521 NOTE: when accessing uncached shared regions, LDXR/STXR rely
522 on an external transaction monitoring block called a global
523 monitor to maintain update atomicity. If your system does not
524 implement a global monitor, this option can cause programs that
525 perform SWP operations to uncached memory to deadlock.
529 config CP15_BARRIER_EMULATION
530 bool "Emulate CP15 Barrier instructions"
532 The CP15 barrier instructions - CP15ISB, CP15DSB, and
533 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
534 strongly recommended to use the ISB, DSB, and DMB
535 instructions instead.
537 Say Y here to enable software emulation of these
538 instructions for AArch32 userspace code. When this option is
539 enabled, CP15 barrier usage is traced which can help
540 identify software that needs updating.
551 string "Default kernel command string"
554 Provide a set of default command-line options at build time by
555 entering them here. As a minimum, you should specify the the
556 root device (e.g. root=/dev/nfs).
559 bool "Always use the default kernel command string"
561 Always use the default kernel command string, even if the boot
562 loader passes other arguments to the kernel.
563 This is useful if you cannot or don't want to change the
564 command-line options your boot loader passes to the kernel.
570 bool "UEFI runtime support"
571 depends on OF && !CPU_BIG_ENDIAN
574 select EFI_PARAMS_FROM_FDT
575 select EFI_RUNTIME_WRAPPERS
580 This option provides support for runtime services provided
581 by UEFI firmware (such as non-volatile variables, realtime
582 clock, and platform reset). A UEFI stub is also provided to
583 allow the kernel to be booted as an EFI application. This
584 is only useful on systems that have UEFI firmware.
587 bool "Enable support for SMBIOS (DMI) tables"
591 This enables SMBIOS/DMI feature for systems.
593 This option is only useful on systems that have UEFI firmware.
594 However, even with this option, the resultant kernel should
595 continue to boot on existing non-UEFI platforms.
599 menu "Userspace binary formats"
601 source "fs/Kconfig.binfmt"
604 bool "Kernel support for 32-bit EL0"
605 depends on !ARM64_64K_PAGES
606 select COMPAT_BINFMT_ELF
608 select OLD_SIGSUSPEND3
609 select COMPAT_OLD_SIGACTION
611 This option enables support for a 32-bit EL0 running under a 64-bit
612 kernel at EL1. AArch32-specific components such as system calls,
613 the user helper functions, VFP support and the ptrace interface are
614 handled appropriately by the kernel.
616 If you want to execute 32-bit userspace applications, say Y.
618 config SYSVIPC_COMPAT
620 depends on COMPAT && SYSVIPC
624 menu "Power management options"
626 source "kernel/power/Kconfig"
628 config ARCH_SUSPEND_POSSIBLE
631 config ARM64_CPU_SUSPEND
636 menu "CPU Power Management"
638 source "drivers/cpuidle/Kconfig"
640 source "drivers/cpufreq/Kconfig"
646 source "drivers/Kconfig"
648 source "drivers/firmware/Kconfig"
652 source "arch/arm64/kvm/Kconfig"
654 source "arch/arm64/Kconfig.debug"
656 source "security/Kconfig"
658 source "crypto/Kconfig"
660 source "arch/arm64/crypto/Kconfig"