arch/arm64/boot/dts/amlogic/meson-gx.dtsi

   1 /*
   2  * Copyright (c) 2016 Andreas Färber
   3  *
   4  * Copyright (c) 2016 BayLibre, SAS.
   5  * Author: Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * Copyright (c) 2016 Endless Computers, Inc.
   8  * Author: Carlo Caione <carlo@endlessm.com>
   9  *
  10  * This file is dual-licensed: you can use it either under the terms
  11  * of the GPL or the X11 license, at your option. Note that this dual
  12  * licensing only applies to this file, and not this project as a
  13  * whole.
  14  *
  15  *  a) This library is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of the
  18  *     License, or (at your option) any later version.
  19  *
  20  *     This library is distributed in the hope that it will be useful,
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively,
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use,
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 #include <dt-bindings/gpio/gpio.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/interrupt-controller/arm-gic.h>
  52
  53 / {
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         reserved-memory {
  59                 #address-cells = <2>;
  60                 #size-cells = <2>;
  61                 ranges;
  62
  63                 /* 16 MiB reserved for Hardware ROM Firmware */
  64                 hwrom_reserved: hwrom@0 {
  65                         reg = <0x0 0x0 0x0 0x1000000>;
  66                         no-map;
  67                 };
  68
  69                 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
  70                 secmon_reserved: secmon@10000000 {
  71                         reg = <0x0 0x10000000 0x0 0x200000>;
  72                         no-map;
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <0x2>;
  78                 #size-cells = <0x0>;
  79
  80                 cpu0: cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x0>;
  84                         enable-method = "psci";
  85                         next-level-cache = <&l2>;
  86                 };
  87
  88                 cpu1: cpu@1 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53", "arm,armv8";
  91                         reg = <0x0 0x1>;
  92                         enable-method = "psci";
  93                         next-level-cache = <&l2>;
  94                 };
  95
  96                 cpu2: cpu@2 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53", "arm,armv8";
  99                         reg = <0x0 0x2>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&l2>;
 102                 };
 103
 104                 cpu3: cpu@3 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a53", "arm,armv8";
 107                         reg = <0x0 0x3>;
 108                         enable-method = "psci";
 109                         next-level-cache = <&l2>;
 110                 };
 111
 112                 l2: l2-cache0 {
 113                         compatible = "cache";
 114                 };
 115         };
 116
 117         arm-pmu {
 118                 compatible = "arm,cortex-a53-pmu";
 119                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 123                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 124         };
 125
 126         psci {
 127                 compatible = "arm,psci-0.2";
 128                 method = "smc";
 129         };
 130
 131         timer {
 132                 compatible = "arm,armv8-timer";
 133                 interrupts = <GIC_PPI 13
 134                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 14
 136                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 137                              <GIC_PPI 11
 138                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 139                              <GIC_PPI 10
 140                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 141         };
 142
 143         xtal: xtal-clk {
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <24000000>;
 146                 clock-output-names = "xtal";
 147                 #clock-cells = <0>;
 148         };
 149
 150         firmware {
 151                 sm: secure-monitor {
 152                         compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
 153                 };
 154         };
 155
 156         efuse: efuse {
 157                 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
 158                 #address-cells = <1>;
 159                 #size-cells = <1>;
 160
 161                 sn: sn@14 {
 162                         reg = <0x14 0x10>;
 163                 };
 164
 165                 eth_mac: eth_mac@34 {
 166                         reg = <0x34 0x10>;
 167                 };
 168
 169                 bid: bid@46 {
 170                         reg = <0x46 0x30>;
 171                 };
 172         };
 173
 174         soc {
 175                 compatible = "simple-bus";
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 cbus: cbus@c1100000 {
 181                         compatible = "simple-bus";
 182                         reg = <0x0 0xc1100000 0x0 0x100000>;
 183                         #address-cells = <2>;
 184                         #size-cells = <2>;
 185                         ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
 186
 187                         reset: reset-controller@4404 {
 188                                 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
 189                                 reg = <0x0 0x04404 0x0 0x20>;
 190                                 #reset-cells = <1>;
 191                         };
 192
 193                         uart_A: serial@84c0 {
 194                                 compatible = "amlogic,meson-uart";
 195                                 reg = <0x0 0x84c0 0x0 0x14>;
 196                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 197                                 clocks = <&xtal>;
 198                                 status = "disabled";
 199                         };
 200
 201                         uart_B: serial@84dc {
 202                                 compatible = "amlogic,meson-uart";
 203                                 reg = <0x0 0x84dc 0x0 0x14>;
 204                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 205                                 clocks = <&xtal>;
 206                                 status = "disabled";
 207                         };
 208
 209                         i2c_A: i2c@8500 {
 210                                 compatible = "amlogic,meson-gxbb-i2c";
 211                                 reg = <0x0 0x08500 0x0 0x20>;
 212                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
 213                                 #address-cells = <1>;
 214                                 #size-cells = <0>;
 215                                 status = "disabled";
 216                         };
 217
 218                         pwm_ab: pwm@8550 {
 219                                 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
 220                                 reg = <0x0 0x08550 0x0 0x10>;
 221                                 #pwm-cells = <3>;
 222                                 status = "disabled";
 223                         };
 224
 225                         pwm_cd: pwm@8650 {
 226                                 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
 227                                 reg = <0x0 0x08650 0x0 0x10>;
 228                                 #pwm-cells = <3>;
 229                                 status = "disabled";
 230                         };
 231
 232                         pwm_ef: pwm@86c0 {
 233                                 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
 234                                 reg = <0x0 0x086c0 0x0 0x10>;
 235                                 #pwm-cells = <3>;
 236                                 status = "disabled";
 237                         };
 238
 239                         uart_C: serial@8700 {
 240                                 compatible = "amlogic,meson-uart";
 241                                 reg = <0x0 0x8700 0x0 0x14>;
 242                                 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
 243                                 clocks = <&xtal>;
 244                                 status = "disabled";
 245                         };
 246
 247                         i2c_B: i2c@87c0 {
 248                                 compatible = "amlogic,meson-gxbb-i2c";
 249                                 reg = <0x0 0x087c0 0x0 0x20>;
 250                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
 251                                 #address-cells = <1>;
 252                                 #size-cells = <0>;
 253                                 status = "disabled";
 254                         };
 255
 256                         i2c_C: i2c@87e0 {
 257                                 compatible = "amlogic,meson-gxbb-i2c";
 258                                 reg = <0x0 0x087e0 0x0 0x20>;
 259                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
 260                                 #address-cells = <1>;
 261                                 #size-cells = <0>;
 262                                 status = "disabled";
 263                         };
 264
 265                         watchdog@98d0 {
 266                                 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
 267                                 reg = <0x0 0x098d0 0x0 0x10>;
 268                                 clocks = <&xtal>;
 269                         };
 270                 };
 271
 272                 gic: interrupt-controller@c4301000 {
 273                         compatible = "arm,gic-400";
 274                         reg = <0x0 0xc4301000 0 0x1000>,
 275                               <0x0 0xc4302000 0 0x2000>,
 276                               <0x0 0xc4304000 0 0x2000>,
 277                               <0x0 0xc4306000 0 0x2000>;
 278                         interrupt-controller;
 279                         interrupts = <GIC_PPI 9
 280                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 281                         #interrupt-cells = <3>;
 282                         #address-cells = <0>;
 283                 };
 284
 285                 aobus: aobus@c8100000 {
 286                         compatible = "simple-bus";
 287                         reg = <0x0 0xc8100000 0x0 0x100000>;
 288                         #address-cells = <2>;
 289                         #size-cells = <2>;
 290                         ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
 291
 292                         uart_AO: serial@4c0 {
 293                                 compatible = "amlogic,meson-uart";
 294                                 reg = <0x0 0x004c0 0x0 0x14>;
 295                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
 296                                 clocks = <&xtal>;
 297                                 status = "disabled";
 298                         };
 299
 300                         ir: ir@580 {
 301                                 compatible = "amlogic,meson-gxbb-ir";
 302                                 reg = <0x0 0x00580 0x0 0x40>;
 303                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
 304                                 status = "disabled";
 305                         };
 306                 };
 307
 308                 periphs: periphs@c8834000 {
 309                         compatible = "simple-bus";
 310                         reg = <0x0 0xc8834000 0x0 0x2000>;
 311                         #address-cells = <2>;
 312                         #size-cells = <2>;
 313                         ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
 314
 315                         rng {
 316                                 compatible = "amlogic,meson-rng";
 317                                 reg = <0x0 0x0 0x0 0x4>;
 318                         };
 319                 };
 320
 321
 322                 hiubus: hiubus@c883c000 {
 323                         compatible = "simple-bus";
 324                         reg = <0x0 0xc883c000 0x0 0x2000>;
 325                         #address-cells = <2>;
 326                         #size-cells = <2>;
 327                         ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
 328
 329                         mailbox: mailbox@404 {
 330                                 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 331                                 reg = <0 0x404 0 0x4c>;
 332                                 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
 333                                              <0 209 IRQ_TYPE_EDGE_RISING>,
 334                                              <0 210 IRQ_TYPE_EDGE_RISING>;
 335                                 #mbox-cells = <1>;
 336                         };
 337                 };
 338
 339                 ethmac: ethernet@c9410000 {
 340                         compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
 341                         reg = <0x0 0xc9410000 0x0 0x10000
 342                                0x0 0xc8834540 0x0 0x4>;
 343                         interrupts = <0 8 1>;
 344                         interrupt-names = "macirq";
 345                         phy-mode = "rgmii";
 346                         status = "disabled";
 347                 };
 348
 349                 apb: apb@d0000000 {
 350                         compatible = "simple-bus";
 351                         reg = <0x0 0xd0000000 0x0 0x200000>;
 352                         #address-cells = <2>;
 353                         #size-cells = <2>;
 354                         ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
 355
 356                         sd_emmc_a: mmc@70000 {
 357                                 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
 358                                 reg = <0x0 0x70000 0x0 0x2000>;
 359                                 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
 360                                 status = "disabled";
 361                         };
 362
 363                         sd_emmc_b: mmc@72000 {
 364                                 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
 365                                 reg = <0x0 0x72000 0x0 0x2000>;
 366                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
 367                                 status = "disabled";
 368                         };
 369
 370                         sd_emmc_c: mmc@74000 {
 371                                 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
 372                                 reg = <0x0 0x74000 0x0 0x2000>;
 373                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
 374                                 status = "disabled";
 375                         };
 376                 };
 377
 378                 vpu: vpu@d0100000 {
 379                         compatible = "amlogic,meson-gx-vpu";
 380                         reg = <0x0 0xd0100000 0x0 0x100000>,
 381                               <0x0 0xc883c000 0x0 0x1000>,
 382                               <0x0 0xc8838000 0x0 0x1000>;
 383                         reg-names = "vpu", "hhi", "dmc";
 384                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387
 388                         /* CVBS VDAC output port */
 389                         cvbs_vdac_port: port@0 {
 390                                 reg = <0>;
 391                         };
 392                 };
 393         };
 394 };