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arm64: dts: meson-gx: add aiu support
[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / boot / dts / amlogic / meson-gx.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2016 Andreas Färber
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * Copyright (c) 2016 Endless Computers, Inc.
9 * Author: Carlo Caione <carlo@endlessm.com>
10 */
11
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/thermal/thermal.h>
16
17 / {
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 reserved-memory {
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges;
26
27 /* 16 MiB reserved for Hardware ROM Firmware */
28 hwrom_reserved: hwrom@0 {
29 reg = <0x0 0x0 0x0 0x1000000>;
30 no-map;
31 };
32
33 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
34 secmon_reserved: secmon@10000000 {
35 reg = <0x0 0x10000000 0x0 0x200000>;
36 no-map;
37 };
38
39 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
40 secmon_reserved_alt: secmon@5000000 {
41 reg = <0x0 0x05000000 0x0 0x300000>;
42 no-map;
43 };
44
45 linux,cma {
46 compatible = "shared-dma-pool";
47 reusable;
48 size = <0x0 0x10000000>;
49 alignment = <0x0 0x400000>;
50 linux,cma-default;
51 };
52 };
53
54 chosen {
55 #address-cells = <2>;
56 #size-cells = <2>;
57 ranges;
58
59 simplefb_cvbs: framebuffer-cvbs {
60 compatible = "amlogic,simple-framebuffer",
61 "simple-framebuffer";
62 amlogic,pipeline = "vpu-cvbs";
63 power-domains = <&pwrc_vpu>;
64 status = "disabled";
65 };
66
67 simplefb_hdmi: framebuffer-hdmi {
68 compatible = "amlogic,simple-framebuffer",
69 "simple-framebuffer";
70 amlogic,pipeline = "vpu-hdmi";
71 power-domains = <&pwrc_vpu>;
72 status = "disabled";
73 };
74 };
75
76 cpus {
77 #address-cells = <0x2>;
78 #size-cells = <0x0>;
79
80 cpu0: cpu@0 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a53";
83 reg = <0x0 0x0>;
84 enable-method = "psci";
85 next-level-cache = <&l2>;
86 clocks = <&scpi_dvfs 0>;
87 #cooling-cells = <2>;
88 };
89
90 cpu1: cpu@1 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a53";
93 reg = <0x0 0x1>;
94 enable-method = "psci";
95 next-level-cache = <&l2>;
96 clocks = <&scpi_dvfs 0>;
97 #cooling-cells = <2>;
98 };
99
100 cpu2: cpu@2 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x0 0x2>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 clocks = <&scpi_dvfs 0>;
107 #cooling-cells = <2>;
108 };
109
110 cpu3: cpu@3 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a53";
113 reg = <0x0 0x3>;
114 enable-method = "psci";
115 next-level-cache = <&l2>;
116 clocks = <&scpi_dvfs 0>;
117 #cooling-cells = <2>;
118 };
119
120 l2: l2-cache0 {
121 compatible = "cache";
122 };
123 };
124
125 thermal-zones {
126 cpu-thermal {
127 polling-delay-passive = <250>; /* milliseconds */
128 polling-delay = <1000>; /* milliseconds */
129
130 thermal-sensors = <&scpi_sensors 0>;
131
132 trips {
133 cpu_passive: cpu-passive {
134 temperature = <80000>; /* millicelsius */
135 hysteresis = <2000>; /* millicelsius */
136 type = "passive";
137 };
138
139 cpu_hot: cpu-hot {
140 temperature = <90000>; /* millicelsius */
141 hysteresis = <2000>; /* millicelsius */
142 type = "hot";
143 };
144
145 cpu_critical: cpu-critical {
146 temperature = <110000>; /* millicelsius */
147 hysteresis = <2000>; /* millicelsius */
148 type = "critical";
149 };
150 };
151
152 cpu_cooling_maps: cooling-maps {
153 map0 {
154 trip = <&cpu_passive>;
155 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
157 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
158 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
159 };
160
161 map1 {
162 trip = <&cpu_hot>;
163 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
164 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
165 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
166 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
167 };
168 };
169 };
170 };
171
172 arm-pmu {
173 compatible = "arm,cortex-a53-pmu";
174 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
179 };
180
181 psci {
182 compatible = "arm,psci-0.2";
183 method = "smc";
184 };
185
186 timer {
187 compatible = "arm,armv8-timer";
188 interrupts = <GIC_PPI 13
189 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
190 <GIC_PPI 14
191 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
192 <GIC_PPI 11
193 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
194 <GIC_PPI 10
195 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
196 };
197
198 xtal: xtal-clk {
199 compatible = "fixed-clock";
200 clock-frequency = <24000000>;
201 clock-output-names = "xtal";
202 #clock-cells = <0>;
203 };
204
205 firmware {
206 sm: secure-monitor {
207 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
208 };
209 };
210
211 efuse: efuse {
212 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
213 #address-cells = <1>;
214 #size-cells = <1>;
215 read-only;
216 secure-monitor = <&sm>;
217
218 sn: sn@14 {
219 reg = <0x14 0x10>;
220 };
221
222 eth_mac: eth_mac@34 {
223 reg = <0x34 0x10>;
224 };
225
226 bid: bid@46 {
227 reg = <0x46 0x30>;
228 };
229 };
230
231 scpi {
232 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
233 mboxes = <&mailbox 1 &mailbox 2>;
234 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
235
236 scpi_clocks: clocks {
237 compatible = "arm,scpi-clocks";
238
239 scpi_dvfs: scpi_clocks@0 {
240 compatible = "arm,scpi-dvfs-clocks";
241 #clock-cells = <1>;
242 clock-indices = <0>;
243 clock-output-names = "vcpu";
244 };
245 };
246
247 scpi_sensors: sensors {
248 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
249 #thermal-sensor-cells = <1>;
250 };
251 };
252
253 soc {
254 compatible = "simple-bus";
255 #address-cells = <2>;
256 #size-cells = <2>;
257 ranges;
258
259 cbus: bus@c1100000 {
260 compatible = "simple-bus";
261 reg = <0x0 0xc1100000 0x0 0x100000>;
262 #address-cells = <2>;
263 #size-cells = <2>;
264 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
265
266 gpio_intc: interrupt-controller@9880 {
267 compatible = "amlogic,meson-gpio-intc";
268 reg = <0x0 0x9880 0x0 0x10>;
269 interrupt-controller;
270 #interrupt-cells = <2>;
271 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
272 status = "disabled";
273 };
274
275 reset: reset-controller@4404 {
276 compatible = "amlogic,meson-gxbb-reset";
277 reg = <0x0 0x04404 0x0 0x9c>;
278 #reset-cells = <1>;
279 };
280
281 aiu: audio-controller@5400 {
282 compatible = "amlogic,aiu";
283 #sound-dai-cells = <2>;
284 sound-name-prefix = "AIU";
285 reg = <0x0 0x5400 0x0 0x2ac>;
286 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
287 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
288 interrupt-names = "i2s", "spdif";
289 status = "disabled";
290 };
291
292 uart_A: serial@84c0 {
293 compatible = "amlogic,meson-gx-uart";
294 reg = <0x0 0x84c0 0x0 0x18>;
295 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
296 status = "disabled";
297 };
298
299 uart_B: serial@84dc {
300 compatible = "amlogic,meson-gx-uart";
301 reg = <0x0 0x84dc 0x0 0x18>;
302 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
303 status = "disabled";
304 };
305
306 i2c_A: i2c@8500 {
307 compatible = "amlogic,meson-gxbb-i2c";
308 reg = <0x0 0x08500 0x0 0x20>;
309 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 pwm_ab: pwm@8550 {
316 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
317 reg = <0x0 0x08550 0x0 0x10>;
318 #pwm-cells = <3>;
319 status = "disabled";
320 };
321
322 pwm_cd: pwm@8650 {
323 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
324 reg = <0x0 0x08650 0x0 0x10>;
325 #pwm-cells = <3>;
326 status = "disabled";
327 };
328
329 saradc: adc@8680 {
330 compatible = "amlogic,meson-saradc";
331 reg = <0x0 0x8680 0x0 0x34>;
332 #io-channel-cells = <1>;
333 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
334 status = "disabled";
335 };
336
337 pwm_ef: pwm@86c0 {
338 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
339 reg = <0x0 0x086c0 0x0 0x10>;
340 #pwm-cells = <3>;
341 status = "disabled";
342 };
343
344 uart_C: serial@8700 {
345 compatible = "amlogic,meson-gx-uart";
346 reg = <0x0 0x8700 0x0 0x18>;
347 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
348 status = "disabled";
349 };
350
351 clock-measure@8758 {
352 compatible = "amlogic,meson-gx-clk-measure";
353 reg = <0x0 0x8758 0x0 0x10>;
354 };
355
356 i2c_B: i2c@87c0 {
357 compatible = "amlogic,meson-gxbb-i2c";
358 reg = <0x0 0x087c0 0x0 0x20>;
359 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 status = "disabled";
363 };
364
365 i2c_C: i2c@87e0 {
366 compatible = "amlogic,meson-gxbb-i2c";
367 reg = <0x0 0x087e0 0x0 0x20>;
368 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372 };
373
374 spicc: spi@8d80 {
375 compatible = "amlogic,meson-gx-spicc";
376 reg = <0x0 0x08d80 0x0 0x80>;
377 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 status = "disabled";
381 };
382
383 spifc: spi@8c80 {
384 compatible = "amlogic,meson-gxbb-spifc";
385 reg = <0x0 0x08c80 0x0 0x80>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
391 watchdog@98d0 {
392 compatible = "amlogic,meson-gxbb-wdt";
393 reg = <0x0 0x098d0 0x0 0x10>;
394 clocks = <&xtal>;
395 };
396 };
397
398 gic: interrupt-controller@c4301000 {
399 compatible = "arm,gic-400";
400 reg = <0x0 0xc4301000 0 0x1000>,
401 <0x0 0xc4302000 0 0x2000>,
402 <0x0 0xc4304000 0 0x2000>,
403 <0x0 0xc4306000 0 0x2000>;
404 interrupt-controller;
405 interrupts = <GIC_PPI 9
406 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
407 #interrupt-cells = <3>;
408 #address-cells = <0>;
409 };
410
411 sram: sram@c8000000 {
412 compatible = "mmio-sram";
413 reg = <0x0 0xc8000000 0x0 0x14000>;
414
415 #address-cells = <1>;
416 #size-cells = <1>;
417 ranges = <0 0x0 0xc8000000 0x14000>;
418
419 cpu_scp_lpri: scp-sram@0 {
420 compatible = "amlogic,meson-gxbb-scp-shmem";
421 reg = <0x13000 0x400>;
422 };
423
424 cpu_scp_hpri: scp-sram@200 {
425 compatible = "amlogic,meson-gxbb-scp-shmem";
426 reg = <0x13400 0x400>;
427 };
428 };
429
430 aobus: bus@c8100000 {
431 compatible = "simple-bus";
432 reg = <0x0 0xc8100000 0x0 0x100000>;
433 #address-cells = <2>;
434 #size-cells = <2>;
435 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
436
437 sysctrl_AO: sys-ctrl@0 {
438 compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
439 reg = <0x0 0x0 0x0 0x100>;
440
441 pwrc_vpu: power-controller-vpu {
442 compatible = "amlogic,meson-gx-pwrc-vpu";
443 #power-domain-cells = <0>;
444 amlogic,hhi-sysctrl = <&sysctrl>;
445 };
446
447 clkc_AO: clock-controller {
448 compatible = "amlogic,meson-gx-aoclkc";
449 #clock-cells = <1>;
450 #reset-cells = <1>;
451 };
452 };
453
454 cec_AO: cec@100 {
455 compatible = "amlogic,meson-gx-ao-cec";
456 reg = <0x0 0x00100 0x0 0x14>;
457 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
458 status = "disabled";
459 };
460
461 sec_AO: ao-secure@140 {
462 compatible = "amlogic,meson-gx-ao-secure", "syscon";
463 reg = <0x0 0x140 0x0 0x140>;
464 amlogic,has-chip-id;
465 };
466
467 uart_AO: serial@4c0 {
468 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
469 reg = <0x0 0x004c0 0x0 0x18>;
470 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
471 status = "disabled";
472 };
473
474 uart_AO_B: serial@4e0 {
475 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
476 reg = <0x0 0x004e0 0x0 0x18>;
477 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
478 status = "disabled";
479 };
480
481 i2c_AO: i2c@500 {
482 compatible = "amlogic,meson-gxbb-i2c";
483 reg = <0x0 0x500 0x0 0x20>;
484 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 status = "disabled";
488 };
489
490 pwm_AO_ab: pwm@550 {
491 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
492 reg = <0x0 0x00550 0x0 0x10>;
493 #pwm-cells = <3>;
494 status = "disabled";
495 };
496
497 ir: ir@580 {
498 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
499 reg = <0x0 0x00580 0x0 0x40>;
500 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
501 status = "disabled";
502 };
503 };
504
505 vdec: video-codec@c8820000 {
506 compatible = "amlogic,gx-vdec";
507 reg = <0x0 0xc8820000 0x0 0x10000>,
508 <0x0 0xc110a580 0x0 0xe4>;
509 reg-names = "dos", "esparser";
510
511 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
512 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
513 interrupt-names = "vdec", "esparser";
514
515 amlogic,ao-sysctrl = <&sysctrl_AO>;
516 amlogic,canvas = <&canvas>;
517 };
518
519 periphs: bus@c8834000 {
520 compatible = "simple-bus";
521 reg = <0x0 0xc8834000 0x0 0x2000>;
522 #address-cells = <2>;
523 #size-cells = <2>;
524 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
525
526 hwrng: rng {
527 compatible = "amlogic,meson-rng";
528 reg = <0x0 0x0 0x0 0x4>;
529 };
530 };
531
532 dmcbus: bus@c8838000 {
533 compatible = "simple-bus";
534 reg = <0x0 0xc8838000 0x0 0x400>;
535 #address-cells = <2>;
536 #size-cells = <2>;
537 ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
538
539 canvas: video-lut@48 {
540 compatible = "amlogic,canvas";
541 reg = <0x0 0x48 0x0 0x14>;
542 };
543 };
544
545 hiubus: bus@c883c000 {
546 compatible = "simple-bus";
547 reg = <0x0 0xc883c000 0x0 0x2000>;
548 #address-cells = <2>;
549 #size-cells = <2>;
550 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
551
552 sysctrl: system-controller@0 {
553 compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
554 reg = <0 0 0 0x400>;
555 };
556
557 mailbox: mailbox@404 {
558 compatible = "amlogic,meson-gxbb-mhu";
559 reg = <0 0x404 0 0x4c>;
560 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
561 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
562 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
563 #mbox-cells = <1>;
564 };
565 };
566
567 ethmac: ethernet@c9410000 {
568 compatible = "amlogic,meson-gxbb-dwmac",
569 "snps,dwmac-3.70a",
570 "snps,dwmac";
571 reg = <0x0 0xc9410000 0x0 0x10000>,
572 <0x0 0xc8834540 0x0 0x4>;
573 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "macirq";
575 rx-fifo-depth = <4096>;
576 tx-fifo-depth = <2048>;
577 status = "disabled";
578 };
579
580 apb: apb@d0000000 {
581 compatible = "simple-bus";
582 reg = <0x0 0xd0000000 0x0 0x200000>;
583 #address-cells = <2>;
584 #size-cells = <2>;
585 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
586
587 sd_emmc_a: mmc@70000 {
588 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
589 reg = <0x0 0x70000 0x0 0x800>;
590 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
591 status = "disabled";
592 };
593
594 sd_emmc_b: mmc@72000 {
595 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
596 reg = <0x0 0x72000 0x0 0x800>;
597 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
598 status = "disabled";
599 };
600
601 sd_emmc_c: mmc@74000 {
602 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
603 reg = <0x0 0x74000 0x0 0x800>;
604 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
605 status = "disabled";
606 };
607 };
608
609 vpu: vpu@d0100000 {
610 compatible = "amlogic,meson-gx-vpu";
611 reg = <0x0 0xd0100000 0x0 0x100000>,
612 <0x0 0xc883c000 0x0 0x1000>;
613 reg-names = "vpu", "hhi";
614 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
615 #address-cells = <1>;
616 #size-cells = <0>;
617 amlogic,canvas = <&canvas>;
618
619 /* CVBS VDAC output port */
620 cvbs_vdac_port: port@0 {
621 reg = <0>;
622 };
623
624 /* HDMI-TX output port */
625 hdmi_tx_port: port@1 {
626 reg = <1>;
627
628 hdmi_tx_out: endpoint {
629 remote-endpoint = <&hdmi_tx_in>;
630 };
631 };
632 };
633
634 hdmi_tx: hdmi-tx@c883a000 {
635 compatible = "amlogic,meson-gx-dw-hdmi";
636 reg = <0x0 0xc883a000 0x0 0x1c>;
637 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
638 #address-cells = <1>;
639 #size-cells = <0>;
640 #sound-dai-cells = <0>;
641 sound-name-prefix = "HDMITX";
642 status = "disabled";
643
644 /* VPU VENC Input */
645 hdmi_tx_venc_port: port@0 {
646 reg = <0>;
647
648 hdmi_tx_in: endpoint {
649 remote-endpoint = <&hdmi_tx_out>;
650 };
651 };
652
653 /* TMDS Output */
654 hdmi_tx_tmds_port: port@1 {
655 reg = <1>;
656 };
657 };
658 };
659 };
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