]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
Merge remote-tracking branch 'asoc/topic/pcm512x' into asoc-next
[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / amlogic / meson-gxl.dtsi
1 /*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44 #include "meson-gx.dtsi"
45 #include <dt-bindings/clock/gxbb-clkc.h>
46 #include <dt-bindings/clock/gxbb-aoclkc.h>
47 #include <dt-bindings/gpio/meson-gxl-gpio.h>
48 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
49
50 / {
51 compatible = "amlogic,meson-gxl";
52
53 reserved-memory {
54 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
55 secmon_reserved_alt: secmon@5000000 {
56 reg = <0x0 0x05000000 0x0 0x300000>;
57 no-map;
58 };
59 };
60 };
61
62 &ethmac {
63 reg = <0x0 0xc9410000 0x0 0x10000
64 0x0 0xc8834540 0x0 0x4>;
65
66 clocks = <&clkc CLKID_ETH>,
67 <&clkc CLKID_FCLK_DIV2>,
68 <&clkc CLKID_MPLL2>;
69 clock-names = "stmmaceth", "clkin0", "clkin1";
70
71 mdio0: mdio {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "snps,dwmac-mdio";
75 };
76 };
77
78 &aobus {
79 pinctrl_aobus: pinctrl@14 {
80 compatible = "amlogic,meson-gxl-aobus-pinctrl";
81 #address-cells = <2>;
82 #size-cells = <2>;
83 ranges;
84
85 gpio_ao: bank@14 {
86 reg = <0x0 0x00014 0x0 0x8>,
87 <0x0 0x0002c 0x0 0x4>,
88 <0x0 0x00024 0x0 0x8>;
89 reg-names = "mux", "pull", "gpio";
90 gpio-controller;
91 #gpio-cells = <2>;
92 gpio-ranges = <&pinctrl_aobus 0 0 14>;
93 };
94
95 uart_ao_a_pins: uart_ao_a {
96 mux {
97 groups = "uart_tx_ao_a", "uart_rx_ao_a";
98 function = "uart_ao";
99 };
100 };
101
102 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
103 mux {
104 groups = "uart_cts_ao_a",
105 "uart_rts_ao_a";
106 function = "uart_ao";
107 };
108 };
109
110 uart_ao_b_pins: uart_ao_b {
111 mux {
112 groups = "uart_tx_ao_b", "uart_rx_ao_b";
113 function = "uart_ao_b";
114 };
115 };
116
117 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
118 mux {
119 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
120 function = "uart_ao_b";
121 };
122 };
123
124 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
125 mux {
126 groups = "uart_cts_ao_b",
127 "uart_rts_ao_b";
128 function = "uart_ao_b";
129 };
130 };
131
132 remote_input_ao_pins: remote_input_ao {
133 mux {
134 groups = "remote_input_ao";
135 function = "remote_input_ao";
136 };
137 };
138
139 i2c_ao_pins: i2c_ao {
140 mux {
141 groups = "i2c_sck_ao",
142 "i2c_sda_ao";
143 function = "i2c_ao";
144 };
145 };
146
147 pwm_ao_a_3_pins: pwm_ao_a_3 {
148 mux {
149 groups = "pwm_ao_a_3";
150 function = "pwm_ao_a";
151 };
152 };
153
154 pwm_ao_a_8_pins: pwm_ao_a_8 {
155 mux {
156 groups = "pwm_ao_a_8";
157 function = "pwm_ao_a";
158 };
159 };
160
161 pwm_ao_b_pins: pwm_ao_b {
162 mux {
163 groups = "pwm_ao_b";
164 function = "pwm_ao_b";
165 };
166 };
167
168 pwm_ao_b_6_pins: pwm_ao_b_6 {
169 mux {
170 groups = "pwm_ao_b_6";
171 function = "pwm_ao_b";
172 };
173 };
174
175 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
176 mux {
177 groups = "i2s_out_ch23_ao";
178 function = "i2s_out_ao";
179 };
180 };
181
182 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
183 mux {
184 groups = "i2s_out_ch45_ao";
185 function = "i2s_out_ao";
186 };
187 };
188
189 spdif_out_ao_6_pins: spdif_out_ao_6 {
190 mux {
191 groups = "spdif_out_ao_6";
192 function = "spdif_out_ao";
193 };
194 };
195
196 spdif_out_ao_9_pins: spdif_out_ao_9 {
197 mux {
198 groups = "spdif_out_ao_9";
199 function = "spdif_out_ao";
200 };
201 };
202
203 ao_cec_pins: ao_cec {
204 mux {
205 groups = "ao_cec";
206 function = "cec_ao";
207 };
208 };
209
210 ee_cec_pins: ee_cec {
211 mux {
212 groups = "ee_cec";
213 function = "cec_ao";
214 };
215 };
216 };
217 };
218
219 &cec_AO {
220 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
221 clock-names = "core";
222 };
223
224 &clkc_AO {
225 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
226 };
227
228 &gpio_intc {
229 compatible = "amlogic,meson-gpio-intc",
230 "amlogic,meson-gxl-gpio-intc";
231 status = "okay";
232 };
233
234 &hdmi_tx {
235 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
236 resets = <&reset RESET_HDMITX_CAPB3>,
237 <&reset RESET_HDMI_SYSTEM_RESET>,
238 <&reset RESET_HDMI_TX>;
239 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
240 clocks = <&clkc CLKID_HDMI_PCLK>,
241 <&clkc CLKID_CLK81>,
242 <&clkc CLKID_GCLK_VENCI_INT0>;
243 clock-names = "isfr", "iahb", "venci";
244 };
245
246 &hiubus {
247 clkc: clock-controller@0 {
248 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
249 #clock-cells = <1>;
250 reg = <0x0 0x0 0x0 0x3db>;
251 };
252 };
253
254 &i2c_A {
255 clocks = <&clkc CLKID_I2C>;
256 };
257
258 &i2c_AO {
259 clocks = <&clkc CLKID_AO_I2C>;
260 };
261
262 &i2c_B {
263 clocks = <&clkc CLKID_I2C>;
264 };
265
266 &i2c_C {
267 clocks = <&clkc CLKID_I2C>;
268 };
269
270 &periphs {
271 pinctrl_periphs: pinctrl@4b0 {
272 compatible = "amlogic,meson-gxl-periphs-pinctrl";
273 #address-cells = <2>;
274 #size-cells = <2>;
275 ranges;
276
277 gpio: bank@4b0 {
278 reg = <0x0 0x004b0 0x0 0x28>,
279 <0x0 0x004e8 0x0 0x14>,
280 <0x0 0x00520 0x0 0x14>,
281 <0x0 0x00430 0x0 0x40>;
282 reg-names = "mux", "pull", "pull-enable", "gpio";
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = <&pinctrl_periphs 0 0 100>;
286 };
287
288 emmc_pins: emmc {
289 mux {
290 groups = "emmc_nand_d07",
291 "emmc_cmd",
292 "emmc_clk";
293 function = "emmc";
294 };
295 };
296
297 emmc_ds_pins: emmc-ds {
298 mux {
299 groups = "emmc_ds";
300 function = "emmc";
301 };
302 };
303
304 emmc_clk_gate_pins: emmc_clk_gate {
305 mux {
306 groups = "BOOT_8";
307 function = "gpio_periphs";
308 };
309 cfg-pull-down {
310 pins = "BOOT_8";
311 bias-pull-down;
312 };
313 };
314
315 nor_pins: nor {
316 mux {
317 groups = "nor_d",
318 "nor_q",
319 "nor_c",
320 "nor_cs";
321 function = "nor";
322 };
323 };
324
325 spi_pins: spi {
326 mux {
327 groups = "spi_miso",
328 "spi_mosi",
329 "spi_sclk";
330 function = "spi";
331 };
332 };
333
334 spi_ss0_pins: spi-ss0 {
335 mux {
336 groups = "spi_ss0";
337 function = "spi";
338 };
339 };
340
341 sdcard_pins: sdcard {
342 mux {
343 groups = "sdcard_d0",
344 "sdcard_d1",
345 "sdcard_d2",
346 "sdcard_d3",
347 "sdcard_cmd",
348 "sdcard_clk";
349 function = "sdcard";
350 };
351 };
352
353 sdcard_clk_gate_pins: sdcard_clk_gate {
354 mux {
355 groups = "CARD_2";
356 function = "gpio_periphs";
357 };
358 cfg-pull-down {
359 pins = "CARD_2";
360 bias-pull-down;
361 };
362 };
363
364 sdio_pins: sdio {
365 mux {
366 groups = "sdio_d0",
367 "sdio_d1",
368 "sdio_d2",
369 "sdio_d3",
370 "sdio_cmd",
371 "sdio_clk";
372 function = "sdio";
373 };
374 };
375
376 sdio_clk_gate_pins: sdio_clk_gate {
377 mux {
378 groups = "GPIOX_4";
379 function = "gpio_periphs";
380 };
381 cfg-pull-down {
382 pins = "GPIOX_4";
383 bias-pull-down;
384 };
385 };
386
387 sdio_irq_pins: sdio_irq {
388 mux {
389 groups = "sdio_irq";
390 function = "sdio";
391 };
392 };
393
394 uart_a_pins: uart_a {
395 mux {
396 groups = "uart_tx_a",
397 "uart_rx_a";
398 function = "uart_a";
399 };
400 };
401
402 uart_a_cts_rts_pins: uart_a_cts_rts {
403 mux {
404 groups = "uart_cts_a",
405 "uart_rts_a";
406 function = "uart_a";
407 };
408 };
409
410 uart_b_pins: uart_b {
411 mux {
412 groups = "uart_tx_b",
413 "uart_rx_b";
414 function = "uart_b";
415 };
416 };
417
418 uart_b_cts_rts_pins: uart_b_cts_rts {
419 mux {
420 groups = "uart_cts_b",
421 "uart_rts_b";
422 function = "uart_b";
423 };
424 };
425
426 uart_c_pins: uart_c {
427 mux {
428 groups = "uart_tx_c",
429 "uart_rx_c";
430 function = "uart_c";
431 };
432 };
433
434 uart_c_cts_rts_pins: uart_c_cts_rts {
435 mux {
436 groups = "uart_cts_c",
437 "uart_rts_c";
438 function = "uart_c";
439 };
440 };
441
442 i2c_a_pins: i2c_a {
443 mux {
444 groups = "i2c_sck_a",
445 "i2c_sda_a";
446 function = "i2c_a";
447 };
448 };
449
450 i2c_b_pins: i2c_b {
451 mux {
452 groups = "i2c_sck_b",
453 "i2c_sda_b";
454 function = "i2c_b";
455 };
456 };
457
458 i2c_c_pins: i2c_c {
459 mux {
460 groups = "i2c_sck_c",
461 "i2c_sda_c";
462 function = "i2c_c";
463 };
464 };
465
466 eth_pins: eth_c {
467 mux {
468 groups = "eth_mdio",
469 "eth_mdc",
470 "eth_clk_rx_clk",
471 "eth_rx_dv",
472 "eth_rxd0",
473 "eth_rxd1",
474 "eth_rxd2",
475 "eth_rxd3",
476 "eth_rgmii_tx_clk",
477 "eth_tx_en",
478 "eth_txd0",
479 "eth_txd1",
480 "eth_txd2",
481 "eth_txd3";
482 function = "eth";
483 };
484 };
485
486 eth_link_led_pins: eth_link_led {
487 mux {
488 groups = "eth_link_led";
489 function = "eth_led";
490 };
491 };
492
493 eth_act_led_pins: eth_act_led {
494 mux {
495 groups = "eth_act_led";
496 function = "eth_led";
497 };
498 };
499
500 pwm_a_pins: pwm_a {
501 mux {
502 groups = "pwm_a";
503 function = "pwm_a";
504 };
505 };
506
507 pwm_b_pins: pwm_b {
508 mux {
509 groups = "pwm_b";
510 function = "pwm_b";
511 };
512 };
513
514 pwm_c_pins: pwm_c {
515 mux {
516 groups = "pwm_c";
517 function = "pwm_c";
518 };
519 };
520
521 pwm_d_pins: pwm_d {
522 mux {
523 groups = "pwm_d";
524 function = "pwm_d";
525 };
526 };
527
528 pwm_e_pins: pwm_e {
529 mux {
530 groups = "pwm_e";
531 function = "pwm_e";
532 };
533 };
534
535 pwm_f_clk_pins: pwm_f_clk {
536 mux {
537 groups = "pwm_f_clk";
538 function = "pwm_f";
539 };
540 };
541
542 pwm_f_x_pins: pwm_f_x {
543 mux {
544 groups = "pwm_f_x";
545 function = "pwm_f";
546 };
547 };
548
549 hdmi_hpd_pins: hdmi_hpd {
550 mux {
551 groups = "hdmi_hpd";
552 function = "hdmi_hpd";
553 };
554 };
555
556 hdmi_i2c_pins: hdmi_i2c {
557 mux {
558 groups = "hdmi_sda", "hdmi_scl";
559 function = "hdmi_i2c";
560 };
561 };
562
563 i2s_am_clk_pins: i2s_am_clk {
564 mux {
565 groups = "i2s_am_clk";
566 function = "i2s_out";
567 };
568 };
569
570 i2s_out_ao_clk_pins: i2s_out_ao_clk {
571 mux {
572 groups = "i2s_out_ao_clk";
573 function = "i2s_out";
574 };
575 };
576
577 i2s_out_lr_clk_pins: i2s_out_lr_clk {
578 mux {
579 groups = "i2s_out_lr_clk";
580 function = "i2s_out";
581 };
582 };
583
584 i2s_out_ch01_pins: i2s_out_ch01 {
585 mux {
586 groups = "i2s_out_ch01";
587 function = "i2s_out";
588 };
589 };
590 i2sout_ch23_z_pins: i2sout_ch23_z {
591 mux {
592 groups = "i2sout_ch23_z";
593 function = "i2s_out";
594 };
595 };
596
597 i2sout_ch45_z_pins: i2sout_ch45_z {
598 mux {
599 groups = "i2sout_ch45_z";
600 function = "i2s_out";
601 };
602 };
603
604 i2sout_ch67_z_pins: i2sout_ch67_z {
605 mux {
606 groups = "i2sout_ch67_z";
607 function = "i2s_out";
608 };
609 };
610
611 spdif_out_h_pins: spdif_out_ao_h {
612 mux {
613 groups = "spdif_out_h";
614 function = "spdif_out";
615 };
616 };
617 };
618
619 eth-phy-mux {
620 compatible = "mdio-mux-mmioreg", "mdio-mux";
621 #address-cells = <1>;
622 #size-cells = <0>;
623 reg = <0x0 0x55c 0x0 0x4>;
624 mux-mask = <0xffffffff>;
625 mdio-parent-bus = <&mdio0>;
626
627 internal_mdio: mdio@e40908ff {
628 reg = <0xe40908ff>;
629 #address-cells = <1>;
630 #size-cells = <0>;
631
632 internal_phy: ethernet-phy@8 {
633 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
634 reg = <8>;
635 max-speed = <100>;
636 };
637 };
638
639 external_mdio: mdio@2009087f {
640 reg = <0x2009087f>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 };
644 };
645 };
646
647 &saradc {
648 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
649 clocks = <&xtal>,
650 <&clkc CLKID_SAR_ADC>,
651 <&clkc CLKID_SANA>,
652 <&clkc CLKID_SAR_ADC_CLK>,
653 <&clkc CLKID_SAR_ADC_SEL>;
654 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
655 };
656
657 &sd_emmc_a {
658 clocks = <&clkc CLKID_SD_EMMC_A>,
659 <&clkc CLKID_SD_EMMC_A_CLK0>,
660 <&clkc CLKID_FCLK_DIV2>;
661 clock-names = "core", "clkin0", "clkin1";
662 };
663
664 &sd_emmc_b {
665 clocks = <&clkc CLKID_SD_EMMC_B>,
666 <&clkc CLKID_SD_EMMC_B_CLK0>,
667 <&clkc CLKID_FCLK_DIV2>;
668 clock-names = "core", "clkin0", "clkin1";
669 };
670
671 &sd_emmc_c {
672 clocks = <&clkc CLKID_SD_EMMC_C>,
673 <&clkc CLKID_SD_EMMC_C_CLK0>,
674 <&clkc CLKID_FCLK_DIV2>;
675 clock-names = "core", "clkin0", "clkin1";
676 };
677
678 &spicc {
679 clocks = <&clkc CLKID_SPICC>;
680 clock-names = "core";
681 resets = <&reset RESET_PERIPHS_SPICC>;
682 num-cs = <1>;
683 };
684
685 &spifc {
686 clocks = <&clkc CLKID_SPI>;
687 };
688
689 &uart_A {
690 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
691 clock-names = "xtal", "pclk", "baud";
692 };
693
694 &uart_AO {
695 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
696 clock-names = "xtal", "pclk", "baud";
697 };
698
699 &uart_AO_B {
700 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
701 clock-names = "xtal", "pclk", "baud";
702 };
703
704 &uart_B {
705 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
706 clock-names = "xtal", "pclk", "baud";
707 };
708
709 &uart_C {
710 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
711 clock-names = "xtal", "pclk", "baud";
712 };
713
714 &vpu {
715 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
716 };