arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Endless Computers, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/input/input.h>
  10
  11 #include "meson-gxm.dtsi"
  12 #include "meson-gx-p23x-q20x.dtsi"
  13
  14 / {
  15         compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
  16         model = "Amlogic Meson GXM (S912) Q200 Development Board";
  17
  18         adc-keys {
  19                 compatible = "adc-keys";
  20                 io-channels = <&saradc 0>;
  21                 io-channel-names = "buttons";
  22                 keyup-threshold-microvolt = <1710000>;
  23
  24                 button-function {
  25                         label = "Update";
  26                         linux,code = <KEY_VENDOR>;
  27                         press-threshold-microvolt = <10000>;
  28                 };
  29         };
  30
  31         gpio-keys-polled {
  32                 compatible = "gpio-keys-polled";
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35                 poll-interval = <100>;
  36
  37                 button@0 {
  38                         label = "power";
  39                         linux,code = <KEY_POWER>;
  40                         gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
  41                 };
  42         };
  43 };
  44
  45 /* Q200 has exclusive choice between internal or external PHY */
  46 &ethmac {
  47         pinctrl-0 = <&eth_pins>;
  48         pinctrl-names = "default";
  49
  50         /* Select external PHY by default */
  51         phy-handle = <&external_phy>;
  52
  53         amlogic,tx-delay-ns = <2>;
  54
  55         /* External PHY reset is shared with internal PHY Led signals */
  56         snps,reset-gpio = <&gpio GPIOZ_14 0>;
  57         snps,reset-delays-us = <0 10000 1000000>;
  58         snps,reset-active-low;
  59
  60         /* External PHY is in RGMII */
  61         phy-mode = "rgmii";
  62 };
  63
  64 &external_mdio {
  65         external_phy: ethernet-phy@0 {
  66                 compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
  67                 reg = <0>;
  68                 max-speed = <1000>;
  69                 interrupt-parent = <&gpio_intc>;
  70                 /* MAC_INTR on GPIOZ_15 */
  71                 interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
  72         };
  73 };
  74
  75 &sd_emmc_a {
  76         brcmf: wifi@1 {
  77                 reg = <1>;
  78                 compatible = "brcm,bcm4329-fmac";
  79         };
  80 };