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arm64: dts: juno: refactor CoreSight support on Juno r0
[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / boot / dts / arm / juno-base.dtsi
1 #include "juno-clocks.dtsi"
2
3 / {
4 /*
5 * Devices shared by all Juno boards
6 */
7
8 memtimer: timer@2a810000 {
9 compatible = "arm,armv7-timer-mem";
10 reg = <0x0 0x2a810000 0x0 0x10000>;
11 clock-frequency = <50000000>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 ranges;
15 status = "disabled";
16 frame@2a830000 {
17 frame-number = <1>;
18 interrupts = <0 60 4>;
19 reg = <0x0 0x2a830000 0x0 0x10000>;
20 };
21 };
22
23 mailbox: mhu@2b1f0000 {
24 compatible = "arm,mhu", "arm,primecell";
25 reg = <0x0 0x2b1f0000 0x0 0x1000>;
26 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
27 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
28 interrupt-names = "mhu_lpri_rx",
29 "mhu_hpri_rx";
30 #mbox-cells = <1>;
31 clocks = <&soc_refclk100mhz>;
32 clock-names = "apb_pclk";
33 };
34
35 smmu_pcie: iommu@2b500000 {
36 compatible = "arm,mmu-401", "arm,smmu-v1";
37 reg = <0x0 0x2b500000 0x0 0x10000>;
38 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
40 #iommu-cells = <1>;
41 #global-interrupts = <1>;
42 dma-coherent;
43 status = "disabled";
44 };
45
46 smmu_etr: iommu@2b600000 {
47 compatible = "arm,mmu-401", "arm,smmu-v1";
48 reg = <0x0 0x2b600000 0x0 0x10000>;
49 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
51 #iommu-cells = <1>;
52 #global-interrupts = <1>;
53 dma-coherent;
54 status = "disabled";
55 };
56
57 gic: interrupt-controller@2c010000 {
58 compatible = "arm,gic-400", "arm,cortex-a15-gic";
59 reg = <0x0 0x2c010000 0 0x1000>,
60 <0x0 0x2c02f000 0 0x2000>,
61 <0x0 0x2c04f000 0 0x2000>,
62 <0x0 0x2c06f000 0 0x2000>;
63 #address-cells = <2>;
64 #interrupt-cells = <3>;
65 #size-cells = <2>;
66 interrupt-controller;
67 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
68 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
69 v2m_0: v2m@0 {
70 compatible = "arm,gic-v2m-frame";
71 msi-controller;
72 reg = <0 0 0 0x1000>;
73 };
74 };
75
76 timer {
77 compatible = "arm,armv8-timer";
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
82 };
83
84 /*
85 * Juno TRMs specify the size for these coresight components as 64K.
86 * The actual size is just 4K though 64K is reserved. Access to the
87 * unmapped reserved region results in a DECERR response.
88 */
89 etf@20010000 { /* etf0 */
90 compatible = "arm,coresight-tmc", "arm,primecell";
91 reg = <0 0x20010000 0 0x1000>;
92
93 clocks = <&soc_smc50mhz>;
94 clock-names = "apb_pclk";
95 power-domains = <&scpi_devpd 0>;
96 ports {
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 /* input port */
101 port@0 {
102 reg = <0>;
103 etf0_in_port: endpoint {
104 slave-mode;
105 remote-endpoint = <&main_funnel_out_port>;
106 };
107 };
108
109 /* output port */
110 port@1 {
111 reg = <0>;
112 etf0_out_port: endpoint {
113 };
114 };
115 };
116 };
117
118 tpiu@20030000 {
119 compatible = "arm,coresight-tpiu", "arm,primecell";
120 reg = <0 0x20030000 0 0x1000>;
121
122 clocks = <&soc_smc50mhz>;
123 clock-names = "apb_pclk";
124 power-domains = <&scpi_devpd 0>;
125 port {
126 tpiu_in_port: endpoint {
127 slave-mode;
128 remote-endpoint = <&replicator_out_port0>;
129 };
130 };
131 };
132
133 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
134 main_funnel: funnel@20040000 {
135 compatible = "arm,coresight-funnel", "arm,primecell";
136 reg = <0 0x20040000 0 0x1000>;
137
138 clocks = <&soc_smc50mhz>;
139 clock-names = "apb_pclk";
140 power-domains = <&scpi_devpd 0>;
141 ports {
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 /* output port */
146 port@0 {
147 reg = <0>;
148 main_funnel_out_port: endpoint {
149 remote-endpoint = <&etf0_in_port>;
150 };
151 };
152
153 /* input ports */
154 port@1 {
155 reg = <0>;
156 main_funnel_in_port0: endpoint {
157 slave-mode;
158 remote-endpoint = <&cluster0_funnel_out_port>;
159 };
160 };
161
162 port@2 {
163 reg = <1>;
164 main_funnel_in_port1: endpoint {
165 slave-mode;
166 remote-endpoint = <&cluster1_funnel_out_port>;
167 };
168 };
169 };
170 };
171
172 etr@20070000 {
173 compatible = "arm,coresight-tmc", "arm,primecell";
174 reg = <0 0x20070000 0 0x1000>;
175 iommus = <&smmu_etr 0>;
176
177 clocks = <&soc_smc50mhz>;
178 clock-names = "apb_pclk";
179 power-domains = <&scpi_devpd 0>;
180 port {
181 etr_in_port: endpoint {
182 slave-mode;
183 remote-endpoint = <&replicator_out_port1>;
184 };
185 };
186 };
187
188 etm0: etm@22040000 {
189 compatible = "arm,coresight-etm4x", "arm,primecell";
190 reg = <0 0x22040000 0 0x1000>;
191
192 clocks = <&soc_smc50mhz>;
193 clock-names = "apb_pclk";
194 power-domains = <&scpi_devpd 0>;
195 port {
196 cluster0_etm0_out_port: endpoint {
197 remote-endpoint = <&cluster0_funnel_in_port0>;
198 };
199 };
200 };
201
202 funnel@220c0000 { /* cluster0 funnel */
203 compatible = "arm,coresight-funnel", "arm,primecell";
204 reg = <0 0x220c0000 0 0x1000>;
205
206 clocks = <&soc_smc50mhz>;
207 clock-names = "apb_pclk";
208 power-domains = <&scpi_devpd 0>;
209 ports {
210 #address-cells = <1>;
211 #size-cells = <0>;
212
213 port@0 {
214 reg = <0>;
215 cluster0_funnel_out_port: endpoint {
216 remote-endpoint = <&main_funnel_in_port0>;
217 };
218 };
219
220 port@1 {
221 reg = <0>;
222 cluster0_funnel_in_port0: endpoint {
223 slave-mode;
224 remote-endpoint = <&cluster0_etm0_out_port>;
225 };
226 };
227
228 port@2 {
229 reg = <1>;
230 cluster0_funnel_in_port1: endpoint {
231 slave-mode;
232 remote-endpoint = <&cluster0_etm1_out_port>;
233 };
234 };
235 };
236 };
237
238 etm1: etm@22140000 {
239 compatible = "arm,coresight-etm4x", "arm,primecell";
240 reg = <0 0x22140000 0 0x1000>;
241
242 clocks = <&soc_smc50mhz>;
243 clock-names = "apb_pclk";
244 power-domains = <&scpi_devpd 0>;
245 port {
246 cluster0_etm1_out_port: endpoint {
247 remote-endpoint = <&cluster0_funnel_in_port1>;
248 };
249 };
250 };
251
252 etm2: etm@23040000 {
253 compatible = "arm,coresight-etm4x", "arm,primecell";
254 reg = <0 0x23040000 0 0x1000>;
255
256 clocks = <&soc_smc50mhz>;
257 clock-names = "apb_pclk";
258 power-domains = <&scpi_devpd 0>;
259 port {
260 cluster1_etm0_out_port: endpoint {
261 remote-endpoint = <&cluster1_funnel_in_port0>;
262 };
263 };
264 };
265
266 funnel@230c0000 { /* cluster1 funnel */
267 compatible = "arm,coresight-funnel", "arm,primecell";
268 reg = <0 0x230c0000 0 0x1000>;
269
270 clocks = <&soc_smc50mhz>;
271 clock-names = "apb_pclk";
272 power-domains = <&scpi_devpd 0>;
273 ports {
274 #address-cells = <1>;
275 #size-cells = <0>;
276
277 port@0 {
278 reg = <0>;
279 cluster1_funnel_out_port: endpoint {
280 remote-endpoint = <&main_funnel_in_port1>;
281 };
282 };
283
284 port@1 {
285 reg = <0>;
286 cluster1_funnel_in_port0: endpoint {
287 slave-mode;
288 remote-endpoint = <&cluster1_etm0_out_port>;
289 };
290 };
291
292 port@2 {
293 reg = <1>;
294 cluster1_funnel_in_port1: endpoint {
295 slave-mode;
296 remote-endpoint = <&cluster1_etm1_out_port>;
297 };
298 };
299 port@3 {
300 reg = <2>;
301 cluster1_funnel_in_port2: endpoint {
302 slave-mode;
303 remote-endpoint = <&cluster1_etm2_out_port>;
304 };
305 };
306 port@4 {
307 reg = <3>;
308 cluster1_funnel_in_port3: endpoint {
309 slave-mode;
310 remote-endpoint = <&cluster1_etm3_out_port>;
311 };
312 };
313 };
314 };
315
316 etm3: etm@23140000 {
317 compatible = "arm,coresight-etm4x", "arm,primecell";
318 reg = <0 0x23140000 0 0x1000>;
319
320 clocks = <&soc_smc50mhz>;
321 clock-names = "apb_pclk";
322 power-domains = <&scpi_devpd 0>;
323 port {
324 cluster1_etm1_out_port: endpoint {
325 remote-endpoint = <&cluster1_funnel_in_port1>;
326 };
327 };
328 };
329
330 etm4: etm@23240000 {
331 compatible = "arm,coresight-etm4x", "arm,primecell";
332 reg = <0 0x23240000 0 0x1000>;
333
334 clocks = <&soc_smc50mhz>;
335 clock-names = "apb_pclk";
336 power-domains = <&scpi_devpd 0>;
337 port {
338 cluster1_etm2_out_port: endpoint {
339 remote-endpoint = <&cluster1_funnel_in_port2>;
340 };
341 };
342 };
343
344 etm5: etm@23340000 {
345 compatible = "arm,coresight-etm4x", "arm,primecell";
346 reg = <0 0x23340000 0 0x1000>;
347
348 clocks = <&soc_smc50mhz>;
349 clock-names = "apb_pclk";
350 power-domains = <&scpi_devpd 0>;
351 port {
352 cluster1_etm3_out_port: endpoint {
353 remote-endpoint = <&cluster1_funnel_in_port3>;
354 };
355 };
356 };
357
358 coresight-replicator {
359 /*
360 * Non-configurable replicators don't show up on the
361 * AMBA bus. As such no need to add "arm,primecell".
362 */
363 compatible = "arm,coresight-replicator";
364
365 ports {
366 #address-cells = <1>;
367 #size-cells = <0>;
368
369 /* replicator output ports */
370 port@0 {
371 reg = <0>;
372 replicator_out_port0: endpoint {
373 remote-endpoint = <&tpiu_in_port>;
374 };
375 };
376
377 port@1 {
378 reg = <1>;
379 replicator_out_port1: endpoint {
380 remote-endpoint = <&etr_in_port>;
381 };
382 };
383
384 /* replicator input port */
385 port@2 {
386 reg = <0>;
387 replicator_in_port0: endpoint {
388 slave-mode;
389 };
390 };
391 };
392 };
393
394 sram: sram@2e000000 {
395 compatible = "arm,juno-sram-ns", "mmio-sram";
396 reg = <0x0 0x2e000000 0x0 0x8000>;
397
398 #address-cells = <1>;
399 #size-cells = <1>;
400 ranges = <0 0x0 0x2e000000 0x8000>;
401
402 cpu_scp_lpri: scp-shmem@0 {
403 compatible = "arm,juno-scp-shmem";
404 reg = <0x0 0x200>;
405 };
406
407 cpu_scp_hpri: scp-shmem@200 {
408 compatible = "arm,juno-scp-shmem";
409 reg = <0x200 0x200>;
410 };
411 };
412
413 pcie_ctlr: pcie-controller@40000000 {
414 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
415 device_type = "pci";
416 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
417 bus-range = <0 255>;
418 linux,pci-domain = <0>;
419 #address-cells = <3>;
420 #size-cells = <2>;
421 dma-coherent;
422 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
423 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
424 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
425 #interrupt-cells = <1>;
426 interrupt-map-mask = <0 0 0 7>;
427 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
428 <0 0 0 2 &gic 0 0 0 137 4>,
429 <0 0 0 3 &gic 0 0 0 138 4>,
430 <0 0 0 4 &gic 0 0 0 139 4>;
431 msi-parent = <&v2m_0>;
432 status = "disabled";
433 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
434 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
435 };
436
437 scpi {
438 compatible = "arm,scpi";
439 mboxes = <&mailbox 1>;
440 shmem = <&cpu_scp_hpri>;
441
442 clocks {
443 compatible = "arm,scpi-clocks";
444
445 scpi_dvfs: scpi-dvfs {
446 compatible = "arm,scpi-dvfs-clocks";
447 #clock-cells = <1>;
448 clock-indices = <0>, <1>, <2>;
449 clock-output-names = "atlclk", "aplclk","gpuclk";
450 };
451 scpi_clk: scpi-clk {
452 compatible = "arm,scpi-variable-clocks";
453 #clock-cells = <1>;
454 clock-indices = <3>;
455 clock-output-names = "pxlclk";
456 };
457 };
458
459 scpi_devpd: scpi-power-domains {
460 compatible = "arm,scpi-power-domains";
461 num-domains = <2>;
462 #power-domain-cells = <1>;
463 };
464
465 scpi_sensors0: sensors {
466 compatible = "arm,scpi-sensors";
467 #thermal-sensor-cells = <1>;
468 };
469 };
470
471 thermal-zones {
472 pmic {
473 polling-delay = <1000>;
474 polling-delay-passive = <100>;
475 thermal-sensors = <&scpi_sensors0 0>;
476 };
477
478 soc {
479 polling-delay = <1000>;
480 polling-delay-passive = <100>;
481 thermal-sensors = <&scpi_sensors0 3>;
482 };
483
484 big_cluster_thermal_zone: big_cluster {
485 polling-delay = <1000>;
486 polling-delay-passive = <100>;
487 thermal-sensors = <&scpi_sensors0 21>;
488 status = "disabled";
489 };
490
491 little_cluster_thermal_zone: little_cluster {
492 polling-delay = <1000>;
493 polling-delay-passive = <100>;
494 thermal-sensors = <&scpi_sensors0 22>;
495 status = "disabled";
496 };
497
498 gpu0_thermal_zone: gpu0 {
499 polling-delay = <1000>;
500 polling-delay-passive = <100>;
501 thermal-sensors = <&scpi_sensors0 23>;
502 status = "disabled";
503 };
504
505 gpu1_thermal_zone: gpu1 {
506 polling-delay = <1000>;
507 polling-delay-passive = <100>;
508 thermal-sensors = <&scpi_sensors0 24>;
509 status = "disabled";
510 };
511 };
512
513 smmu_dma: iommu@7fb00000 {
514 compatible = "arm,mmu-401", "arm,smmu-v1";
515 reg = <0x0 0x7fb00000 0x0 0x10000>;
516 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
518 #iommu-cells = <1>;
519 #global-interrupts = <1>;
520 dma-coherent;
521 status = "disabled";
522 };
523
524 smmu_hdlcd1: iommu@7fb10000 {
525 compatible = "arm,mmu-401", "arm,smmu-v1";
526 reg = <0x0 0x7fb10000 0x0 0x10000>;
527 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
529 #iommu-cells = <1>;
530 #global-interrupts = <1>;
531 status = "disabled";
532 };
533
534 smmu_hdlcd0: iommu@7fb20000 {
535 compatible = "arm,mmu-401", "arm,smmu-v1";
536 reg = <0x0 0x7fb20000 0x0 0x10000>;
537 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
539 #iommu-cells = <1>;
540 #global-interrupts = <1>;
541 status = "disabled";
542 };
543
544 smmu_usb: iommu@7fb30000 {
545 compatible = "arm,mmu-401", "arm,smmu-v1";
546 reg = <0x0 0x7fb30000 0x0 0x10000>;
547 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
549 #iommu-cells = <1>;
550 #global-interrupts = <1>;
551 dma-coherent;
552 status = "disabled";
553 };
554
555 dma@7ff00000 {
556 compatible = "arm,pl330", "arm,primecell";
557 reg = <0x0 0x7ff00000 0 0x1000>;
558 #dma-cells = <1>;
559 #dma-channels = <8>;
560 #dma-requests = <32>;
561 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
570 iommus = <&smmu_dma 0>,
571 <&smmu_dma 1>,
572 <&smmu_dma 2>,
573 <&smmu_dma 3>,
574 <&smmu_dma 4>,
575 <&smmu_dma 5>,
576 <&smmu_dma 6>,
577 <&smmu_dma 7>,
578 <&smmu_dma 8>;
579 clocks = <&soc_faxiclk>;
580 clock-names = "apb_pclk";
581 };
582
583 hdlcd@7ff50000 {
584 compatible = "arm,hdlcd";
585 reg = <0 0x7ff50000 0 0x1000>;
586 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
587 iommus = <&smmu_hdlcd1 0>;
588 clocks = <&scpi_clk 3>;
589 clock-names = "pxlclk";
590
591 port {
592 hdlcd1_output: hdlcd1-endpoint {
593 remote-endpoint = <&tda998x_1_input>;
594 };
595 };
596 };
597
598 hdlcd@7ff60000 {
599 compatible = "arm,hdlcd";
600 reg = <0 0x7ff60000 0 0x1000>;
601 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
602 iommus = <&smmu_hdlcd0 0>;
603 clocks = <&scpi_clk 3>;
604 clock-names = "pxlclk";
605
606 port {
607 hdlcd0_output: hdlcd0-endpoint {
608 remote-endpoint = <&tda998x_0_input>;
609 };
610 };
611 };
612
613 soc_uart0: uart@7ff80000 {
614 compatible = "arm,pl011", "arm,primecell";
615 reg = <0x0 0x7ff80000 0x0 0x1000>;
616 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
618 clock-names = "uartclk", "apb_pclk";
619 };
620
621 i2c@7ffa0000 {
622 compatible = "snps,designware-i2c";
623 reg = <0x0 0x7ffa0000 0x0 0x1000>;
624 #address-cells = <1>;
625 #size-cells = <0>;
626 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
627 clock-frequency = <400000>;
628 i2c-sda-hold-time-ns = <500>;
629 clocks = <&soc_smc50mhz>;
630
631 hdmi-transmitter@70 {
632 compatible = "nxp,tda998x";
633 reg = <0x70>;
634 port {
635 tda998x_0_input: tda998x-0-endpoint {
636 remote-endpoint = <&hdlcd0_output>;
637 };
638 };
639 };
640
641 hdmi-transmitter@71 {
642 compatible = "nxp,tda998x";
643 reg = <0x71>;
644 port {
645 tda998x_1_input: tda998x-1-endpoint {
646 remote-endpoint = <&hdlcd1_output>;
647 };
648 };
649 };
650 };
651
652 ohci@7ffb0000 {
653 compatible = "generic-ohci";
654 reg = <0x0 0x7ffb0000 0x0 0x10000>;
655 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
656 iommus = <&smmu_usb 0>;
657 clocks = <&soc_usb48mhz>;
658 };
659
660 ehci@7ffc0000 {
661 compatible = "generic-ehci";
662 reg = <0x0 0x7ffc0000 0x0 0x10000>;
663 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
664 iommus = <&smmu_usb 0>;
665 clocks = <&soc_usb48mhz>;
666 };
667
668 memory-controller@7ffd0000 {
669 compatible = "arm,pl354", "arm,primecell";
670 reg = <0 0x7ffd0000 0 0x1000>;
671 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&soc_smc50mhz>;
674 clock-names = "apb_pclk";
675 };
676
677 memory@80000000 {
678 device_type = "memory";
679 /* last 16MB of the first memory area is reserved for secure world use by firmware */
680 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
681 <0x00000008 0x80000000 0x1 0x80000000>;
682 };
683
684 smb@08000000 {
685 compatible = "simple-bus";
686 #address-cells = <2>;
687 #size-cells = <1>;
688 ranges = <0 0 0 0x08000000 0x04000000>,
689 <1 0 0 0x14000000 0x04000000>,
690 <2 0 0 0x18000000 0x04000000>,
691 <3 0 0 0x1c000000 0x04000000>,
692 <4 0 0 0x0c000000 0x04000000>,
693 <5 0 0 0x10000000 0x04000000>;
694
695 #interrupt-cells = <1>;
696 interrupt-map-mask = <0 0 15>;
697 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
698 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
699 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
700 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
701 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
702 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
703 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
704 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
705 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
706 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
707 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
708 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
709 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
710
711 /include/ "juno-motherboard.dtsi"
712 };
713
714 site2: tlx@60000000 {
715 compatible = "simple-bus";
716 #address-cells = <1>;
717 #size-cells = <1>;
718 ranges = <0 0 0x60000000 0x10000000>;
719 #interrupt-cells = <1>;
720 interrupt-map-mask = <0 0>;
721 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
722 };
723 };
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