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Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into...
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / boot / dts / arm / juno-base.dtsi
1 #include "juno-clocks.dtsi"
2
3 / {
4 /*
5 * Devices shared by all Juno boards
6 */
7 dma-ranges = <0 0 0 0 0x100 0>;
8
9 memtimer: timer@2a810000 {
10 compatible = "arm,armv7-timer-mem";
11 reg = <0x0 0x2a810000 0x0 0x10000>;
12 clock-frequency = <50000000>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 ranges;
16 status = "disabled";
17 frame@2a830000 {
18 frame-number = <1>;
19 interrupts = <0 60 4>;
20 reg = <0x0 0x2a830000 0x0 0x10000>;
21 };
22 };
23
24 mailbox: mhu@2b1f0000 {
25 compatible = "arm,mhu", "arm,primecell";
26 reg = <0x0 0x2b1f0000 0x0 0x1000>;
27 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-names = "mhu_lpri_rx",
30 "mhu_hpri_rx";
31 #mbox-cells = <1>;
32 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk";
34 };
35
36 smmu_pcie: iommu@2b500000 {
37 compatible = "arm,mmu-401", "arm,smmu-v1";
38 reg = <0x0 0x2b500000 0x0 0x10000>;
39 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
41 #iommu-cells = <1>;
42 #global-interrupts = <1>;
43 dma-coherent;
44 status = "disabled";
45 };
46
47 smmu_etr: iommu@2b600000 {
48 compatible = "arm,mmu-401", "arm,smmu-v1";
49 reg = <0x0 0x2b600000 0x0 0x10000>;
50 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
52 #iommu-cells = <1>;
53 #global-interrupts = <1>;
54 dma-coherent;
55 power-domains = <&scpi_devpd 0>;
56 status = "disabled";
57 };
58
59 gic: interrupt-controller@2c010000 {
60 compatible = "arm,gic-400", "arm,cortex-a15-gic";
61 reg = <0x0 0x2c010000 0 0x1000>,
62 <0x0 0x2c02f000 0 0x2000>,
63 <0x0 0x2c04f000 0 0x2000>,
64 <0x0 0x2c06f000 0 0x2000>;
65 #address-cells = <2>;
66 #interrupt-cells = <3>;
67 #size-cells = <2>;
68 interrupt-controller;
69 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
70 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
71 v2m_0: v2m@0 {
72 compatible = "arm,gic-v2m-frame";
73 msi-controller;
74 reg = <0 0 0 0x1000>;
75 };
76 };
77
78 timer {
79 compatible = "arm,armv8-timer";
80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
84 };
85
86 /*
87 * Juno TRMs specify the size for these coresight components as 64K.
88 * The actual size is just 4K though 64K is reserved. Access to the
89 * unmapped reserved region results in a DECERR response.
90 */
91 etf@20010000 { /* etf0 */
92 compatible = "arm,coresight-tmc", "arm,primecell";
93 reg = <0 0x20010000 0 0x1000>;
94
95 clocks = <&soc_smc50mhz>;
96 clock-names = "apb_pclk";
97 power-domains = <&scpi_devpd 0>;
98 ports {
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 /* input port */
103 port@0 {
104 reg = <0>;
105 etf0_in_port: endpoint {
106 slave-mode;
107 remote-endpoint = <&main_funnel_out_port>;
108 };
109 };
110
111 /* output port */
112 port@1 {
113 reg = <0>;
114 etf0_out_port: endpoint {
115 };
116 };
117 };
118 };
119
120 tpiu@20030000 {
121 compatible = "arm,coresight-tpiu", "arm,primecell";
122 reg = <0 0x20030000 0 0x1000>;
123
124 clocks = <&soc_smc50mhz>;
125 clock-names = "apb_pclk";
126 power-domains = <&scpi_devpd 0>;
127 port {
128 tpiu_in_port: endpoint {
129 slave-mode;
130 remote-endpoint = <&replicator_out_port0>;
131 };
132 };
133 };
134
135 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
136 main_funnel: funnel@20040000 {
137 compatible = "arm,coresight-funnel", "arm,primecell";
138 reg = <0 0x20040000 0 0x1000>;
139
140 clocks = <&soc_smc50mhz>;
141 clock-names = "apb_pclk";
142 power-domains = <&scpi_devpd 0>;
143 ports {
144 #address-cells = <1>;
145 #size-cells = <0>;
146
147 /* output port */
148 port@0 {
149 reg = <0>;
150 main_funnel_out_port: endpoint {
151 remote-endpoint = <&etf0_in_port>;
152 };
153 };
154
155 /* input ports */
156 port@1 {
157 reg = <0>;
158 main_funnel_in_port0: endpoint {
159 slave-mode;
160 remote-endpoint = <&cluster0_funnel_out_port>;
161 };
162 };
163
164 port@2 {
165 reg = <1>;
166 main_funnel_in_port1: endpoint {
167 slave-mode;
168 remote-endpoint = <&cluster1_funnel_out_port>;
169 };
170 };
171 };
172 };
173
174 etr@20070000 {
175 compatible = "arm,coresight-tmc", "arm,primecell";
176 reg = <0 0x20070000 0 0x1000>;
177 iommus = <&smmu_etr 0>;
178
179 clocks = <&soc_smc50mhz>;
180 clock-names = "apb_pclk";
181 power-domains = <&scpi_devpd 0>;
182 port {
183 etr_in_port: endpoint {
184 slave-mode;
185 remote-endpoint = <&replicator_out_port1>;
186 };
187 };
188 };
189
190 stm@20100000 {
191 compatible = "arm,coresight-stm", "arm,primecell";
192 reg = <0 0x20100000 0 0x1000>,
193 <0 0x28000000 0 0x1000000>;
194 reg-names = "stm-base", "stm-stimulus-base";
195
196 clocks = <&soc_smc50mhz>;
197 clock-names = "apb_pclk";
198 power-domains = <&scpi_devpd 0>;
199 port {
200 stm_out_port: endpoint {
201 };
202 };
203 };
204
205 etm0: etm@22040000 {
206 compatible = "arm,coresight-etm4x", "arm,primecell";
207 reg = <0 0x22040000 0 0x1000>;
208
209 clocks = <&soc_smc50mhz>;
210 clock-names = "apb_pclk";
211 power-domains = <&scpi_devpd 0>;
212 port {
213 cluster0_etm0_out_port: endpoint {
214 remote-endpoint = <&cluster0_funnel_in_port0>;
215 };
216 };
217 };
218
219 funnel@220c0000 { /* cluster0 funnel */
220 compatible = "arm,coresight-funnel", "arm,primecell";
221 reg = <0 0x220c0000 0 0x1000>;
222
223 clocks = <&soc_smc50mhz>;
224 clock-names = "apb_pclk";
225 power-domains = <&scpi_devpd 0>;
226 ports {
227 #address-cells = <1>;
228 #size-cells = <0>;
229
230 port@0 {
231 reg = <0>;
232 cluster0_funnel_out_port: endpoint {
233 remote-endpoint = <&main_funnel_in_port0>;
234 };
235 };
236
237 port@1 {
238 reg = <0>;
239 cluster0_funnel_in_port0: endpoint {
240 slave-mode;
241 remote-endpoint = <&cluster0_etm0_out_port>;
242 };
243 };
244
245 port@2 {
246 reg = <1>;
247 cluster0_funnel_in_port1: endpoint {
248 slave-mode;
249 remote-endpoint = <&cluster0_etm1_out_port>;
250 };
251 };
252 };
253 };
254
255 etm1: etm@22140000 {
256 compatible = "arm,coresight-etm4x", "arm,primecell";
257 reg = <0 0x22140000 0 0x1000>;
258
259 clocks = <&soc_smc50mhz>;
260 clock-names = "apb_pclk";
261 power-domains = <&scpi_devpd 0>;
262 port {
263 cluster0_etm1_out_port: endpoint {
264 remote-endpoint = <&cluster0_funnel_in_port1>;
265 };
266 };
267 };
268
269 etm2: etm@23040000 {
270 compatible = "arm,coresight-etm4x", "arm,primecell";
271 reg = <0 0x23040000 0 0x1000>;
272
273 clocks = <&soc_smc50mhz>;
274 clock-names = "apb_pclk";
275 power-domains = <&scpi_devpd 0>;
276 port {
277 cluster1_etm0_out_port: endpoint {
278 remote-endpoint = <&cluster1_funnel_in_port0>;
279 };
280 };
281 };
282
283 funnel@230c0000 { /* cluster1 funnel */
284 compatible = "arm,coresight-funnel", "arm,primecell";
285 reg = <0 0x230c0000 0 0x1000>;
286
287 clocks = <&soc_smc50mhz>;
288 clock-names = "apb_pclk";
289 power-domains = <&scpi_devpd 0>;
290 ports {
291 #address-cells = <1>;
292 #size-cells = <0>;
293
294 port@0 {
295 reg = <0>;
296 cluster1_funnel_out_port: endpoint {
297 remote-endpoint = <&main_funnel_in_port1>;
298 };
299 };
300
301 port@1 {
302 reg = <0>;
303 cluster1_funnel_in_port0: endpoint {
304 slave-mode;
305 remote-endpoint = <&cluster1_etm0_out_port>;
306 };
307 };
308
309 port@2 {
310 reg = <1>;
311 cluster1_funnel_in_port1: endpoint {
312 slave-mode;
313 remote-endpoint = <&cluster1_etm1_out_port>;
314 };
315 };
316 port@3 {
317 reg = <2>;
318 cluster1_funnel_in_port2: endpoint {
319 slave-mode;
320 remote-endpoint = <&cluster1_etm2_out_port>;
321 };
322 };
323 port@4 {
324 reg = <3>;
325 cluster1_funnel_in_port3: endpoint {
326 slave-mode;
327 remote-endpoint = <&cluster1_etm3_out_port>;
328 };
329 };
330 };
331 };
332
333 etm3: etm@23140000 {
334 compatible = "arm,coresight-etm4x", "arm,primecell";
335 reg = <0 0x23140000 0 0x1000>;
336
337 clocks = <&soc_smc50mhz>;
338 clock-names = "apb_pclk";
339 power-domains = <&scpi_devpd 0>;
340 port {
341 cluster1_etm1_out_port: endpoint {
342 remote-endpoint = <&cluster1_funnel_in_port1>;
343 };
344 };
345 };
346
347 etm4: etm@23240000 {
348 compatible = "arm,coresight-etm4x", "arm,primecell";
349 reg = <0 0x23240000 0 0x1000>;
350
351 clocks = <&soc_smc50mhz>;
352 clock-names = "apb_pclk";
353 power-domains = <&scpi_devpd 0>;
354 port {
355 cluster1_etm2_out_port: endpoint {
356 remote-endpoint = <&cluster1_funnel_in_port2>;
357 };
358 };
359 };
360
361 etm5: etm@23340000 {
362 compatible = "arm,coresight-etm4x", "arm,primecell";
363 reg = <0 0x23340000 0 0x1000>;
364
365 clocks = <&soc_smc50mhz>;
366 clock-names = "apb_pclk";
367 power-domains = <&scpi_devpd 0>;
368 port {
369 cluster1_etm3_out_port: endpoint {
370 remote-endpoint = <&cluster1_funnel_in_port3>;
371 };
372 };
373 };
374
375 replicator@20120000 {
376 compatible = "qcom,coresight-replicator1x", "arm,primecell";
377 reg = <0 0x20120000 0 0x1000>;
378
379 clocks = <&soc_smc50mhz>;
380 clock-names = "apb_pclk";
381 power-domains = <&scpi_devpd 0>;
382
383 ports {
384 #address-cells = <1>;
385 #size-cells = <0>;
386
387 /* replicator output ports */
388 port@0 {
389 reg = <0>;
390 replicator_out_port0: endpoint {
391 remote-endpoint = <&tpiu_in_port>;
392 };
393 };
394
395 port@1 {
396 reg = <1>;
397 replicator_out_port1: endpoint {
398 remote-endpoint = <&etr_in_port>;
399 };
400 };
401
402 /* replicator input port */
403 port@2 {
404 reg = <0>;
405 replicator_in_port0: endpoint {
406 slave-mode;
407 };
408 };
409 };
410 };
411
412 sram: sram@2e000000 {
413 compatible = "arm,juno-sram-ns", "mmio-sram";
414 reg = <0x0 0x2e000000 0x0 0x8000>;
415
416 #address-cells = <1>;
417 #size-cells = <1>;
418 ranges = <0 0x0 0x2e000000 0x8000>;
419
420 cpu_scp_lpri: scp-shmem@0 {
421 compatible = "arm,juno-scp-shmem";
422 reg = <0x0 0x200>;
423 };
424
425 cpu_scp_hpri: scp-shmem@200 {
426 compatible = "arm,juno-scp-shmem";
427 reg = <0x200 0x200>;
428 };
429 };
430
431 pcie_ctlr: pcie-controller@40000000 {
432 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
433 device_type = "pci";
434 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
435 bus-range = <0 255>;
436 linux,pci-domain = <0>;
437 #address-cells = <3>;
438 #size-cells = <2>;
439 dma-coherent;
440 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
441 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
442 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
443 #interrupt-cells = <1>;
444 interrupt-map-mask = <0 0 0 7>;
445 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
446 <0 0 0 2 &gic 0 0 0 137 4>,
447 <0 0 0 3 &gic 0 0 0 138 4>,
448 <0 0 0 4 &gic 0 0 0 139 4>;
449 msi-parent = <&v2m_0>;
450 status = "disabled";
451 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
452 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
453 };
454
455 scpi {
456 compatible = "arm,scpi";
457 mboxes = <&mailbox 1>;
458 shmem = <&cpu_scp_hpri>;
459
460 clocks {
461 compatible = "arm,scpi-clocks";
462
463 scpi_dvfs: scpi-dvfs {
464 compatible = "arm,scpi-dvfs-clocks";
465 #clock-cells = <1>;
466 clock-indices = <0>, <1>, <2>;
467 clock-output-names = "atlclk", "aplclk","gpuclk";
468 };
469 scpi_clk: scpi-clk {
470 compatible = "arm,scpi-variable-clocks";
471 #clock-cells = <1>;
472 clock-indices = <3>;
473 clock-output-names = "pxlclk";
474 };
475 };
476
477 scpi_devpd: scpi-power-domains {
478 compatible = "arm,scpi-power-domains";
479 num-domains = <2>;
480 #power-domain-cells = <1>;
481 };
482
483 scpi_sensors0: sensors {
484 compatible = "arm,scpi-sensors";
485 #thermal-sensor-cells = <1>;
486 };
487 };
488
489 thermal-zones {
490 pmic {
491 polling-delay = <1000>;
492 polling-delay-passive = <100>;
493 thermal-sensors = <&scpi_sensors0 0>;
494 };
495
496 soc {
497 polling-delay = <1000>;
498 polling-delay-passive = <100>;
499 thermal-sensors = <&scpi_sensors0 3>;
500 };
501
502 big_cluster_thermal_zone: big_cluster {
503 polling-delay = <1000>;
504 polling-delay-passive = <100>;
505 thermal-sensors = <&scpi_sensors0 21>;
506 status = "disabled";
507 };
508
509 little_cluster_thermal_zone: little_cluster {
510 polling-delay = <1000>;
511 polling-delay-passive = <100>;
512 thermal-sensors = <&scpi_sensors0 22>;
513 status = "disabled";
514 };
515
516 gpu0_thermal_zone: gpu0 {
517 polling-delay = <1000>;
518 polling-delay-passive = <100>;
519 thermal-sensors = <&scpi_sensors0 23>;
520 status = "disabled";
521 };
522
523 gpu1_thermal_zone: gpu1 {
524 polling-delay = <1000>;
525 polling-delay-passive = <100>;
526 thermal-sensors = <&scpi_sensors0 24>;
527 status = "disabled";
528 };
529 };
530
531 smmu_dma: iommu@7fb00000 {
532 compatible = "arm,mmu-401", "arm,smmu-v1";
533 reg = <0x0 0x7fb00000 0x0 0x10000>;
534 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
536 #iommu-cells = <1>;
537 #global-interrupts = <1>;
538 dma-coherent;
539 status = "disabled";
540 };
541
542 smmu_hdlcd1: iommu@7fb10000 {
543 compatible = "arm,mmu-401", "arm,smmu-v1";
544 reg = <0x0 0x7fb10000 0x0 0x10000>;
545 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
547 #iommu-cells = <1>;
548 #global-interrupts = <1>;
549 status = "disabled";
550 };
551
552 smmu_hdlcd0: iommu@7fb20000 {
553 compatible = "arm,mmu-401", "arm,smmu-v1";
554 reg = <0x0 0x7fb20000 0x0 0x10000>;
555 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
557 #iommu-cells = <1>;
558 #global-interrupts = <1>;
559 status = "disabled";
560 };
561
562 smmu_usb: iommu@7fb30000 {
563 compatible = "arm,mmu-401", "arm,smmu-v1";
564 reg = <0x0 0x7fb30000 0x0 0x10000>;
565 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
567 #iommu-cells = <1>;
568 #global-interrupts = <1>;
569 dma-coherent;
570 status = "disabled";
571 };
572
573 dma@7ff00000 {
574 compatible = "arm,pl330", "arm,primecell";
575 reg = <0x0 0x7ff00000 0 0x1000>;
576 #dma-cells = <1>;
577 #dma-channels = <8>;
578 #dma-requests = <32>;
579 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
588 iommus = <&smmu_dma 0>,
589 <&smmu_dma 1>,
590 <&smmu_dma 2>,
591 <&smmu_dma 3>,
592 <&smmu_dma 4>,
593 <&smmu_dma 5>,
594 <&smmu_dma 6>,
595 <&smmu_dma 7>,
596 <&smmu_dma 8>;
597 clocks = <&soc_faxiclk>;
598 clock-names = "apb_pclk";
599 };
600
601 hdlcd@7ff50000 {
602 compatible = "arm,hdlcd";
603 reg = <0 0x7ff50000 0 0x1000>;
604 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
605 iommus = <&smmu_hdlcd1 0>;
606 clocks = <&scpi_clk 3>;
607 clock-names = "pxlclk";
608
609 port {
610 hdlcd1_output: hdlcd1-endpoint {
611 remote-endpoint = <&tda998x_1_input>;
612 };
613 };
614 };
615
616 hdlcd@7ff60000 {
617 compatible = "arm,hdlcd";
618 reg = <0 0x7ff60000 0 0x1000>;
619 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
620 iommus = <&smmu_hdlcd0 0>;
621 clocks = <&scpi_clk 3>;
622 clock-names = "pxlclk";
623
624 port {
625 hdlcd0_output: hdlcd0-endpoint {
626 remote-endpoint = <&tda998x_0_input>;
627 };
628 };
629 };
630
631 soc_uart0: uart@7ff80000 {
632 compatible = "arm,pl011", "arm,primecell";
633 reg = <0x0 0x7ff80000 0x0 0x1000>;
634 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
636 clock-names = "uartclk", "apb_pclk";
637 };
638
639 i2c@7ffa0000 {
640 compatible = "snps,designware-i2c";
641 reg = <0x0 0x7ffa0000 0x0 0x1000>;
642 #address-cells = <1>;
643 #size-cells = <0>;
644 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
645 clock-frequency = <400000>;
646 i2c-sda-hold-time-ns = <500>;
647 clocks = <&soc_smc50mhz>;
648
649 hdmi-transmitter@70 {
650 compatible = "nxp,tda998x";
651 reg = <0x70>;
652 port {
653 tda998x_0_input: tda998x-0-endpoint {
654 remote-endpoint = <&hdlcd0_output>;
655 };
656 };
657 };
658
659 hdmi-transmitter@71 {
660 compatible = "nxp,tda998x";
661 reg = <0x71>;
662 port {
663 tda998x_1_input: tda998x-1-endpoint {
664 remote-endpoint = <&hdlcd1_output>;
665 };
666 };
667 };
668 };
669
670 ohci@7ffb0000 {
671 compatible = "generic-ohci";
672 reg = <0x0 0x7ffb0000 0x0 0x10000>;
673 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
674 iommus = <&smmu_usb 0>;
675 clocks = <&soc_usb48mhz>;
676 };
677
678 ehci@7ffc0000 {
679 compatible = "generic-ehci";
680 reg = <0x0 0x7ffc0000 0x0 0x10000>;
681 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
682 iommus = <&smmu_usb 0>;
683 clocks = <&soc_usb48mhz>;
684 };
685
686 memory-controller@7ffd0000 {
687 compatible = "arm,pl354", "arm,primecell";
688 reg = <0 0x7ffd0000 0 0x1000>;
689 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&soc_smc50mhz>;
692 clock-names = "apb_pclk";
693 };
694
695 memory@80000000 {
696 device_type = "memory";
697 /* last 16MB of the first memory area is reserved for secure world use by firmware */
698 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
699 <0x00000008 0x80000000 0x1 0x80000000>;
700 };
701
702 smb@08000000 {
703 compatible = "simple-bus";
704 #address-cells = <2>;
705 #size-cells = <1>;
706 ranges = <0 0 0 0x08000000 0x04000000>,
707 <1 0 0 0x14000000 0x04000000>,
708 <2 0 0 0x18000000 0x04000000>,
709 <3 0 0 0x1c000000 0x04000000>,
710 <4 0 0 0x0c000000 0x04000000>,
711 <5 0 0 0x10000000 0x04000000>;
712
713 #interrupt-cells = <1>;
714 interrupt-map-mask = <0 0 15>;
715 interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
716 <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
717 <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
718 <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
719 <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
720 <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
721 <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
722 <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
723 <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
724 <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
725 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
726 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
727 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
728
729 /include/ "juno-motherboard.dtsi"
730 };
731
732 site2: tlx@60000000 {
733 compatible = "simple-bus";
734 #address-cells = <1>;
735 #size-cells = <1>;
736 ranges = <0 0 0x60000000 0x10000000>;
737 #interrupt-cells = <1>;
738 interrupt-map-mask = <0 0>;
739 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
740 };
741 };
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