2 * ARM Ltd. Juno Platform
4 * Copyright (c) 2015 ARM Ltd.
6 * This file is licensed under a dual GPLv2 or BSD license.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "ARM Juno development board (r1)";
15 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
16 interrupt-parent = <&gic>;
25 stdout-path = "serial0:115200n8";
29 compatible = "arm,psci-0.2";
64 entry-method = "arm,psci";
66 CPU_SLEEP_0: cpu-sleep-0 {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x0010000>;
70 entry-latency-us = <300>;
71 exit-latency-us = <1200>;
72 min-residency-us = <2000>;
75 CLUSTER_SLEEP_0: cluster-sleep-0 {
76 compatible = "arm,idle-state";
77 arm,psci-suspend-param = <0x1010000>;
79 entry-latency-us = <400>;
80 exit-latency-us = <1200>;
81 min-residency-us = <2500>;
86 compatible = "arm,cortex-a57","arm,armv8";
89 enable-method = "psci";
90 next-level-cache = <&A57_L2>;
91 clocks = <&scpi_dvfs 0>;
92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
93 capacity-dmips-mhz = <1024>;
97 compatible = "arm,cortex-a57","arm,armv8";
100 enable-method = "psci";
101 next-level-cache = <&A57_L2>;
102 clocks = <&scpi_dvfs 0>;
103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
108 compatible = "arm,cortex-a53","arm,armv8";
111 enable-method = "psci";
112 next-level-cache = <&A53_L2>;
113 clocks = <&scpi_dvfs 1>;
114 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
115 capacity-dmips-mhz = <578>;
119 compatible = "arm,cortex-a53","arm,armv8";
122 enable-method = "psci";
123 next-level-cache = <&A53_L2>;
124 clocks = <&scpi_dvfs 1>;
125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
126 capacity-dmips-mhz = <578>;
130 compatible = "arm,cortex-a53","arm,armv8";
133 enable-method = "psci";
134 next-level-cache = <&A53_L2>;
135 clocks = <&scpi_dvfs 1>;
136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137 capacity-dmips-mhz = <578>;
141 compatible = "arm,cortex-a53","arm,armv8";
144 enable-method = "psci";
145 next-level-cache = <&A53_L2>;
146 clocks = <&scpi_dvfs 1>;
147 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
148 capacity-dmips-mhz = <578>;
152 compatible = "cache";
156 compatible = "cache";
161 compatible = "arm,cortex-a57-pmu";
162 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-affinity = <&A57_0>,
169 compatible = "arm,cortex-a53-pmu";
170 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
174 interrupt-affinity = <&A53_0>,
180 #include "juno-base.dtsi"
215 &big_cluster_thermal_zone {
219 &little_cluster_thermal_zone {