arch/arm64/boot/dts/arm/juno.dts

   1 /*
   2  * ARM Ltd. Juno Platform
   3  *
   4  * Copyright (c) 2013-2014 ARM Ltd.
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12
  13 / {
  14         model = "ARM Juno development board (r0)";
  15         compatible = "arm,juno", "arm,vexpress";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &soc_uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 cpu-map {
  38                         cluster0 {
  39                                 core0 {
  40                                         cpu = <&A57_0>;
  41                                 };
  42                                 core1 {
  43                                         cpu = <&A57_1>;
  44                                 };
  45                         };
  46
  47                         cluster1 {
  48                                 core0 {
  49                                         cpu = <&A53_0>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&A53_1>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&A53_2>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&A53_3>;
  59                                 };
  60                         };
  61                 };
  62
  63                 A57_0: cpu@0 {
  64                         compatible = "arm,cortex-a57","arm,armv8";
  65                         reg = <0x0 0x0>;
  66                         device_type = "cpu";
  67                         enable-method = "psci";
  68                         next-level-cache = <&A57_L2>;
  69                         clocks = <&scpi_dvfs 0>;
  70                 };
  71
  72                 A57_1: cpu@1 {
  73                         compatible = "arm,cortex-a57","arm,armv8";
  74                         reg = <0x0 0x1>;
  75                         device_type = "cpu";
  76                         enable-method = "psci";
  77                         next-level-cache = <&A57_L2>;
  78                         clocks = <&scpi_dvfs 0>;
  79                 };
  80
  81                 A53_0: cpu@100 {
  82                         compatible = "arm,cortex-a53","arm,armv8";
  83                         reg = <0x0 0x100>;
  84                         device_type = "cpu";
  85                         enable-method = "psci";
  86                         next-level-cache = <&A53_L2>;
  87                         clocks = <&scpi_dvfs 1>;
  88                 };
  89
  90                 A53_1: cpu@101 {
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x101>;
  93                         device_type = "cpu";
  94                         enable-method = "psci";
  95                         next-level-cache = <&A53_L2>;
  96                         clocks = <&scpi_dvfs 1>;
  97                 };
  98
  99                 A53_2: cpu@102 {
 100                         compatible = "arm,cortex-a53","arm,armv8";
 101                         reg = <0x0 0x102>;
 102                         device_type = "cpu";
 103                         enable-method = "psci";
 104                         next-level-cache = <&A53_L2>;
 105                         clocks = <&scpi_dvfs 1>;
 106                 };
 107
 108                 A53_3: cpu@103 {
 109                         compatible = "arm,cortex-a53","arm,armv8";
 110                         reg = <0x0 0x103>;
 111                         device_type = "cpu";
 112                         enable-method = "psci";
 113                         next-level-cache = <&A53_L2>;
 114                         clocks = <&scpi_dvfs 1>;
 115                 };
 116
 117                 A57_L2: l2-cache0 {
 118                         compatible = "cache";
 119                 };
 120
 121                 A53_L2: l2-cache1 {
 122                         compatible = "cache";
 123                 };
 124         };
 125
 126         pmu_a57 {
 127                 compatible = "arm,cortex-a57-pmu";
 128                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
 130                 interrupt-affinity = <&A57_0>,
 131                                      <&A57_1>;
 132         };
 133
 134         pmu_a53 {
 135                 compatible = "arm,cortex-a53-pmu";
 136                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 137                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 138                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 139                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 140                 interrupt-affinity = <&A53_0>,
 141                                      <&A53_1>,
 142                                      <&A53_2>,
 143                                      <&A53_3>;
 144         };
 145
 146         #include "juno-base.dtsi"
 147 };