arch/arm64/boot/dts/arm/juno.dts

   1 /*
   2  * ARM Ltd. Juno Platform
   3  *
   4  * Copyright (c) 2013-2014 ARM Ltd.
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12
  13 / {
  14         model = "ARM Juno development board (r0)";
  15         compatible = "arm,juno", "arm,vexpress";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &soc_uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 cpu-map {
  38                         cluster0 {
  39                                 core0 {
  40                                         cpu = <&A57_0>;
  41                                 };
  42                                 core1 {
  43                                         cpu = <&A57_1>;
  44                                 };
  45                         };
  46
  47                         cluster1 {
  48                                 core0 {
  49                                         cpu = <&A53_0>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&A53_1>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&A53_2>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&A53_3>;
  59                                 };
  60                         };
  61                 };
  62
  63                 idle-states {
  64                         entry-method = "arm,psci";
  65
  66                         CPU_SLEEP_0: cpu-sleep-0 {
  67                                 compatible = "arm,idle-state";
  68                                 arm,psci-suspend-param = <0x0010000>;
  69                                 local-timer-stop;
  70                                 entry-latency-us = <300>;
  71                                 exit-latency-us = <1200>;
  72                                 min-residency-us = <2000>;
  73                         };
  74
  75                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  76                                 compatible = "arm,idle-state";
  77                                 arm,psci-suspend-param = <0x1010000>;
  78                                 local-timer-stop;
  79                                 entry-latency-us = <400>;
  80                                 exit-latency-us = <1200>;
  81                                 min-residency-us = <2500>;
  82                         };
  83                 };
  84
  85                 A57_0: cpu@0 {
  86                         compatible = "arm,cortex-a57","arm,armv8";
  87                         reg = <0x0 0x0>;
  88                         device_type = "cpu";
  89                         enable-method = "psci";
  90                         next-level-cache = <&A57_L2>;
  91                         clocks = <&scpi_dvfs 0>;
  92                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  93                         capacity-dmips-mhz = <1024>;
  94                 };
  95
  96                 A57_1: cpu@1 {
  97                         compatible = "arm,cortex-a57","arm,armv8";
  98                         reg = <0x0 0x1>;
  99                         device_type = "cpu";
 100                         enable-method = "psci";
 101                         next-level-cache = <&A57_L2>;
 102                         clocks = <&scpi_dvfs 0>;
 103                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 104                         capacity-dmips-mhz = <1024>;
 105                 };
 106
 107                 A53_0: cpu@100 {
 108                         compatible = "arm,cortex-a53","arm,armv8";
 109                         reg = <0x0 0x100>;
 110                         device_type = "cpu";
 111                         enable-method = "psci";
 112                         next-level-cache = <&A53_L2>;
 113                         clocks = <&scpi_dvfs 1>;
 114                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 115                         capacity-dmips-mhz = <578>;
 116                 };
 117
 118                 A53_1: cpu@101 {
 119                         compatible = "arm,cortex-a53","arm,armv8";
 120                         reg = <0x0 0x101>;
 121                         device_type = "cpu";
 122                         enable-method = "psci";
 123                         next-level-cache = <&A53_L2>;
 124                         clocks = <&scpi_dvfs 1>;
 125                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 126                         capacity-dmips-mhz = <578>;
 127                 };
 128
 129                 A53_2: cpu@102 {
 130                         compatible = "arm,cortex-a53","arm,armv8";
 131                         reg = <0x0 0x102>;
 132                         device_type = "cpu";
 133                         enable-method = "psci";
 134                         next-level-cache = <&A53_L2>;
 135                         clocks = <&scpi_dvfs 1>;
 136                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 137                         capacity-dmips-mhz = <578>;
 138                 };
 139
 140                 A53_3: cpu@103 {
 141                         compatible = "arm,cortex-a53","arm,armv8";
 142                         reg = <0x0 0x103>;
 143                         device_type = "cpu";
 144                         enable-method = "psci";
 145                         next-level-cache = <&A53_L2>;
 146                         clocks = <&scpi_dvfs 1>;
 147                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 148                         capacity-dmips-mhz = <578>;
 149                 };
 150
 151                 A57_L2: l2-cache0 {
 152                         compatible = "cache";
 153                 };
 154
 155                 A53_L2: l2-cache1 {
 156                         compatible = "cache";
 157                 };
 158         };
 159
 160         pmu_a57 {
 161                 compatible = "arm,cortex-a57-pmu";
 162                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
 164                 interrupt-affinity = <&A57_0>,
 165                                      <&A57_1>;
 166         };
 167
 168         pmu_a53 {
 169                 compatible = "arm,cortex-a53-pmu";
 170                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 174                 interrupt-affinity = <&A53_0>,
 175                                      <&A53_1>,
 176                                      <&A53_2>,
 177                                      <&A53_3>;
 178         };
 179
 180         #include "juno-base.dtsi"
 181 };
 182
 183 &etm0 {
 184         cpu = <&A57_0>;
 185 };
 186
 187 &etm1 {
 188         cpu = <&A57_1>;
 189 };
 190
 191 &etm2 {
 192         cpu = <&A53_0>;
 193 };
 194
 195 &etm3 {
 196         cpu = <&A53_1>;
 197 };
 198
 199 &etm4 {
 200         cpu = <&A53_2>;
 201 };
 202
 203 &etm5 {
 204         cpu = <&A53_3>;
 205 };