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arm64: dts: exynos: Move syscon poweroff and restart nodes under the PMU
[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / exynos / exynos5433.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos5433 SoC device tree source
4 *
5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 *
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
9 * values for board specific bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
13 * additional nodes can be added to this file.
14 */
15
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18
19 / {
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 interrupt-parent = <&gic>;
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu0: cpu@100 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a53", "arm,armv8";
33 enable-method = "psci";
34 reg = <0x100>;
35 clock-frequency = <1300000000>;
36 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
37 clock-names = "apolloclk";
38 operating-points-v2 = <&cluster_a53_opp_table>;
39 #cooling-cells = <2>;
40 };
41
42 cpu1: cpu@101 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a53", "arm,armv8";
45 enable-method = "psci";
46 reg = <0x101>;
47 clock-frequency = <1300000000>;
48 operating-points-v2 = <&cluster_a53_opp_table>;
49 #cooling-cells = <2>;
50 };
51
52 cpu2: cpu@102 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 reg = <0x102>;
57 clock-frequency = <1300000000>;
58 operating-points-v2 = <&cluster_a53_opp_table>;
59 #cooling-cells = <2>;
60 };
61
62 cpu3: cpu@103 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a53", "arm,armv8";
65 enable-method = "psci";
66 reg = <0x103>;
67 clock-frequency = <1300000000>;
68 operating-points-v2 = <&cluster_a53_opp_table>;
69 #cooling-cells = <2>;
70 };
71
72 cpu4: cpu@0 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a57", "arm,armv8";
75 enable-method = "psci";
76 reg = <0x0>;
77 clock-frequency = <1900000000>;
78 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
79 clock-names = "atlasclk";
80 operating-points-v2 = <&cluster_a57_opp_table>;
81 #cooling-cells = <2>;
82 };
83
84 cpu5: cpu@1 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a57", "arm,armv8";
87 enable-method = "psci";
88 reg = <0x1>;
89 clock-frequency = <1900000000>;
90 operating-points-v2 = <&cluster_a57_opp_table>;
91 #cooling-cells = <2>;
92 };
93
94 cpu6: cpu@2 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a57", "arm,armv8";
97 enable-method = "psci";
98 reg = <0x2>;
99 clock-frequency = <1900000000>;
100 operating-points-v2 = <&cluster_a57_opp_table>;
101 #cooling-cells = <2>;
102 };
103
104 cpu7: cpu@3 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a57", "arm,armv8";
107 enable-method = "psci";
108 reg = <0x3>;
109 clock-frequency = <1900000000>;
110 operating-points-v2 = <&cluster_a57_opp_table>;
111 #cooling-cells = <2>;
112 };
113 };
114
115 cluster_a53_opp_table: opp_table0 {
116 compatible = "operating-points-v2";
117 opp-shared;
118
119 opp-400000000 {
120 opp-hz = /bits/ 64 <400000000>;
121 opp-microvolt = <900000>;
122 };
123 opp-500000000 {
124 opp-hz = /bits/ 64 <500000000>;
125 opp-microvolt = <925000>;
126 };
127 opp-600000000 {
128 opp-hz = /bits/ 64 <600000000>;
129 opp-microvolt = <950000>;
130 };
131 opp-700000000 {
132 opp-hz = /bits/ 64 <700000000>;
133 opp-microvolt = <975000>;
134 };
135 opp-800000000 {
136 opp-hz = /bits/ 64 <800000000>;
137 opp-microvolt = <1000000>;
138 };
139 opp-900000000 {
140 opp-hz = /bits/ 64 <900000000>;
141 opp-microvolt = <1050000>;
142 };
143 opp-1000000000 {
144 opp-hz = /bits/ 64 <1000000000>;
145 opp-microvolt = <1075000>;
146 };
147 opp-1100000000 {
148 opp-hz = /bits/ 64 <1100000000>;
149 opp-microvolt = <1112500>;
150 };
151 opp-1200000000 {
152 opp-hz = /bits/ 64 <1200000000>;
153 opp-microvolt = <1112500>;
154 };
155 opp-1300000000 {
156 opp-hz = /bits/ 64 <1300000000>;
157 opp-microvolt = <1150000>;
158 };
159 };
160
161 cluster_a57_opp_table: opp_table1 {
162 compatible = "operating-points-v2";
163 opp-shared;
164
165 opp-500000000 {
166 opp-hz = /bits/ 64 <500000000>;
167 opp-microvolt = <900000>;
168 };
169 opp-600000000 {
170 opp-hz = /bits/ 64 <600000000>;
171 opp-microvolt = <900000>;
172 };
173 opp-700000000 {
174 opp-hz = /bits/ 64 <700000000>;
175 opp-microvolt = <912500>;
176 };
177 opp-800000000 {
178 opp-hz = /bits/ 64 <800000000>;
179 opp-microvolt = <912500>;
180 };
181 opp-900000000 {
182 opp-hz = /bits/ 64 <900000000>;
183 opp-microvolt = <937500>;
184 };
185 opp-1000000000 {
186 opp-hz = /bits/ 64 <1000000000>;
187 opp-microvolt = <975000>;
188 };
189 opp-1100000000 {
190 opp-hz = /bits/ 64 <1100000000>;
191 opp-microvolt = <1012500>;
192 };
193 opp-1200000000 {
194 opp-hz = /bits/ 64 <1200000000>;
195 opp-microvolt = <1037500>;
196 };
197 opp-1300000000 {
198 opp-hz = /bits/ 64 <1300000000>;
199 opp-microvolt = <1062500>;
200 };
201 opp-1400000000 {
202 opp-hz = /bits/ 64 <1400000000>;
203 opp-microvolt = <1087500>;
204 };
205 opp-1500000000 {
206 opp-hz = /bits/ 64 <1500000000>;
207 opp-microvolt = <1125000>;
208 };
209 opp-1600000000 {
210 opp-hz = /bits/ 64 <1600000000>;
211 opp-microvolt = <1137500>;
212 };
213 opp-1700000000 {
214 opp-hz = /bits/ 64 <1700000000>;
215 opp-microvolt = <1175000>;
216 };
217 opp-1800000000 {
218 opp-hz = /bits/ 64 <1800000000>;
219 opp-microvolt = <1212500>;
220 };
221 opp-1900000000 {
222 opp-hz = /bits/ 64 <1900000000>;
223 opp-microvolt = <1262500>;
224 };
225 };
226
227 psci {
228 compatible = "arm,psci";
229 method = "smc";
230 cpu_off = <0x84000002>;
231 cpu_on = <0xC4000003>;
232 };
233
234 soc: soc {
235 compatible = "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges = <0x0 0x0 0x0 0x18000000>;
239
240 arm_a53_pmu {
241 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
242 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
246 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
247 };
248
249 arm_a57_pmu {
250 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
251 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
255 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
256 };
257
258 chipid@10000000 {
259 compatible = "samsung,exynos4210-chipid";
260 reg = <0x10000000 0x100>;
261 };
262
263 xxti: xxti {
264 compatible = "fixed-clock";
265 clock-output-names = "oscclk";
266 #clock-cells = <0>;
267 };
268
269 cmu_top: clock-controller@10030000 {
270 compatible = "samsung,exynos5433-cmu-top";
271 reg = <0x10030000 0x1000>;
272 #clock-cells = <1>;
273
274 clock-names = "oscclk",
275 "sclk_mphy_pll",
276 "sclk_mfc_pll",
277 "sclk_bus_pll";
278 clocks = <&xxti>,
279 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
280 <&cmu_mif CLK_SCLK_MFC_PLL>,
281 <&cmu_mif CLK_SCLK_BUS_PLL>;
282 };
283
284 cmu_cpif: clock-controller@10fc0000 {
285 compatible = "samsung,exynos5433-cmu-cpif";
286 reg = <0x10fc0000 0x1000>;
287 #clock-cells = <1>;
288
289 clock-names = "oscclk";
290 clocks = <&xxti>;
291 };
292
293 cmu_mif: clock-controller@105b0000 {
294 compatible = "samsung,exynos5433-cmu-mif";
295 reg = <0x105b0000 0x2000>;
296 #clock-cells = <1>;
297
298 clock-names = "oscclk",
299 "sclk_mphy_pll";
300 clocks = <&xxti>,
301 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
302 };
303
304 cmu_peric: clock-controller@14c80000 {
305 compatible = "samsung,exynos5433-cmu-peric";
306 reg = <0x14c80000 0x1000>;
307 #clock-cells = <1>;
308 };
309
310 cmu_peris: clock-controller@10040000 {
311 compatible = "samsung,exynos5433-cmu-peris";
312 reg = <0x10040000 0x1000>;
313 #clock-cells = <1>;
314 };
315
316 cmu_fsys: clock-controller@156e0000 {
317 compatible = "samsung,exynos5433-cmu-fsys";
318 reg = <0x156e0000 0x1000>;
319 #clock-cells = <1>;
320
321 clock-names = "oscclk",
322 "sclk_ufs_mphy",
323 "aclk_fsys_200",
324 "sclk_pcie_100_fsys",
325 "sclk_ufsunipro_fsys",
326 "sclk_mmc2_fsys",
327 "sclk_mmc1_fsys",
328 "sclk_mmc0_fsys",
329 "sclk_usbhost30_fsys",
330 "sclk_usbdrd30_fsys";
331 clocks = <&xxti>,
332 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
333 <&cmu_top CLK_ACLK_FSYS_200>,
334 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
335 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
336 <&cmu_top CLK_SCLK_MMC2_FSYS>,
337 <&cmu_top CLK_SCLK_MMC1_FSYS>,
338 <&cmu_top CLK_SCLK_MMC0_FSYS>,
339 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
340 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
341 };
342
343 cmu_g2d: clock-controller@12460000 {
344 compatible = "samsung,exynos5433-cmu-g2d";
345 reg = <0x12460000 0x1000>;
346 #clock-cells = <1>;
347
348 clock-names = "oscclk",
349 "aclk_g2d_266",
350 "aclk_g2d_400";
351 clocks = <&xxti>,
352 <&cmu_top CLK_ACLK_G2D_266>,
353 <&cmu_top CLK_ACLK_G2D_400>;
354 power-domains = <&pd_g2d>;
355 };
356
357 cmu_disp: clock-controller@13b90000 {
358 compatible = "samsung,exynos5433-cmu-disp";
359 reg = <0x13b90000 0x1000>;
360 #clock-cells = <1>;
361
362 clock-names = "oscclk",
363 "sclk_dsim1_disp",
364 "sclk_dsim0_disp",
365 "sclk_dsd_disp",
366 "sclk_decon_tv_eclk_disp",
367 "sclk_decon_vclk_disp",
368 "sclk_decon_eclk_disp",
369 "sclk_decon_tv_vclk_disp",
370 "aclk_disp_333";
371 clocks = <&xxti>,
372 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
373 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
374 <&cmu_mif CLK_SCLK_DSD_DISP>,
375 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
376 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
377 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
378 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
379 <&cmu_mif CLK_ACLK_DISP_333>;
380 power-domains = <&pd_disp>;
381 };
382
383 cmu_aud: clock-controller@114c0000 {
384 compatible = "samsung,exynos5433-cmu-aud";
385 reg = <0x114c0000 0x1000>;
386 #clock-cells = <1>;
387 clock-names = "oscclk", "fout_aud_pll";
388 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
389 power-domains = <&pd_aud>;
390 };
391
392 cmu_bus0: clock-controller@13600000 {
393 compatible = "samsung,exynos5433-cmu-bus0";
394 reg = <0x13600000 0x1000>;
395 #clock-cells = <1>;
396
397 clock-names = "aclk_bus0_400";
398 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
399 };
400
401 cmu_bus1: clock-controller@14800000 {
402 compatible = "samsung,exynos5433-cmu-bus1";
403 reg = <0x14800000 0x1000>;
404 #clock-cells = <1>;
405
406 clock-names = "aclk_bus1_400";
407 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
408 };
409
410 cmu_bus2: clock-controller@13400000 {
411 compatible = "samsung,exynos5433-cmu-bus2";
412 reg = <0x13400000 0x1000>;
413 #clock-cells = <1>;
414
415 clock-names = "oscclk", "aclk_bus2_400";
416 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
417 };
418
419 cmu_g3d: clock-controller@14aa0000 {
420 compatible = "samsung,exynos5433-cmu-g3d";
421 reg = <0x14aa0000 0x2000>;
422 #clock-cells = <1>;
423
424 clock-names = "oscclk", "aclk_g3d_400";
425 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
426 power-domains = <&pd_g3d>;
427 };
428
429 cmu_gscl: clock-controller@13cf0000 {
430 compatible = "samsung,exynos5433-cmu-gscl";
431 reg = <0x13cf0000 0x1000>;
432 #clock-cells = <1>;
433
434 clock-names = "oscclk",
435 "aclk_gscl_111",
436 "aclk_gscl_333";
437 clocks = <&xxti>,
438 <&cmu_top CLK_ACLK_GSCL_111>,
439 <&cmu_top CLK_ACLK_GSCL_333>;
440 power-domains = <&pd_gscl>;
441 };
442
443 cmu_apollo: clock-controller@11900000 {
444 compatible = "samsung,exynos5433-cmu-apollo";
445 reg = <0x11900000 0x2000>;
446 #clock-cells = <1>;
447
448 clock-names = "oscclk", "sclk_bus_pll_apollo";
449 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
450 };
451
452 cmu_atlas: clock-controller@11800000 {
453 compatible = "samsung,exynos5433-cmu-atlas";
454 reg = <0x11800000 0x2000>;
455 #clock-cells = <1>;
456
457 clock-names = "oscclk", "sclk_bus_pll_atlas";
458 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
459 };
460
461 cmu_mscl: clock-controller@150d0000 {
462 compatible = "samsung,exynos5433-cmu-mscl";
463 reg = <0x150d0000 0x1000>;
464 #clock-cells = <1>;
465
466 clock-names = "oscclk",
467 "sclk_jpeg_mscl",
468 "aclk_mscl_400";
469 clocks = <&xxti>,
470 <&cmu_top CLK_SCLK_JPEG_MSCL>,
471 <&cmu_top CLK_ACLK_MSCL_400>;
472 power-domains = <&pd_mscl>;
473 };
474
475 cmu_mfc: clock-controller@15280000 {
476 compatible = "samsung,exynos5433-cmu-mfc";
477 reg = <0x15280000 0x1000>;
478 #clock-cells = <1>;
479
480 clock-names = "oscclk", "aclk_mfc_400";
481 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
482 power-domains = <&pd_mfc>;
483 };
484
485 cmu_hevc: clock-controller@14f80000 {
486 compatible = "samsung,exynos5433-cmu-hevc";
487 reg = <0x14f80000 0x1000>;
488 #clock-cells = <1>;
489
490 clock-names = "oscclk", "aclk_hevc_400";
491 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
492 power-domains = <&pd_hevc>;
493 };
494
495 cmu_isp: clock-controller@146d0000 {
496 compatible = "samsung,exynos5433-cmu-isp";
497 reg = <0x146d0000 0x1000>;
498 #clock-cells = <1>;
499
500 clock-names = "oscclk",
501 "aclk_isp_dis_400",
502 "aclk_isp_400";
503 clocks = <&xxti>,
504 <&cmu_top CLK_ACLK_ISP_DIS_400>,
505 <&cmu_top CLK_ACLK_ISP_400>;
506 power-domains = <&pd_isp>;
507 };
508
509 cmu_cam0: clock-controller@120d0000 {
510 compatible = "samsung,exynos5433-cmu-cam0";
511 reg = <0x120d0000 0x1000>;
512 #clock-cells = <1>;
513
514 clock-names = "oscclk",
515 "aclk_cam0_333",
516 "aclk_cam0_400",
517 "aclk_cam0_552";
518 clocks = <&xxti>,
519 <&cmu_top CLK_ACLK_CAM0_333>,
520 <&cmu_top CLK_ACLK_CAM0_400>,
521 <&cmu_top CLK_ACLK_CAM0_552>;
522 power-domains = <&pd_cam0>;
523 };
524
525 cmu_cam1: clock-controller@145d0000 {
526 compatible = "samsung,exynos5433-cmu-cam1";
527 reg = <0x145d0000 0x1000>;
528 #clock-cells = <1>;
529
530 clock-names = "oscclk",
531 "sclk_isp_uart_cam1",
532 "sclk_isp_spi1_cam1",
533 "sclk_isp_spi0_cam1",
534 "aclk_cam1_333",
535 "aclk_cam1_400",
536 "aclk_cam1_552";
537 clocks = <&xxti>,
538 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
539 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
540 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
541 <&cmu_top CLK_ACLK_CAM1_333>,
542 <&cmu_top CLK_ACLK_CAM1_400>,
543 <&cmu_top CLK_ACLK_CAM1_552>;
544 power-domains = <&pd_cam1>;
545 };
546
547 pd_gscl: power-domain@105c4000 {
548 compatible = "samsung,exynos5433-pd";
549 reg = <0x105c4000 0x20>;
550 #power-domain-cells = <0>;
551 label = "GSCL";
552 };
553
554 pd_cam0: power-domain@105c4020 {
555 compatible = "samsung,exynos5433-pd";
556 reg = <0x105c4020 0x20>;
557 #power-domain-cells = <0>;
558 power-domains = <&pd_cam1>;
559 label = "CAM0";
560 };
561
562 pd_mscl: power-domain@105c4040 {
563 compatible = "samsung,exynos5433-pd";
564 reg = <0x105c4040 0x20>;
565 #power-domain-cells = <0>;
566 label = "MSCL";
567 };
568
569 pd_g3d: power-domain@105c4060 {
570 compatible = "samsung,exynos5433-pd";
571 reg = <0x105c4060 0x20>;
572 #power-domain-cells = <0>;
573 label = "G3D";
574 };
575
576 pd_disp: power-domain@105c4080 {
577 compatible = "samsung,exynos5433-pd";
578 reg = <0x105c4080 0x20>;
579 #power-domain-cells = <0>;
580 label = "DISP";
581 };
582
583 pd_cam1: power-domain@105c40a0 {
584 compatible = "samsung,exynos5433-pd";
585 reg = <0x105c40a0 0x20>;
586 #power-domain-cells = <0>;
587 label = "CAM1";
588 };
589
590 pd_aud: power-domain@105c40c0 {
591 compatible = "samsung,exynos5433-pd";
592 reg = <0x105c40c0 0x20>;
593 #power-domain-cells = <0>;
594 label = "AUD";
595 };
596
597 pd_g2d: power-domain@105c4120 {
598 compatible = "samsung,exynos5433-pd";
599 reg = <0x105c4120 0x20>;
600 #power-domain-cells = <0>;
601 label = "G2D";
602 };
603
604 pd_isp: power-domain@105c4140 {
605 compatible = "samsung,exynos5433-pd";
606 reg = <0x105c4140 0x20>;
607 #power-domain-cells = <0>;
608 power-domains = <&pd_cam0>;
609 label = "ISP";
610 };
611
612 pd_mfc: power-domain@105c4180 {
613 compatible = "samsung,exynos5433-pd";
614 reg = <0x105c4180 0x20>;
615 #power-domain-cells = <0>;
616 label = "MFC";
617 };
618
619 pd_hevc: power-domain@105c41c0 {
620 compatible = "samsung,exynos5433-pd";
621 reg = <0x105c41c0 0x20>;
622 #power-domain-cells = <0>;
623 label = "HEVC";
624 };
625
626 tmu_atlas0: tmu@10060000 {
627 compatible = "samsung,exynos5433-tmu";
628 reg = <0x10060000 0x200>;
629 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
631 <&cmu_peris CLK_SCLK_TMU0>;
632 clock-names = "tmu_apbif", "tmu_sclk";
633 #include "exynos5433-tmu-sensor-conf.dtsi"
634 status = "disabled";
635 };
636
637 tmu_atlas1: tmu@10068000 {
638 compatible = "samsung,exynos5433-tmu";
639 reg = <0x10068000 0x200>;
640 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
642 <&cmu_peris CLK_SCLK_TMU0>;
643 clock-names = "tmu_apbif", "tmu_sclk";
644 #include "exynos5433-tmu-sensor-conf.dtsi"
645 status = "disabled";
646 };
647
648 tmu_g3d: tmu@10070000 {
649 compatible = "samsung,exynos5433-tmu";
650 reg = <0x10070000 0x200>;
651 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
653 <&cmu_peris CLK_SCLK_TMU1>;
654 clock-names = "tmu_apbif", "tmu_sclk";
655 #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
656 status = "disabled";
657 };
658
659 tmu_apollo: tmu@10078000 {
660 compatible = "samsung,exynos5433-tmu";
661 reg = <0x10078000 0x200>;
662 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
664 <&cmu_peris CLK_SCLK_TMU1>;
665 clock-names = "tmu_apbif", "tmu_sclk";
666 #include "exynos5433-tmu-sensor-conf.dtsi"
667 status = "disabled";
668 };
669
670 tmu_isp: tmu@1007c000 {
671 compatible = "samsung,exynos5433-tmu";
672 reg = <0x1007c000 0x200>;
673 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
675 <&cmu_peris CLK_SCLK_TMU1>;
676 clock-names = "tmu_apbif", "tmu_sclk";
677 #include "exynos5433-tmu-sensor-conf.dtsi"
678 status = "disabled";
679 };
680
681 mct@101c0000 {
682 compatible = "samsung,exynos4210-mct";
683 reg = <0x101c0000 0x800>;
684 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
697 clock-names = "fin_pll", "mct";
698 };
699
700 ppmu_d0_cpu: ppmu@10480000 {
701 compatible = "samsung,exynos-ppmu-v2";
702 reg = <0x10480000 0x2000>;
703 status = "disabled";
704 };
705
706 ppmu_d0_general: ppmu@10490000 {
707 compatible = "samsung,exynos-ppmu-v2";
708 reg = <0x10490000 0x2000>;
709 status = "disabled";
710 };
711
712 ppmu_d1_cpu: ppmu@104b0000 {
713 compatible = "samsung,exynos-ppmu-v2";
714 reg = <0x104b0000 0x2000>;
715 status = "disabled";
716 };
717
718 ppmu_d1_general: ppmu@104c0000 {
719 compatible = "samsung,exynos-ppmu-v2";
720 reg = <0x104c0000 0x2000>;
721 status = "disabled";
722 };
723
724 pinctrl_alive: pinctrl@10580000 {
725 compatible = "samsung,exynos5433-pinctrl";
726 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
727
728 wakeup-interrupt-controller {
729 compatible = "samsung,exynos7-wakeup-eint";
730 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
731 };
732 };
733
734 pinctrl_aud: pinctrl@114b0000 {
735 compatible = "samsung,exynos5433-pinctrl";
736 reg = <0x114b0000 0x1000>;
737 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
738 power-domains = <&pd_aud>;
739 };
740
741 pinctrl_cpif: pinctrl@10fe0000 {
742 compatible = "samsung,exynos5433-pinctrl";
743 reg = <0x10fe0000 0x1000>;
744 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
745 };
746
747 pinctrl_ese: pinctrl@14ca0000 {
748 compatible = "samsung,exynos5433-pinctrl";
749 reg = <0x14ca0000 0x1000>;
750 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
751 };
752
753 pinctrl_finger: pinctrl@14cb0000 {
754 compatible = "samsung,exynos5433-pinctrl";
755 reg = <0x14cb0000 0x1000>;
756 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
757 };
758
759 pinctrl_fsys: pinctrl@15690000 {
760 compatible = "samsung,exynos5433-pinctrl";
761 reg = <0x15690000 0x1000>;
762 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
763 };
764
765 pinctrl_imem: pinctrl@11090000 {
766 compatible = "samsung,exynos5433-pinctrl";
767 reg = <0x11090000 0x1000>;
768 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
769 };
770
771 pinctrl_nfc: pinctrl@14cd0000 {
772 compatible = "samsung,exynos5433-pinctrl";
773 reg = <0x14cd0000 0x1000>;
774 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
775 };
776
777 pinctrl_peric: pinctrl@14cc0000 {
778 compatible = "samsung,exynos5433-pinctrl";
779 reg = <0x14cc0000 0x1100>;
780 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
781 };
782
783 pinctrl_touch: pinctrl@14ce0000 {
784 compatible = "samsung,exynos5433-pinctrl";
785 reg = <0x14ce0000 0x1100>;
786 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
787 };
788
789 pmu_system_controller: system-controller@105c0000 {
790 compatible = "samsung,exynos5433-pmu", "syscon";
791 reg = <0x105c0000 0x5008>;
792 #clock-cells = <1>;
793 clock-names = "clkout16";
794 clocks = <&xxti>;
795
796 reboot: syscon-reboot {
797 compatible = "syscon-reboot";
798 regmap = <&pmu_system_controller>;
799 offset = <0x400>; /* SWRESET */
800 mask = <0x1>;
801 };
802 };
803
804 gic: interrupt-controller@11001000 {
805 compatible = "arm,gic-400";
806 #interrupt-cells = <3>;
807 interrupt-controller;
808 reg = <0x11001000 0x1000>,
809 <0x11002000 0x2000>,
810 <0x11004000 0x2000>,
811 <0x11006000 0x2000>;
812 interrupts = <GIC_PPI 9 0xf04>;
813 };
814
815 mipi_phy: video-phy {
816 compatible = "samsung,exynos5433-mipi-video-phy";
817 #phy-cells = <1>;
818 samsung,pmu-syscon = <&pmu_system_controller>;
819 samsung,cam0-sysreg = <&syscon_cam0>;
820 samsung,cam1-sysreg = <&syscon_cam1>;
821 samsung,disp-sysreg = <&syscon_disp>;
822 };
823
824 decon: decon@13800000 {
825 compatible = "samsung,exynos5433-decon";
826 reg = <0x13800000 0x2104>;
827 clocks = <&cmu_disp CLK_PCLK_DECON>,
828 <&cmu_disp CLK_ACLK_DECON>,
829 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
830 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
831 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
832 <&cmu_disp CLK_SCLK_DECON_VCLK>,
833 <&cmu_disp CLK_SCLK_DECON_ECLK>;
834 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
835 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
836 "sclk_decon_vclk", "sclk_decon_eclk";
837 power-domains = <&pd_disp>;
838 interrupt-names = "fifo", "vsync", "lcd_sys";
839 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
842 samsung,disp-sysreg = <&syscon_disp>;
843 status = "disabled";
844 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
845 iommu-names = "m0", "m1";
846
847 ports {
848 #address-cells = <1>;
849 #size-cells = <0>;
850
851 port@0 {
852 reg = <0>;
853 decon_to_mic: endpoint {
854 remote-endpoint =
855 <&mic_to_decon>;
856 };
857 };
858 };
859 };
860
861 decon_tv: decon@13880000 {
862 compatible = "samsung,exynos5433-decon-tv";
863 reg = <0x13880000 0x20b8>;
864 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
865 <&cmu_disp CLK_ACLK_DECON_TV>,
866 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
867 <&cmu_disp CLK_ACLK_XIU_TV0X>,
868 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
869 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
870 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
871 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
872 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
873 "sclk_decon_vclk", "sclk_decon_eclk";
874 samsung,disp-sysreg = <&syscon_disp>;
875 power-domains = <&pd_disp>;
876 interrupt-names = "fifo", "vsync", "lcd_sys";
877 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
879 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
880 status = "disabled";
881 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
882 iommu-names = "m0", "m1";
883 };
884
885 dsi: dsi@13900000 {
886 compatible = "samsung,exynos5433-mipi-dsi";
887 reg = <0x13900000 0xC0>;
888 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
889 phys = <&mipi_phy 1>;
890 phy-names = "dsim";
891 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
892 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
893 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
894 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
895 <&cmu_disp CLK_SCLK_DSIM0>;
896 clock-names = "bus_clk",
897 "phyclk_mipidphy0_bitclkdiv8",
898 "phyclk_mipidphy0_rxclkesc0",
899 "sclk_rgb_vclk_to_dsim0",
900 "sclk_mipi";
901 power-domains = <&pd_disp>;
902 status = "disabled";
903 #address-cells = <1>;
904 #size-cells = <0>;
905
906 ports {
907 #address-cells = <1>;
908 #size-cells = <0>;
909
910 port@0 {
911 reg = <0>;
912 dsi_to_mic: endpoint {
913 remote-endpoint = <&mic_to_dsi>;
914 };
915 };
916 };
917 };
918
919 mic: mic@13930000 {
920 compatible = "samsung,exynos5433-mic";
921 reg = <0x13930000 0x48>;
922 clocks = <&cmu_disp CLK_PCLK_MIC0>,
923 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
924 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
925 power-domains = <&pd_disp>;
926 samsung,disp-syscon = <&syscon_disp>;
927 status = "disabled";
928
929 ports {
930 #address-cells = <1>;
931 #size-cells = <0>;
932
933 port@0 {
934 reg = <0>;
935 mic_to_decon: endpoint {
936 remote-endpoint =
937 <&decon_to_mic>;
938 };
939 };
940
941 port@1 {
942 reg = <1>;
943 mic_to_dsi: endpoint {
944 remote-endpoint = <&dsi_to_mic>;
945 };
946 };
947 };
948 };
949
950 hdmi: hdmi@13970000 {
951 compatible = "samsung,exynos5433-hdmi";
952 reg = <0x13970000 0x70000>;
953 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&cmu_disp CLK_PCLK_HDMI>,
955 <&cmu_disp CLK_PCLK_HDMIPHY>,
956 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
957 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
958 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
959 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
960 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
961 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
962 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
963 clock-names = "hdmi_pclk", "hdmi_i_pclk",
964 "i_tmds_clk", "i_pixel_clk",
965 "tmds_clko", "tmds_clko_user",
966 "pixel_clko", "pixel_clko_user",
967 "oscclk", "i_spdif_clk";
968 phy = <&hdmiphy>;
969 ddc = <&hsi2c_11>;
970 samsung,syscon-phandle = <&pmu_system_controller>;
971 samsung,sysreg-phandle = <&syscon_disp>;
972 #sound-dai-cells = <0>;
973 status = "disabled";
974 };
975
976 hdmiphy: hdmiphy@13af0000 {
977 reg = <0x13af0000 0x80>;
978 };
979
980 syscon_disp: syscon@13b80000 {
981 compatible = "syscon";
982 reg = <0x13b80000 0x1010>;
983 };
984
985 syscon_cam0: syscon@120f0000 {
986 compatible = "syscon";
987 reg = <0x120f0000 0x1020>;
988 };
989
990 syscon_cam1: syscon@145f0000 {
991 compatible = "syscon";
992 reg = <0x145f0000 0x1038>;
993 };
994
995 gsc_0: video-scaler@13c00000 {
996 compatible = "samsung,exynos5433-gsc";
997 reg = <0x13c00000 0x1000>;
998 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
999 clock-names = "pclk", "aclk", "aclk_xiu",
1000 "aclk_gsclbend";
1001 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1002 <&cmu_gscl CLK_ACLK_GSCL0>,
1003 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1004 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1005 iommus = <&sysmmu_gscl0>;
1006 power-domains = <&pd_gscl>;
1007 };
1008
1009 gsc_1: video-scaler@13c10000 {
1010 compatible = "samsung,exynos5433-gsc";
1011 reg = <0x13c10000 0x1000>;
1012 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1013 clock-names = "pclk", "aclk", "aclk_xiu",
1014 "aclk_gsclbend";
1015 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1016 <&cmu_gscl CLK_ACLK_GSCL1>,
1017 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1018 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1019 iommus = <&sysmmu_gscl1>;
1020 power-domains = <&pd_gscl>;
1021 };
1022
1023 gsc_2: video-scaler@13c20000 {
1024 compatible = "samsung,exynos5433-gsc";
1025 reg = <0x13c20000 0x1000>;
1026 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1027 clock-names = "pclk", "aclk", "aclk_xiu",
1028 "aclk_gsclbend";
1029 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1030 <&cmu_gscl CLK_ACLK_GSCL2>,
1031 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1032 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1033 iommus = <&sysmmu_gscl2>;
1034 power-domains = <&pd_gscl>;
1035 };
1036
1037 jpeg: codec@15020000 {
1038 compatible = "samsung,exynos5433-jpeg";
1039 reg = <0x15020000 0x10000>;
1040 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1041 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1042 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1043 <&cmu_mscl CLK_ACLK_JPEG>,
1044 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1045 <&cmu_mscl CLK_SCLK_JPEG>;
1046 iommus = <&sysmmu_jpeg>;
1047 power-domains = <&pd_mscl>;
1048 };
1049
1050 mfc: codec@152e0000 {
1051 compatible = "samsung,exynos5433-mfc";
1052 reg = <0x152E0000 0x10000>;
1053 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1054 clock-names = "pclk", "aclk", "aclk_xiu";
1055 clocks = <&cmu_mfc CLK_PCLK_MFC>,
1056 <&cmu_mfc CLK_ACLK_MFC>,
1057 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1058 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1059 iommu-names = "left", "right";
1060 power-domains = <&pd_mfc>;
1061 };
1062
1063 sysmmu_decon0x: sysmmu@13a00000 {
1064 compatible = "samsung,exynos-sysmmu";
1065 reg = <0x13a00000 0x1000>;
1066 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1067 clock-names = "pclk", "aclk";
1068 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
1069 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
1070 power-domains = <&pd_disp>;
1071 #iommu-cells = <0>;
1072 };
1073
1074 sysmmu_decon1x: sysmmu@13a10000 {
1075 compatible = "samsung,exynos-sysmmu";
1076 reg = <0x13a10000 0x1000>;
1077 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1078 clock-names = "pclk", "aclk";
1079 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
1080 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
1081 #iommu-cells = <0>;
1082 power-domains = <&pd_disp>;
1083 };
1084
1085 sysmmu_tv0x: sysmmu@13a20000 {
1086 compatible = "samsung,exynos-sysmmu";
1087 reg = <0x13a20000 0x1000>;
1088 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1089 clock-names = "pclk", "aclk";
1090 clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1091 <&cmu_disp CLK_ACLK_SMMU_TV0X>;
1092 #iommu-cells = <0>;
1093 power-domains = <&pd_disp>;
1094 };
1095
1096 sysmmu_tv1x: sysmmu@13a30000 {
1097 compatible = "samsung,exynos-sysmmu";
1098 reg = <0x13a30000 0x1000>;
1099 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1100 clock-names = "pclk", "aclk";
1101 clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1102 <&cmu_disp CLK_ACLK_SMMU_TV1X>;
1103 #iommu-cells = <0>;
1104 power-domains = <&pd_disp>;
1105 };
1106
1107 sysmmu_gscl0: sysmmu@13c80000 {
1108 compatible = "samsung,exynos-sysmmu";
1109 reg = <0x13C80000 0x1000>;
1110 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1111 clock-names = "aclk", "pclk";
1112 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1113 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1114 #iommu-cells = <0>;
1115 power-domains = <&pd_gscl>;
1116 };
1117
1118 sysmmu_gscl1: sysmmu@13c90000 {
1119 compatible = "samsung,exynos-sysmmu";
1120 reg = <0x13C90000 0x1000>;
1121 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1122 clock-names = "aclk", "pclk";
1123 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1124 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1125 #iommu-cells = <0>;
1126 power-domains = <&pd_gscl>;
1127 };
1128
1129 sysmmu_gscl2: sysmmu@13ca0000 {
1130 compatible = "samsung,exynos-sysmmu";
1131 reg = <0x13CA0000 0x1000>;
1132 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1133 clock-names = "aclk", "pclk";
1134 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1135 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1136 #iommu-cells = <0>;
1137 power-domains = <&pd_gscl>;
1138 };
1139
1140 sysmmu_jpeg: sysmmu@15060000 {
1141 compatible = "samsung,exynos-sysmmu";
1142 reg = <0x15060000 0x1000>;
1143 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1144 clock-names = "pclk", "aclk";
1145 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
1146 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
1147 #iommu-cells = <0>;
1148 power-domains = <&pd_mscl>;
1149 };
1150
1151 sysmmu_mfc_0: sysmmu@15200000 {
1152 compatible = "samsung,exynos-sysmmu";
1153 reg = <0x15200000 0x1000>;
1154 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1155 clock-names = "pclk", "aclk";
1156 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
1157 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
1158 #iommu-cells = <0>;
1159 power-domains = <&pd_mfc>;
1160 };
1161
1162 sysmmu_mfc_1: sysmmu@15210000 {
1163 compatible = "samsung,exynos-sysmmu";
1164 reg = <0x15210000 0x1000>;
1165 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1166 clock-names = "pclk", "aclk";
1167 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
1168 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
1169 #iommu-cells = <0>;
1170 power-domains = <&pd_mfc>;
1171 };
1172
1173 serial_0: serial@14c10000 {
1174 compatible = "samsung,exynos5433-uart";
1175 reg = <0x14c10000 0x100>;
1176 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cmu_peric CLK_PCLK_UART0>,
1178 <&cmu_peric CLK_SCLK_UART0>;
1179 clock-names = "uart", "clk_uart_baud0";
1180 pinctrl-names = "default";
1181 pinctrl-0 = <&uart0_bus>;
1182 status = "disabled";
1183 };
1184
1185 serial_1: serial@14c20000 {
1186 compatible = "samsung,exynos5433-uart";
1187 reg = <0x14c20000 0x100>;
1188 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&cmu_peric CLK_PCLK_UART1>,
1190 <&cmu_peric CLK_SCLK_UART1>;
1191 clock-names = "uart", "clk_uart_baud0";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&uart1_bus>;
1194 status = "disabled";
1195 };
1196
1197 serial_2: serial@14c30000 {
1198 compatible = "samsung,exynos5433-uart";
1199 reg = <0x14c30000 0x100>;
1200 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&cmu_peric CLK_PCLK_UART2>,
1202 <&cmu_peric CLK_SCLK_UART2>;
1203 clock-names = "uart", "clk_uart_baud0";
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&uart2_bus>;
1206 status = "disabled";
1207 };
1208
1209 spi_0: spi@14d20000 {
1210 compatible = "samsung,exynos5433-spi";
1211 reg = <0x14d20000 0x100>;
1212 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1213 dmas = <&pdma0 9>, <&pdma0 8>;
1214 dma-names = "tx", "rx";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 clocks = <&cmu_peric CLK_PCLK_SPI0>,
1218 <&cmu_peric CLK_SCLK_SPI0>,
1219 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1220 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1221 samsung,spi-src-clk = <0>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&spi0_bus>;
1224 num-cs = <1>;
1225 status = "disabled";
1226 };
1227
1228 spi_1: spi@14d30000 {
1229 compatible = "samsung,exynos5433-spi";
1230 reg = <0x14d30000 0x100>;
1231 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1232 dmas = <&pdma0 11>, <&pdma0 10>;
1233 dma-names = "tx", "rx";
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1236 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1237 <&cmu_peric CLK_SCLK_SPI1>,
1238 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1239 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1240 samsung,spi-src-clk = <0>;
1241 pinctrl-names = "default";
1242 pinctrl-0 = <&spi1_bus>;
1243 num-cs = <1>;
1244 status = "disabled";
1245 };
1246
1247 spi_2: spi@14d40000 {
1248 compatible = "samsung,exynos5433-spi";
1249 reg = <0x14d40000 0x100>;
1250 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1251 dmas = <&pdma0 13>, <&pdma0 12>;
1252 dma-names = "tx", "rx";
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1255 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1256 <&cmu_peric CLK_SCLK_SPI2>,
1257 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1258 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1259 samsung,spi-src-clk = <0>;
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&spi2_bus>;
1262 num-cs = <1>;
1263 status = "disabled";
1264 };
1265
1266 spi_3: spi@14d50000 {
1267 compatible = "samsung,exynos5433-spi";
1268 reg = <0x14d50000 0x100>;
1269 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1270 dmas = <&pdma0 23>, <&pdma0 22>;
1271 dma-names = "tx", "rx";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1274 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1275 <&cmu_peric CLK_SCLK_SPI3>,
1276 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1277 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1278 samsung,spi-src-clk = <0>;
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&spi3_bus>;
1281 num-cs = <1>;
1282 status = "disabled";
1283 };
1284
1285 spi_4: spi@14d00000 {
1286 compatible = "samsung,exynos5433-spi";
1287 reg = <0x14d00000 0x100>;
1288 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1289 dmas = <&pdma0 25>, <&pdma0 24>;
1290 dma-names = "tx", "rx";
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1293 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1294 <&cmu_peric CLK_SCLK_SPI4>,
1295 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1296 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1297 samsung,spi-src-clk = <0>;
1298 pinctrl-names = "default";
1299 pinctrl-0 = <&spi4_bus>;
1300 num-cs = <1>;
1301 status = "disabled";
1302 };
1303
1304 adc: adc@14d10000 {
1305 compatible = "samsung,exynos7-adc";
1306 reg = <0x14d10000 0x100>;
1307 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1308 clock-names = "adc";
1309 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1310 #io-channel-cells = <1>;
1311 io-channel-ranges;
1312 status = "disabled";
1313 };
1314
1315 i2s1: i2s@14d60000 {
1316 compatible = "samsung,exynos7-i2s";
1317 reg = <0x14d60000 0x100>;
1318 dmas = <&pdma0 31 &pdma0 30>;
1319 dma-names = "tx", "rx";
1320 interrupts = <GIC_SPI 435 IRQ_TYPE_NONE>;
1321 clocks = <&cmu_peric CLK_PCLK_I2S1>,
1322 <&cmu_peric CLK_PCLK_I2S1>,
1323 <&cmu_peric CLK_SCLK_I2S1>;
1324 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1325 #clock-cells = <1>;
1326 samsung,supports-6ch;
1327 samsung,supports-rstclr;
1328 samsung,supports-tdm;
1329 samsung,supports-low-rfs;
1330 #sound-dai-cells = <1>;
1331 status = "disabled";
1332 };
1333
1334 pwm: pwm@14dd0000 {
1335 compatible = "samsung,exynos4210-pwm";
1336 reg = <0x14dd0000 0x100>;
1337 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1342 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1343 clocks = <&cmu_peric CLK_PCLK_PWM>;
1344 clock-names = "timers";
1345 #pwm-cells = <3>;
1346 status = "disabled";
1347 };
1348
1349 hsi2c_0: hsi2c@14e40000 {
1350 compatible = "samsung,exynos7-hsi2c";
1351 reg = <0x14e40000 0x1000>;
1352 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1355 pinctrl-names = "default";
1356 pinctrl-0 = <&hs_i2c0_bus>;
1357 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1358 clock-names = "hsi2c";
1359 status = "disabled";
1360 };
1361
1362 hsi2c_1: hsi2c@14e50000 {
1363 compatible = "samsung,exynos7-hsi2c";
1364 reg = <0x14e50000 0x1000>;
1365 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&hs_i2c1_bus>;
1370 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1371 clock-names = "hsi2c";
1372 status = "disabled";
1373 };
1374
1375 hsi2c_2: hsi2c@14e60000 {
1376 compatible = "samsung,exynos7-hsi2c";
1377 reg = <0x14e60000 0x1000>;
1378 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1381 pinctrl-names = "default";
1382 pinctrl-0 = <&hs_i2c2_bus>;
1383 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1384 clock-names = "hsi2c";
1385 status = "disabled";
1386 };
1387
1388 hsi2c_3: hsi2c@14e70000 {
1389 compatible = "samsung,exynos7-hsi2c";
1390 reg = <0x14e70000 0x1000>;
1391 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1392 #address-cells = <1>;
1393 #size-cells = <0>;
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&hs_i2c3_bus>;
1396 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1397 clock-names = "hsi2c";
1398 status = "disabled";
1399 };
1400
1401 hsi2c_4: hsi2c@14ec0000 {
1402 compatible = "samsung,exynos7-hsi2c";
1403 reg = <0x14ec0000 0x1000>;
1404 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&hs_i2c4_bus>;
1409 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1410 clock-names = "hsi2c";
1411 status = "disabled";
1412 };
1413
1414 hsi2c_5: hsi2c@14ed0000 {
1415 compatible = "samsung,exynos7-hsi2c";
1416 reg = <0x14ed0000 0x1000>;
1417 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&hs_i2c5_bus>;
1422 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1423 clock-names = "hsi2c";
1424 status = "disabled";
1425 };
1426
1427 hsi2c_6: hsi2c@14ee0000 {
1428 compatible = "samsung,exynos7-hsi2c";
1429 reg = <0x14ee0000 0x1000>;
1430 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&hs_i2c6_bus>;
1435 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1436 clock-names = "hsi2c";
1437 status = "disabled";
1438 };
1439
1440 hsi2c_7: hsi2c@14ef0000 {
1441 compatible = "samsung,exynos7-hsi2c";
1442 reg = <0x14ef0000 0x1000>;
1443 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1446 pinctrl-names = "default";
1447 pinctrl-0 = <&hs_i2c7_bus>;
1448 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1449 clock-names = "hsi2c";
1450 status = "disabled";
1451 };
1452
1453 hsi2c_8: hsi2c@14d90000 {
1454 compatible = "samsung,exynos7-hsi2c";
1455 reg = <0x14d90000 0x1000>;
1456 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1459 pinctrl-names = "default";
1460 pinctrl-0 = <&hs_i2c8_bus>;
1461 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1462 clock-names = "hsi2c";
1463 status = "disabled";
1464 };
1465
1466 hsi2c_9: hsi2c@14da0000 {
1467 compatible = "samsung,exynos7-hsi2c";
1468 reg = <0x14da0000 0x1000>;
1469 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&hs_i2c9_bus>;
1474 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1475 clock-names = "hsi2c";
1476 status = "disabled";
1477 };
1478
1479 hsi2c_10: hsi2c@14de0000 {
1480 compatible = "samsung,exynos7-hsi2c";
1481 reg = <0x14de0000 0x1000>;
1482 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 pinctrl-names = "default";
1486 pinctrl-0 = <&hs_i2c10_bus>;
1487 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1488 clock-names = "hsi2c";
1489 status = "disabled";
1490 };
1491
1492 hsi2c_11: hsi2c@14df0000 {
1493 compatible = "samsung,exynos7-hsi2c";
1494 reg = <0x14df0000 0x1000>;
1495 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 pinctrl-names = "default";
1499 pinctrl-0 = <&hs_i2c11_bus>;
1500 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1501 clock-names = "hsi2c";
1502 status = "disabled";
1503 };
1504
1505 usbdrd30: usbdrd {
1506 compatible = "samsung,exynos5250-dwusb3";
1507 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1508 <&cmu_fsys CLK_SCLK_USBDRD30>;
1509 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1510 #address-cells = <1>;
1511 #size-cells = <1>;
1512 ranges;
1513 status = "disabled";
1514
1515 usbdrd_dwc3: dwc3@15400000 {
1516 compatible = "snps,dwc3";
1517 reg = <0x15400000 0x10000>;
1518 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1519 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1520 phy-names = "usb2-phy", "usb3-phy";
1521 };
1522 };
1523
1524 usbdrd30_phy: phy@15500000 {
1525 compatible = "samsung,exynos5433-usbdrd-phy";
1526 reg = <0x15500000 0x100>;
1527 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1528 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1529 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1530 <&cmu_fsys CLK_SCLK_USBDRD30>;
1531 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1532 "itp";
1533 #phy-cells = <1>;
1534 samsung,pmu-syscon = <&pmu_system_controller>;
1535 status = "disabled";
1536 };
1537
1538 usbhost30_phy: phy@15580000 {
1539 compatible = "samsung,exynos5433-usbdrd-phy";
1540 reg = <0x15580000 0x100>;
1541 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1542 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1543 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1544 <&cmu_fsys CLK_SCLK_USBHOST30>;
1545 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1546 "itp";
1547 #phy-cells = <1>;
1548 samsung,pmu-syscon = <&pmu_system_controller>;
1549 status = "disabled";
1550 };
1551
1552 usbhost30: usbhost {
1553 compatible = "samsung,exynos5250-dwusb3";
1554 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1555 <&cmu_fsys CLK_SCLK_USBHOST30>;
1556 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1557 #address-cells = <1>;
1558 #size-cells = <1>;
1559 ranges;
1560 status = "disabled";
1561
1562 usbhost_dwc3: dwc3@15a00000 {
1563 compatible = "snps,dwc3";
1564 reg = <0x15a00000 0x10000>;
1565 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1566 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1567 phy-names = "usb2-phy", "usb3-phy";
1568 };
1569 };
1570
1571 mshc_0: mshc@15540000 {
1572 compatible = "samsung,exynos7-dw-mshc-smu";
1573 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1574 #address-cells = <1>;
1575 #size-cells = <0>;
1576 reg = <0x15540000 0x2000>;
1577 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1578 <&cmu_fsys CLK_SCLK_MMC0>;
1579 clock-names = "biu", "ciu";
1580 fifo-depth = <0x40>;
1581 status = "disabled";
1582 };
1583
1584 mshc_1: mshc@15550000 {
1585 compatible = "samsung,exynos7-dw-mshc-smu";
1586 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589 reg = <0x15550000 0x2000>;
1590 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1591 <&cmu_fsys CLK_SCLK_MMC1>;
1592 clock-names = "biu", "ciu";
1593 fifo-depth = <0x40>;
1594 status = "disabled";
1595 };
1596
1597 mshc_2: mshc@15560000 {
1598 compatible = "samsung,exynos7-dw-mshc-smu";
1599 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1602 reg = <0x15560000 0x2000>;
1603 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1604 <&cmu_fsys CLK_SCLK_MMC2>;
1605 clock-names = "biu", "ciu";
1606 fifo-depth = <0x40>;
1607 status = "disabled";
1608 };
1609
1610 amba {
1611 compatible = "simple-bus";
1612 #address-cells = <1>;
1613 #size-cells = <1>;
1614 ranges;
1615
1616 pdma0: pdma@15610000 {
1617 compatible = "arm,pl330", "arm,primecell";
1618 reg = <0x15610000 0x1000>;
1619 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1620 clocks = <&cmu_fsys CLK_PDMA0>;
1621 clock-names = "apb_pclk";
1622 #dma-cells = <1>;
1623 #dma-channels = <8>;
1624 #dma-requests = <32>;
1625 };
1626
1627 pdma1: pdma@15600000 {
1628 compatible = "arm,pl330", "arm,primecell";
1629 reg = <0x15600000 0x1000>;
1630 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1631 clocks = <&cmu_fsys CLK_PDMA1>;
1632 clock-names = "apb_pclk";
1633 #dma-cells = <1>;
1634 #dma-channels = <8>;
1635 #dma-requests = <32>;
1636 };
1637 };
1638
1639 audio-subsystem@11400000 {
1640 compatible = "samsung,exynos5433-lpass";
1641 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1642 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1643 clock-names = "sfr0_ctrl";
1644 samsung,pmu-syscon = <&pmu_system_controller>;
1645 power-domains = <&pd_aud>;
1646 #address-cells = <1>;
1647 #size-cells = <1>;
1648 ranges;
1649
1650 adma: adma@11420000 {
1651 compatible = "arm,pl330", "arm,primecell";
1652 reg = <0x11420000 0x1000>;
1653 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1654 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1655 clock-names = "apb_pclk";
1656 #dma-cells = <1>;
1657 #dma-channels = <8>;
1658 #dma-requests = <32>;
1659 power-domains = <&pd_aud>;
1660 };
1661
1662 i2s0: i2s@11440000 {
1663 compatible = "samsung,exynos7-i2s";
1664 reg = <0x11440000 0x100>;
1665 dmas = <&adma 0 &adma 2>;
1666 dma-names = "tx", "rx";
1667 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1671 <&cmu_aud CLK_SCLK_AUD_I2S>,
1672 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1673 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1674 #clock-cells = <1>;
1675 pinctrl-names = "default";
1676 pinctrl-0 = <&i2s0_bus>;
1677 power-domains = <&pd_aud>;
1678 #sound-dai-cells = <1>;
1679 status = "disabled";
1680 };
1681
1682 serial_3: serial@11460000 {
1683 compatible = "samsung,exynos5433-uart";
1684 reg = <0x11460000 0x100>;
1685 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1686 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1687 <&cmu_aud CLK_SCLK_AUD_UART>;
1688 clock-names = "uart", "clk_uart_baud0";
1689 pinctrl-names = "default";
1690 pinctrl-0 = <&uart_aud_bus>;
1691 power-domains = <&pd_aud>;
1692 status = "disabled";
1693 };
1694 };
1695 };
1696
1697 timer: timer {
1698 compatible = "arm,armv8-timer";
1699 interrupts = <GIC_PPI 13
1700 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1701 <GIC_PPI 14
1702 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1703 <GIC_PPI 11
1704 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1705 <GIC_PPI 10
1706 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1707 };
1708 };
1709
1710 #include "exynos5433-bus.dtsi"
1711 #include "exynos5433-pinctrl.dtsi"
1712 #include "exynos5433-tmu.dtsi"
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