arch/arm64/boot/dts/exynos/exynos7.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMSUNG EXYNOS7 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 #include <dt-bindings/clock/exynos7-clk.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "samsung,exynos7";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 pinctrl0 = &pinctrl_alive;
  20                 pinctrl1 = &pinctrl_bus0;
  21                 pinctrl2 = &pinctrl_nfc;
  22                 pinctrl3 = &pinctrl_touch;
  23                 pinctrl4 = &pinctrl_ff;
  24                 pinctrl5 = &pinctrl_ese;
  25                 pinctrl6 = &pinctrl_fsys0;
  26                 pinctrl7 = &pinctrl_fsys1;
  27                 pinctrl8 = &pinctrl_bus1;
  28                 tmuctrl0 = &tmuctrl_0;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu_atlas0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a57", "arm,armv8";
  38                         reg = <0x0>;
  39                         enable-method = "psci";
  40                 };
  41
  42                 cpu_atlas1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a57", "arm,armv8";
  45                         reg = <0x1>;
  46                         enable-method = "psci";
  47                 };
  48
  49                 cpu_atlas2: cpu@2 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a57", "arm,armv8";
  52                         reg = <0x2>;
  53                         enable-method = "psci";
  54                 };
  55
  56                 cpu_atlas3: cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a57", "arm,armv8";
  59                         reg = <0x3>;
  60                         enable-method = "psci";
  61                 };
  62         };
  63
  64         psci {
  65                 compatible = "arm,psci-0.2";
  66                 method = "smc";
  67         };
  68
  69         soc: soc {
  70                 compatible = "simple-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 ranges = <0 0 0 0x18000000>;
  74
  75                 chipid@10000000 {
  76                         compatible = "samsung,exynos4210-chipid";
  77                         reg = <0x10000000 0x100>;
  78                 };
  79
  80                 fin_pll: xxti {
  81                         compatible = "fixed-clock";
  82                         clock-output-names = "fin_pll";
  83                         #clock-cells = <0>;
  84                 };
  85
  86                 gic: interrupt-controller@11001000 {
  87                         compatible = "arm,gic-400";
  88                         #interrupt-cells = <3>;
  89                         #address-cells = <0>;
  90                         interrupt-controller;
  91                         reg =   <0x11001000 0x1000>,
  92                                 <0x11002000 0x1000>,
  93                                 <0x11004000 0x2000>,
  94                                 <0x11006000 0x2000>;
  95                 };
  96
  97                 amba {
  98                         compatible = "simple-bus";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges;
 102
 103                         pdma0: pdma@10e10000 {
 104                                 compatible = "arm,pl330", "arm,primecell";
 105                                 reg = <0x10E10000 0x1000>;
 106                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 107                                 clocks = <&clock_fsys0 ACLK_PDMA0>;
 108                                 clock-names = "apb_pclk";
 109                                 #dma-cells = <1>;
 110                                 #dma-channels = <8>;
 111                                 #dma-requests = <32>;
 112                         };
 113
 114                         pdma1: pdma@10eb0000 {
 115                                 compatible = "arm,pl330", "arm,primecell";
 116                                 reg = <0x10EB0000 0x1000>;
 117                                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 118                                 clocks = <&clock_fsys0 ACLK_PDMA1>;
 119                                 clock-names = "apb_pclk";
 120                                 #dma-cells = <1>;
 121                                 #dma-channels = <8>;
 122                                 #dma-requests = <32>;
 123                         };
 124                 };
 125
 126                 clock_topc: clock-controller@10570000 {
 127                         compatible = "samsung,exynos7-clock-topc";
 128                         reg = <0x10570000 0x10000>;
 129                         #clock-cells = <1>;
 130                 };
 131
 132                 clock_top0: clock-controller@105d0000 {
 133                         compatible = "samsung,exynos7-clock-top0";
 134                         reg = <0x105d0000 0xb000>;
 135                         #clock-cells = <1>;
 136                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 137                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 138                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 139                                  <&clock_topc DOUT_SCLK_MFC_PLL>;
 140                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 141                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 142                                       "dout_sclk_mfc_pll";
 143                 };
 144
 145                 clock_top1: clock-controller@105e0000 {
 146                         compatible = "samsung,exynos7-clock-top1";
 147                         reg = <0x105e0000 0xb000>;
 148                         #clock-cells = <1>;
 149                         clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
 150                                  <&clock_topc DOUT_SCLK_BUS1_PLL>,
 151                                  <&clock_topc DOUT_SCLK_CC_PLL>,
 152                                  <&clock_topc DOUT_SCLK_MFC_PLL>;
 153                         clock-names = "fin_pll", "dout_sclk_bus0_pll",
 154                                       "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
 155                                       "dout_sclk_mfc_pll";
 156                 };
 157
 158                 clock_ccore: clock-controller@105b0000 {
 159                         compatible = "samsung,exynos7-clock-ccore";
 160                         reg = <0x105b0000 0xd00>;
 161                         #clock-cells = <1>;
 162                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
 163                         clock-names = "fin_pll", "dout_aclk_ccore_133";
 164                 };
 165
 166                 clock_peric0: clock-controller@13610000 {
 167                         compatible = "samsung,exynos7-clock-peric0";
 168                         reg = <0x13610000 0xd00>;
 169                         #clock-cells = <1>;
 170                         clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
 171                                  <&clock_top0 CLK_SCLK_UART0>;
 172                         clock-names = "fin_pll", "dout_aclk_peric0_66",
 173                                       "sclk_uart0";
 174                 };
 175
 176                 clock_peric1: clock-controller@14c80000 {
 177                         compatible = "samsung,exynos7-clock-peric1";
 178                         reg = <0x14c80000 0xd00>;
 179                         #clock-cells = <1>;
 180                         clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
 181                                  <&clock_top0 CLK_SCLK_UART1>,
 182                                  <&clock_top0 CLK_SCLK_UART2>,
 183                                  <&clock_top0 CLK_SCLK_UART3>;
 184                         clock-names = "fin_pll", "dout_aclk_peric1_66",
 185                                       "sclk_uart1", "sclk_uart2", "sclk_uart3";
 186                 };
 187
 188                 clock_peris: clock-controller@10040000 {
 189                         compatible = "samsung,exynos7-clock-peris";
 190                         reg = <0x10040000 0xd00>;
 191                         #clock-cells = <1>;
 192                         clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
 193                         clock-names = "fin_pll", "dout_aclk_peris_66";
 194                 };
 195
 196                 clock_fsys0: clock-controller@10e90000 {
 197                         compatible = "samsung,exynos7-clock-fsys0";
 198                         reg = <0x10e90000 0xd00>;
 199                         #clock-cells = <1>;
 200                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
 201                                  <&clock_top1 DOUT_SCLK_MMC2>;
 202                         clock-names = "fin_pll", "dout_aclk_fsys0_200",
 203                                       "dout_sclk_mmc2";
 204                 };
 205
 206                 clock_fsys1: clock-controller@156e0000 {
 207                         compatible = "samsung,exynos7-clock-fsys1";
 208                         reg = <0x156e0000 0xd00>;
 209                         #clock-cells = <1>;
 210                         clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
 211                                  <&clock_top1 DOUT_SCLK_MMC0>,
 212                                  <&clock_top1 DOUT_SCLK_MMC1>;
 213                         clock-names = "fin_pll", "dout_aclk_fsys1_200",
 214                                       "dout_sclk_mmc0", "dout_sclk_mmc1";
 215                 };
 216
 217                 serial_0: serial@13630000 {
 218                         compatible = "samsung,exynos4210-uart";
 219                         reg = <0x13630000 0x100>;
 220                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&clock_peric0 PCLK_UART0>,
 222                                  <&clock_peric0 SCLK_UART0>;
 223                         clock-names = "uart", "clk_uart_baud0";
 224                         status = "disabled";
 225                 };
 226
 227                 serial_1: serial@14c20000 {
 228                         compatible = "samsung,exynos4210-uart";
 229                         reg = <0x14c20000 0x100>;
 230                         interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
 231                         clocks = <&clock_peric1 PCLK_UART1>,
 232                                  <&clock_peric1 SCLK_UART1>;
 233                         clock-names = "uart", "clk_uart_baud0";
 234                         status = "disabled";
 235                 };
 236
 237                 serial_2: serial@14c30000 {
 238                         compatible = "samsung,exynos4210-uart";
 239                         reg = <0x14c30000 0x100>;
 240                         interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&clock_peric1 PCLK_UART2>,
 242                                  <&clock_peric1 SCLK_UART2>;
 243                         clock-names = "uart", "clk_uart_baud0";
 244                         status = "disabled";
 245                 };
 246
 247                 serial_3: serial@14c40000 {
 248                         compatible = "samsung,exynos4210-uart";
 249                         reg = <0x14c40000 0x100>;
 250                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
 251                         clocks = <&clock_peric1 PCLK_UART3>,
 252                                  <&clock_peric1 SCLK_UART3>;
 253                         clock-names = "uart", "clk_uart_baud0";
 254                         status = "disabled";
 255                 };
 256
 257                 pinctrl_alive: pinctrl@10580000 {
 258                         compatible = "samsung,exynos7-pinctrl";
 259                         reg = <0x10580000 0x1000>;
 260
 261                         wakeup-interrupt-controller {
 262                                 compatible = "samsung,exynos7-wakeup-eint";
 263                                 interrupt-parent = <&gic>;
 264                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 265                         };
 266                 };
 267
 268                 pinctrl_bus0: pinctrl@13470000 {
 269                         compatible = "samsung,exynos7-pinctrl";
 270                         reg = <0x13470000 0x1000>;
 271                         interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
 272                 };
 273
 274                 pinctrl_nfc: pinctrl@14cd0000 {
 275                         compatible = "samsung,exynos7-pinctrl";
 276                         reg = <0x14cd0000 0x1000>;
 277                         interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 278                 };
 279
 280                 pinctrl_touch: pinctrl@14ce0000 {
 281                         compatible = "samsung,exynos7-pinctrl";
 282                         reg = <0x14ce0000 0x1000>;
 283                         interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
 284                 };
 285
 286                 pinctrl_ff: pinctrl@14c90000 {
 287                         compatible = "samsung,exynos7-pinctrl";
 288                         reg = <0x14c90000 0x1000>;
 289                         interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
 290                 };
 291
 292                 pinctrl_ese: pinctrl@14ca0000 {
 293                         compatible = "samsung,exynos7-pinctrl";
 294                         reg = <0x14ca0000 0x1000>;
 295                         interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
 296                 };
 297
 298                 pinctrl_fsys0: pinctrl@10e60000 {
 299                         compatible = "samsung,exynos7-pinctrl";
 300                         reg = <0x10e60000 0x1000>;
 301                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 302                 };
 303
 304                 pinctrl_fsys1: pinctrl@15690000 {
 305                         compatible = "samsung,exynos7-pinctrl";
 306                         reg = <0x15690000 0x1000>;
 307                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 308                 };
 309
 310                 pinctrl_bus1: pinctrl@14870000 {
 311                         compatible = "samsung,exynos7-pinctrl";
 312                         reg = <0x14870000 0x1000>;
 313                         interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 314                 };
 315
 316                 hsi2c_0: hsi2c@13640000 {
 317                         compatible = "samsung,exynos7-hsi2c";
 318                         reg = <0x13640000 0x1000>;
 319                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         pinctrl-names = "default";
 323                         pinctrl-0 = <&hs_i2c0_bus>;
 324                         clocks = <&clock_peric0 PCLK_HSI2C0>;
 325                         clock-names = "hsi2c";
 326                         status = "disabled";
 327                 };
 328
 329                 hsi2c_1: hsi2c@13650000 {
 330                         compatible = "samsung,exynos7-hsi2c";
 331                         reg = <0x13650000 0x1000>;
 332                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         pinctrl-names = "default";
 336                         pinctrl-0 = <&hs_i2c1_bus>;
 337                         clocks = <&clock_peric0 PCLK_HSI2C1>;
 338                         clock-names = "hsi2c";
 339                         status = "disabled";
 340                 };
 341
 342                 hsi2c_2: hsi2c@14e60000 {
 343                         compatible = "samsung,exynos7-hsi2c";
 344                         reg = <0x14e60000 0x1000>;
 345                         interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         pinctrl-names = "default";
 349                         pinctrl-0 = <&hs_i2c2_bus>;
 350                         clocks = <&clock_peric1 PCLK_HSI2C2>;
 351                         clock-names = "hsi2c";
 352                         status = "disabled";
 353                 };
 354
 355                 hsi2c_3: hsi2c@14e70000 {
 356                         compatible = "samsung,exynos7-hsi2c";
 357                         reg = <0x14e70000 0x1000>;
 358                         interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         pinctrl-names = "default";
 362                         pinctrl-0 = <&hs_i2c3_bus>;
 363                         clocks = <&clock_peric1 PCLK_HSI2C3>;
 364                         clock-names = "hsi2c";
 365                         status = "disabled";
 366                 };
 367
 368                 hsi2c_4: hsi2c@13660000 {
 369                         compatible = "samsung,exynos7-hsi2c";
 370                         reg = <0x13660000 0x1000>;
 371                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         pinctrl-names = "default";
 375                         pinctrl-0 = <&hs_i2c4_bus>;
 376                         clocks = <&clock_peric0 PCLK_HSI2C4>;
 377                         clock-names = "hsi2c";
 378                         status = "disabled";
 379                 };
 380
 381                 hsi2c_5: hsi2c@13670000 {
 382                         compatible = "samsung,exynos7-hsi2c";
 383                         reg = <0x13670000 0x1000>;
 384                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         pinctrl-names = "default";
 388                         pinctrl-0 = <&hs_i2c5_bus>;
 389                         clocks = <&clock_peric0 PCLK_HSI2C5>;
 390                         clock-names = "hsi2c";
 391                         status = "disabled";
 392                 };
 393
 394                 hsi2c_6: hsi2c@14e00000 {
 395                         compatible = "samsung,exynos7-hsi2c";
 396                         reg = <0x14e00000 0x1000>;
 397                         interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         pinctrl-names = "default";
 401                         pinctrl-0 = <&hs_i2c6_bus>;
 402                         clocks = <&clock_peric1 PCLK_HSI2C6>;
 403                         clock-names = "hsi2c";
 404                         status = "disabled";
 405                 };
 406
 407                 hsi2c_7: hsi2c@13e10000 {
 408                         compatible = "samsung,exynos7-hsi2c";
 409                         reg = <0x13e10000 0x1000>;
 410                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         pinctrl-names = "default";
 414                         pinctrl-0 = <&hs_i2c7_bus>;
 415                         clocks = <&clock_peric1 PCLK_HSI2C7>;
 416                         clock-names = "hsi2c";
 417                         status = "disabled";
 418                 };
 419
 420                 hsi2c_8: hsi2c@14e20000 {
 421                         compatible = "samsung,exynos7-hsi2c";
 422                         reg = <0x14e20000 0x1000>;
 423                         interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         pinctrl-names = "default";
 427                         pinctrl-0 = <&hs_i2c8_bus>;
 428                         clocks = <&clock_peric1 PCLK_HSI2C8>;
 429                         clock-names = "hsi2c";
 430                         status = "disabled";
 431                 };
 432
 433                 hsi2c_9: hsi2c@13680000 {
 434                         compatible = "samsung,exynos7-hsi2c";
 435                         reg = <0x13680000 0x1000>;
 436                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         pinctrl-names = "default";
 440                         pinctrl-0 = <&hs_i2c9_bus>;
 441                         clocks = <&clock_peric0 PCLK_HSI2C9>;
 442                         clock-names = "hsi2c";
 443                         status = "disabled";
 444                 };
 445
 446                 hsi2c_10: hsi2c@13690000 {
 447                         compatible = "samsung,exynos7-hsi2c";
 448                         reg = <0x13690000 0x1000>;
 449                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         pinctrl-names = "default";
 453                         pinctrl-0 = <&hs_i2c10_bus>;
 454                         clocks = <&clock_peric0 PCLK_HSI2C10>;
 455                         clock-names = "hsi2c";
 456                         status = "disabled";
 457                 };
 458
 459                 hsi2c_11: hsi2c@136a0000 {
 460                         compatible = "samsung,exynos7-hsi2c";
 461                         reg = <0x136a0000 0x1000>;
 462                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                         pinctrl-names = "default";
 466                         pinctrl-0 = <&hs_i2c11_bus>;
 467                         clocks = <&clock_peric0 PCLK_HSI2C11>;
 468                         clock-names = "hsi2c";
 469                         status = "disabled";
 470                 };
 471
 472                 arm-pmu {
 473                         compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
 474                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 476                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 477                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 478                         interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
 479                                              <&cpu_atlas2>, <&cpu_atlas3>;
 480                 };
 481
 482                 timer {
 483                         compatible = "arm,armv8-timer";
 484                         interrupts = <GIC_PPI 13
 485                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 486                                      <GIC_PPI 14
 487                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 488                                      <GIC_PPI 11
 489                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 490                                      <GIC_PPI 10
 491                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 492                 };
 493
 494                 pmu_system_controller: system-controller@105c0000 {
 495                         compatible = "samsung,exynos7-pmu", "syscon";
 496                         reg = <0x105c0000 0x5000>;
 497
 498                         reboot: syscon-reboot {
 499                                 compatible = "syscon-reboot";
 500                                 regmap = <&pmu_system_controller>;
 501                                 offset = <0x0400>;
 502                                 mask = <0x1>;
 503                         };
 504                 };
 505
 506                 rtc: rtc@10590000 {
 507                         compatible = "samsung,s3c6410-rtc";
 508                         reg = <0x10590000 0x100>;
 509                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 510                                      <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&clock_ccore PCLK_RTC>;
 512                         clock-names = "rtc";
 513                         status = "disabled";
 514                 };
 515
 516                 watchdog: watchdog@101d0000 {
 517                         compatible = "samsung,exynos7-wdt";
 518                         reg = <0x101d0000 0x100>;
 519                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&clock_peris PCLK_WDT>;
 521                         clock-names = "watchdog";
 522                         samsung,syscon-phandle = <&pmu_system_controller>;
 523                         status = "disabled";
 524                 };
 525
 526                 mmc_0: mmc@15740000 {
 527                         compatible = "samsung,exynos7-dw-mshc-smu";
 528                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         reg = <0x15740000 0x2000>;
 532                         clocks = <&clock_fsys1 ACLK_MMC0>,
 533                                  <&clock_top1 CLK_SCLK_MMC0>;
 534                         clock-names = "biu", "ciu";
 535                         fifo-depth = <0x40>;
 536                         status = "disabled";
 537                 };
 538
 539                 mmc_1: mmc@15750000 {
 540                         compatible = "samsung,exynos7-dw-mshc";
 541                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544                         reg = <0x15750000 0x2000>;
 545                         clocks = <&clock_fsys1 ACLK_MMC1>,
 546                                  <&clock_top1 CLK_SCLK_MMC1>;
 547                         clock-names = "biu", "ciu";
 548                         fifo-depth = <0x40>;
 549                         status = "disabled";
 550                 };
 551
 552                 mmc_2: mmc@15560000 {
 553                         compatible = "samsung,exynos7-dw-mshc-smu";
 554                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         reg = <0x15560000 0x2000>;
 558                         clocks = <&clock_fsys0 ACLK_MMC2>,
 559                                  <&clock_top1 CLK_SCLK_MMC2>;
 560                         clock-names = "biu", "ciu";
 561                         fifo-depth = <0x40>;
 562                         status = "disabled";
 563                 };
 564
 565                 adc: adc@13620000 {
 566                         compatible = "samsung,exynos7-adc";
 567                         reg = <0x13620000 0x100>;
 568                         interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
 569                         clocks = <&clock_peric0 PCLK_ADCIF>;
 570                         clock-names = "adc";
 571                         #io-channel-cells = <1>;
 572                         io-channel-ranges;
 573                         status = "disabled";
 574                 };
 575
 576                 pwm: pwm@136c0000 {
 577                         compatible = "samsung,exynos4210-pwm";
 578                         reg = <0x136c0000 0x100>;
 579                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 580                         #pwm-cells = <3>;
 581                         clocks = <&clock_peric0 PCLK_PWM>;
 582                         clock-names = "timers";
 583                 };
 584
 585                 tmuctrl_0: tmu@10060000 {
 586                         compatible = "samsung,exynos7-tmu";
 587                         reg = <0x10060000 0x200>;
 588                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 589                         clocks = <&clock_peris PCLK_TMU>,
 590                                  <&clock_peris SCLK_TMU>;
 591                         clock-names = "tmu_apbif", "tmu_sclk";
 592                         #include "exynos7-tmu-sensor-conf.dtsi"
 593                 };
 594
 595                 thermal-zones {
 596                         atlas_thermal: cluster0-thermal {
 597                                 polling-delay-passive = <0>; /* milliseconds */
 598                                 polling-delay = <0>; /* milliseconds */
 599                                 thermal-sensors = <&tmuctrl_0>;
 600                                 #include "exynos7-trip-points.dtsi"
 601                         };
 602                 };
 603
 604                 usbdrd_phy: phy@15500000 {
 605                         compatible = "samsung,exynos7-usbdrd-phy";
 606                         reg = <0x15500000 0x100>;
 607                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 608                                <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
 609                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
 610                                <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
 611                                <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
 612                         clock-names = "phy", "ref", "phy_pipe",
 613                                 "phy_utmi", "itp";
 614                         samsung,pmu-syscon = <&pmu_system_controller>;
 615                         #phy-cells = <1>;
 616                 };
 617
 618                 usbdrd3 {
 619                         compatible = "samsung,exynos7-dwusb3";
 620                         clocks = <&clock_fsys0 ACLK_USBDRD300>,
 621                                <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
 622                                <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
 623                         clock-names = "usbdrd30", "usbdrd30_susp_clk",
 624                                 "usbdrd30_axius_clk";
 625                         #address-cells = <1>;
 626                         #size-cells = <1>;
 627                         ranges;
 628
 629                         dwc3@15400000 {
 630                                 compatible = "snps,dwc3";
 631                                 reg = <0x15400000 0x10000>;
 632                                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 633                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 634                                 phy-names = "usb2-phy", "usb3-phy";
 635                         };
 636                 };
 637         };
 638 };
 639
 640 #include "exynos7-pinctrl.dtsi"