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[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / boot / dts / freescale / imx8mq-zii-ultra.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2019 Zodiac Inflight Innovations
4 */
5
6 #include "imx8mq.dtsi"
7
8 / {
9 aliases {
10 mdio-gpio0 = &mdio0;
11 rtc0 = &ds1341;
12 };
13
14 chosen {
15 stdout-path = &uart1;
16 };
17
18 mdio0: bitbang-mdio {
19 compatible = "virtual,mdio-gpio";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
22 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
23 <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 phy0: ethernet-phy@0 {
28 reg = <0>;
29 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
30 };
31 };
32
33 pcie0_refclk: clock-pcie0-refclk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <100000000>;
37 };
38
39 pcie1_refclk: clock-pcie1-refclk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <100000000>;
43 };
44
45 reg_12p0_main: regulator-12p0-main {
46 compatible = "regulator-fixed";
47 regulator-name = "12V_MAIN";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 regulator-always-on;
51 };
52
53 reg_5p0_main: regulator-5p0-main {
54 compatible = "regulator-fixed";
55 vin-supply = <&reg_12p0_main>;
56 regulator-name = "5V_MAIN";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 regulator-always-on;
60 };
61
62 reg_3p3_main: regulator-3p3-main {
63 compatible = "regulator-fixed";
64 vin-supply = <&reg_12p0_main>;
65 regulator-name = "3V3_MAIN";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 regulator-always-on;
69 };
70
71 reg_gen_3p3: regulator-gen-3p3 {
72 compatible = "regulator-fixed";
73 vin-supply = <&reg_3p3_main>;
74 regulator-name = "GEN_3V3";
75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>;
77 regulator-always-on;
78 };
79
80 reg_usdhc2_vmmc: regulator-vsd-3v3 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_reg_usdhc2>;
83 compatible = "regulator-fixed";
84 vin-supply = <&reg_gen_3p3>;
85 regulator-name = "3V3_SD";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
88 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
89 enable-active-high;
90 };
91
92 reg_arm: regulator-arm {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_reg_arm>;
95 compatible = "regulator-gpio";
96 vin-supply = <&reg_12p0_main>;
97 regulator-name = "0V9_ARM";
98 regulator-min-microvolt = <900000>;
99 regulator-max-microvolt = <1000000>;
100 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
101 states = <1000000 0x1
102 900000 0x0>;
103 regulator-always-on;
104 };
105 };
106
107 &A53_0 {
108 cpu-supply = <&reg_arm>;
109 };
110
111 &A53_1 {
112 cpu-supply = <&reg_arm>;
113 };
114
115 &A53_2 {
116 cpu-supply = <&reg_arm>;
117 };
118
119 &A53_3 {
120 cpu-supply = <&reg_arm>;
121 };
122
123 &fec1 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_fec1>;
126
127 phy-handle = <&phy0>;
128 phy-mode = "rmii";
129 status = "okay";
130
131 mdio {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 clock-frequency = <12500000>;
135 suppress-preamble;
136 status = "okay";
137
138 switch: switch@0 {
139 compatible = "marvell,mv88e6085";
140 pinctrl-0 = <&pinctrl_switch_irq>;
141 pinctrl-names = "default";
142 reg = <0>;
143 dsa,member = <0 0>;
144 eeprom-length = <512>;
145 interrupt-parent = <&gpio1>;
146 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
149
150 ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 port@0 {
155 reg = <0>;
156 label = "gigabit_proc";
157 phy-handle = <&switchphy0>;
158 };
159
160 port@1 {
161 reg = <1>;
162 label = "netaux";
163 phy-handle = <&switchphy1>;
164 };
165
166 port@2 {
167 reg = <2>;
168 label = "cpu";
169 ethernet = <&fec1>;
170
171 fixed-link {
172 speed = <100>;
173 full-duplex;
174 };
175 };
176
177 port@3 {
178 reg = <3>;
179 label = "netright";
180 phy-handle = <&switchphy3>;
181 };
182
183 port@4 {
184 reg = <4>;
185 label = "netleft";
186 phy-handle = <&switchphy4>;
187 };
188 };
189
190 mdio {
191 #address-cells = <1>;
192 #size-cells = <0>;
193
194 switchphy0: switchphy@0 {
195 reg = <0>;
196 interrupt-parent = <&switch>;
197 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
198 };
199
200 switchphy1: switchphy@1 {
201 reg = <1>;
202 interrupt-parent = <&switch>;
203 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
204 };
205
206 switchphy2: switchphy@2 {
207 reg = <2>;
208 interrupt-parent = <&switch>;
209 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
210 };
211
212 switchphy3: switchphy@3 {
213 reg = <3>;
214 interrupt-parent = <&switch>;
215 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
216 };
217
218 switchphy4: switchphy@4 {
219 reg = <4>;
220 interrupt-parent = <&switch>;
221 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
222 };
223 };
224 };
225 };
226 };
227
228 &gpio3 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_gpio3_hog>;
231
232 usb-emulation-hog {
233 gpio-hog;
234 gpios = <10 GPIO_ACTIVE_HIGH>;
235 output-low;
236 line-name = "usb-emulation";
237 };
238
239 usb-mode1-hog {
240 gpio-hog;
241 gpios = <11 GPIO_ACTIVE_HIGH>;
242 output-high;
243 line-name = "usb-mode1";
244 };
245
246 usb-pwr-hog {
247 gpio-hog;
248 gpios = <12 GPIO_ACTIVE_LOW>;
249 output-high;
250 line-name = "usb-pwr-ctrl-en-n";
251 };
252
253 usb-mode2-hog {
254 gpio-hog;
255 gpios = <13 GPIO_ACTIVE_HIGH>;
256 output-high;
257 line-name = "usb-mode2";
258 };
259 };
260
261 &i2c1 {
262 clock-frequency = <400000>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_i2c1>;
265 status = "okay";
266
267 accelerometer@1c {
268 compatible = "fsl,mma8451";
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_accel>;
271 reg = <0x1c>;
272 interrupt-parent = <&gpio3>;
273 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
274 interrupt-names = "INT2";
275 vdd-supply = <&reg_gen_3p3>;
276 vddio-supply = <&reg_gen_3p3>;
277 };
278
279 ucs1002: charger@32 {
280 compatible = "microchip,ucs1002";
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_ucs1002>;
283 reg = <0x32>;
284 interrupt-parent = <&gpio3>;
285 interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
286 <18 IRQ_TYPE_EDGE_BOTH>;
287 interrupt-names = "a_det", "alert";
288 };
289 };
290
291 &i2c2 {
292 clock-frequency = <400000>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_i2c2>;
295 status = "okay";
296
297 pmic@8 {
298 compatible = "fsl,pfuze100";
299 reg = <0x8>;
300
301 regulators {
302 sw1a_reg: sw1ab {
303 regulator-min-microvolt = <825000>;
304 regulator-max-microvolt = <1100000>;
305 };
306
307 sw1c_reg: sw1c {
308 regulator-min-microvolt = <825000>;
309 regulator-max-microvolt = <1100000>;
310 };
311
312 sw2_reg: sw2 {
313 regulator-min-microvolt = <1100000>;
314 regulator-max-microvolt = <1100000>;
315 regulator-always-on;
316 };
317
318 sw3a_reg: sw3ab {
319 regulator-min-microvolt = <825000>;
320 regulator-max-microvolt = <1100000>;
321 regulator-always-on;
322 };
323
324 sw4_reg: sw4 {
325 regulator-min-microvolt = <1800000>;
326 regulator-max-microvolt = <1800000>;
327 regulator-always-on;
328 };
329
330 swbst_reg: swbst {
331 regulator-min-microvolt = <5000000>;
332 regulator-max-microvolt = <5150000>;
333 };
334
335 snvs_reg: vsnvs {
336 regulator-min-microvolt = <1000000>;
337 regulator-max-microvolt = <3000000>;
338 regulator-always-on;
339 };
340
341 vref_reg: vrefddr {
342 regulator-always-on;
343 };
344
345 vgen1_reg: vgen1 {
346 regulator-min-microvolt = <800000>;
347 regulator-max-microvolt = <1550000>;
348 };
349
350 vgen2_reg: vgen2 {
351 regulator-min-microvolt = <850000>;
352 regulator-max-microvolt = <975000>;
353 regulator-always-on;
354 };
355
356 vgen3_reg: vgen3 {
357 regulator-min-microvolt = <1675000>;
358 regulator-max-microvolt = <1975000>;
359 regulator-always-on;
360 };
361
362 vgen4_reg: vgen4 {
363 regulator-min-microvolt = <1625000>;
364 regulator-max-microvolt = <1875000>;
365 regulator-always-on;
366 };
367
368 vgen5_reg: vgen5 {
369 regulator-min-microvolt = <3075000>;
370 regulator-max-microvolt = <3625000>;
371 regulator-always-on;
372 };
373
374 vgen6_reg: vgen6 {
375 regulator-min-microvolt = <1800000>;
376 regulator-max-microvolt = <3300000>;
377 };
378 };
379 };
380
381 eeprom@54 {
382 compatible = "atmel,24c128";
383 reg = <0x54>;
384 };
385
386 ds1341: rtc@68 {
387 compatible = "dallas,ds1341";
388 reg = <0x68>;
389 };
390 };
391
392 &i2c3 {
393 clock-frequency = <100000>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_i2c3>;
396 status = "okay";
397
398 usbhub: usbhub@2c {
399 compatible ="microchip,usb2513b";
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_usbhub>;
402 reg = <0x2c>;
403 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
404 };
405
406 watchdog@38 {
407 compatible = "zii,rave-wdt";
408 reg = <0x38>;
409 };
410 };
411
412 &i2c4 {
413 clock-frequency = <400000>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_i2c4>;
416 status = "okay";
417 };
418
419 &uart1 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_uart1>;
422 status = "okay";
423 };
424
425 &uart2 {
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_uart2>;
428 status = "okay";
429
430 rave-sp {
431 compatible = "zii,rave-sp-rdu2";
432 current-speed = <1000000>;
433 #address-cells = <1>;
434 #size-cells = <1>;
435
436 watchdog {
437 compatible = "zii,rave-sp-watchdog";
438 };
439
440 backlight {
441 compatible = "zii,rave-sp-backlight";
442 };
443
444 pwrbutton {
445 compatible = "zii,rave-sp-pwrbutton";
446 };
447
448 eeprom@a3 {
449 compatible = "zii,rave-sp-eeprom";
450 reg = <0xa3 0x4000>;
451 zii,eeprom-name = "dds-eeprom";
452 };
453
454 eeprom@a4 {
455 compatible = "zii,rave-sp-eeprom";
456 reg = <0xa4 0x4000>;
457 #address-cells = <1>;
458 #size-cells = <1>;
459 zii,eeprom-name = "main-eeprom";
460 };
461 };
462 };
463
464 &usb3_phy0 {
465 vbus-supply = <&ucs1002>;
466 status = "okay";
467 };
468
469 &usb_dwc3_0 {
470 dr_mode = "host";
471 status = "okay";
472 };
473
474 &usb3_phy1 {
475 vbus-supply = <&reg_5p0_main>;
476 status = "okay";
477 };
478
479 &usb_dwc3_1 {
480 dr_mode = "host";
481 status = "okay";
482 };
483
484 &pcie0 {
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_pcie0>;
487 reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
488 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
489 <&clk IMX8MQ_CLK_PCIE1_AUX>,
490 <&clk IMX8MQ_CLK_PCIE1_PHY>,
491 <&pcie0_refclk>;
492 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
493 status = "okay";
494 };
495
496 &pcie1 {
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_pcie1>;
499 reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
500 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
501 <&clk IMX8MQ_CLK_PCIE2_AUX>,
502 <&clk IMX8MQ_CLK_PCIE2_PHY>,
503 <&pcie1_refclk>;
504 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
505 status = "okay";
506 };
507
508 &pgc_gpu {
509 power-supply = <&sw1a_reg>;
510 };
511
512 &pgc_vpu {
513 power-supply = <&sw1c_reg>;
514 };
515
516 &usdhc1 {
517 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
518 assigned-clock-rates = <400000000>;
519 pinctrl-names = "default", "state_100mhz", "state_200mhz";
520 pinctrl-0 = <&pinctrl_usdhc1>;
521 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
522 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
523 vqmmc-supply = <&sw4_reg>;
524 bus-width = <8>;
525 non-removable;
526 no-sd;
527 no-sdio;
528 status = "okay";
529 };
530
531 &usdhc2 {
532 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
533 assigned-clock-rates = <200000000>;
534 pinctrl-names = "default", "state_100mhz", "state_200mhz";
535 pinctrl-0 = <&pinctrl_usdhc2>;
536 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
537 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
538 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
539 vmmc-supply = <&reg_usdhc2_vmmc>;
540 status = "okay";
541 };
542
543 &snvs_rtc {
544 status = "disabled";
545 };
546
547 &iomuxc {
548 pinctrl_accel: accelgrp {
549 fsl,pins = <
550 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
551 >;
552 };
553
554 pinctrl_fec1: fec1grp {
555 fsl,pins = <
556 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
557 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
558 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
559 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
560 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
561 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
562 MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f
563 MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
564 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
565 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
566 >;
567 };
568
569 pinctrl_fec1_phy_reset: fec1phyresetgrp {
570 fsl,pins = <
571 MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11
572 >;
573 };
574
575 pinctrl_gpio3_hog: gpio3hoggrp {
576 fsl,pins = <
577 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6
578 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6
579 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
580 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6
581 >;
582 };
583
584 pinctrl_i2c1: i2c1grp {
585 fsl,pins = <
586 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
587 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
588 >;
589 };
590
591 pinctrl_i2c2: i2c2grp {
592 fsl,pins = <
593 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
594 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
595 >;
596 };
597
598 pinctrl_i2c3: i2c3grp {
599 fsl,pins = <
600 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
601 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
602 >;
603 };
604
605 pinctrl_i2c4: i2c4grp {
606 fsl,pins = <
607 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
608 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
609 >;
610 };
611
612 pinctrl_mdio_bitbang: bitbangmdiogrp {
613 fsl,pins = <
614 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44
615 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64
616 >;
617 };
618
619 pinctrl_pcie0: pcie0grp {
620 fsl,pins = <
621 MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66
622 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6
623 >;
624 };
625
626 pinctrl_pcie1: pcie1grp {
627 fsl,pins = <
628 MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66
629 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6
630 >;
631 };
632
633 pinctrl_reg_arm: regarmgrp {
634 fsl,pins = <
635 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
636 >;
637 };
638
639 pinctrl_reg_usdhc2: regusdhc2grp {
640 fsl,pins = <
641 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
642 >;
643 };
644
645 pinctrl_switch_irq: switchgrp {
646 fsl,pins = <
647 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
648 >;
649 };
650
651 pinctrl_ts: tsgrp {
652 fsl,pins = <
653 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96
654 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96
655 >;
656 };
657
658 pinctrl_uart1: uart1grp {
659 fsl,pins = <
660 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
661 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
662 >;
663 };
664
665 pinctrl_uart2: uart2grp {
666 fsl,pins = <
667 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
668 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
669 >;
670 };
671
672 pinctrl_ucs1002: ucs1002grp {
673 fsl,pins = <
674 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41
675 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41
676 >;
677 };
678
679 pinctrl_usbhub: usbhubgrp {
680 fsl,pins = <
681 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
682 >;
683 };
684
685 pinctrl_usdhc1: usdhc1grp {
686 fsl,pins = <
687 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
688 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
689 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
690 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
691 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
692 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
693 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
694 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
695 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
696 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
697 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
698 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
699 >;
700 };
701
702 pinctrl_usdhc1_100mhz: usdhc1-100grp {
703 fsl,pins = <
704 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
705 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
706 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
707 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
708 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
709 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
710 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
711 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
712 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
713 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
714 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
715 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
716 >;
717 };
718
719 pinctrl_usdhc1_200mhz: usdhc1-200grp {
720 fsl,pins = <
721 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
722 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
723 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
724 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
725 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
726 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
727 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
728 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
729 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
730 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
731 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
732 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
733 >;
734 };
735
736 pinctrl_usdhc2: usdhc2grp {
737 fsl,pins = <
738 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
739 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
740 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
741 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
742 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
743 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
744 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
745 >;
746 };
747
748 pinctrl_usdhc2_100mhz: usdhc2-100grp {
749 fsl,pins = <
750 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
751 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
752 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
753 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
754 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
755 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
756 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
757 >;
758 };
759
760 pinctrl_usdhc2_200mhz: usdhc2-200grp {
761 fsl,pins = <
762 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
763 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
764 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
765 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
766 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
767 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
768 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
769 >;
770 };
771 };
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