arch/arm64/boot/dts/hisilicon/hip07.dtsi

   1 /**
   2  * dts file for Hisilicon D05 Development Board
   3  *
   4  * Copyright (C) 2016 Hisilicon Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * publishhed by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14 / {
  15         compatible = "hisilicon,hip07-d05";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         psci {
  21                 compatible = "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&cpu0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&cpu1>;
  36                                 };
  37                                 core2 {
  38                                         cpu = <&cpu2>;
  39                                 };
  40                                 core3 {
  41                                         cpu = <&cpu3>;
  42                                 };
  43                         };
  44
  45                         cluster1 {
  46                                 core0 {
  47                                         cpu = <&cpu4>;
  48                                 };
  49                                 core1 {
  50                                         cpu = <&cpu5>;
  51                                 };
  52                                 core2 {
  53                                         cpu = <&cpu6>;
  54                                 };
  55                                 core3 {
  56                                         cpu = <&cpu7>;
  57                                 };
  58                         };
  59
  60                         cluster2 {
  61                                 core0 {
  62                                         cpu = <&cpu8>;
  63                                 };
  64                                 core1 {
  65                                         cpu = <&cpu9>;
  66                                 };
  67                                 core2 {
  68                                         cpu = <&cpu10>;
  69                                 };
  70                                 core3 {
  71                                         cpu = <&cpu11>;
  72                                 };
  73                         };
  74
  75                         cluster3 {
  76                                 core0 {
  77                                         cpu = <&cpu12>;
  78                                 };
  79                                 core1 {
  80                                         cpu = <&cpu13>;
  81                                 };
  82                                 core2 {
  83                                         cpu = <&cpu14>;
  84                                 };
  85                                 core3 {
  86                                         cpu = <&cpu15>;
  87                                 };
  88                         };
  89
  90                         cluster4 {
  91                                 core0 {
  92                                         cpu = <&cpu16>;
  93                                 };
  94                                 core1 {
  95                                         cpu = <&cpu17>;
  96                                 };
  97                                 core2 {
  98                                         cpu = <&cpu18>;
  99                                 };
 100                                 core3 {
 101                                         cpu = <&cpu19>;
 102                                 };
 103                         };
 104
 105                         cluster5 {
 106                                 core0 {
 107                                         cpu = <&cpu20>;
 108                                 };
 109                                 core1 {
 110                                         cpu = <&cpu21>;
 111                                 };
 112                                 core2 {
 113                                         cpu = <&cpu22>;
 114                                 };
 115                                 core3 {
 116                                         cpu = <&cpu23>;
 117                                 };
 118                         };
 119
 120                         cluster6 {
 121                                 core0 {
 122                                         cpu = <&cpu24>;
 123                                 };
 124                                 core1 {
 125                                         cpu = <&cpu25>;
 126                                 };
 127                                 core2 {
 128                                         cpu = <&cpu26>;
 129                                 };
 130                                 core3 {
 131                                         cpu = <&cpu27>;
 132                                 };
 133                         };
 134
 135                         cluster7 {
 136                                 core0 {
 137                                         cpu = <&cpu28>;
 138                                 };
 139                                 core1 {
 140                                         cpu = <&cpu29>;
 141                                 };
 142                                 core2 {
 143                                         cpu = <&cpu30>;
 144                                 };
 145                                 core3 {
 146                                         cpu = <&cpu31>;
 147                                 };
 148                         };
 149
 150                         cluster8 {
 151                                 core0 {
 152                                         cpu = <&cpu32>;
 153                                 };
 154                                 core1 {
 155                                         cpu = <&cpu33>;
 156                                 };
 157                                 core2 {
 158                                         cpu = <&cpu34>;
 159                                 };
 160                                 core3 {
 161                                         cpu = <&cpu35>;
 162                                 };
 163                         };
 164
 165                         cluster9 {
 166                                 core0 {
 167                                         cpu = <&cpu36>;
 168                                 };
 169                                 core1 {
 170                                         cpu = <&cpu37>;
 171                                 };
 172                                 core2 {
 173                                         cpu = <&cpu38>;
 174                                 };
 175                                 core3 {
 176                                         cpu = <&cpu39>;
 177                                 };
 178                         };
 179
 180                         cluster10 {
 181                                 core0 {
 182                                         cpu = <&cpu40>;
 183                                 };
 184                                 core1 {
 185                                         cpu = <&cpu41>;
 186                                 };
 187                                 core2 {
 188                                         cpu = <&cpu42>;
 189                                 };
 190                                 core3 {
 191                                         cpu = <&cpu43>;
 192                                 };
 193                         };
 194
 195                         cluster11 {
 196                                 core0 {
 197                                         cpu = <&cpu44>;
 198                                 };
 199                                 core1 {
 200                                         cpu = <&cpu45>;
 201                                 };
 202                                 core2 {
 203                                         cpu = <&cpu46>;
 204                                 };
 205                                 core3 {
 206                                         cpu = <&cpu47>;
 207                                 };
 208                         };
 209
 210                         cluster12 {
 211                                 core0 {
 212                                         cpu = <&cpu48>;
 213                                 };
 214                                 core1 {
 215                                         cpu = <&cpu49>;
 216                                 };
 217                                 core2 {
 218                                         cpu = <&cpu50>;
 219                                 };
 220                                 core3 {
 221                                         cpu = <&cpu51>;
 222                                 };
 223                         };
 224
 225                         cluster13 {
 226                                 core0 {
 227                                         cpu = <&cpu52>;
 228                                 };
 229                                 core1 {
 230                                         cpu = <&cpu53>;
 231                                 };
 232                                 core2 {
 233                                         cpu = <&cpu54>;
 234                                 };
 235                                 core3 {
 236                                         cpu = <&cpu55>;
 237                                 };
 238                         };
 239
 240                         cluster14 {
 241                                 core0 {
 242                                         cpu = <&cpu56>;
 243                                 };
 244                                 core1 {
 245                                         cpu = <&cpu57>;
 246                                 };
 247                                 core2 {
 248                                         cpu = <&cpu58>;
 249                                 };
 250                                 core3 {
 251                                         cpu = <&cpu59>;
 252                                 };
 253                         };
 254
 255                         cluster15 {
 256                                 core0 {
 257                                         cpu = <&cpu60>;
 258                                 };
 259                                 core1 {
 260                                         cpu = <&cpu61>;
 261                                 };
 262                                 core2 {
 263                                         cpu = <&cpu62>;
 264                                 };
 265                                 core3 {
 266                                         cpu = <&cpu63>;
 267                                 };
 268                         };
 269                 };
 270
 271                 cpu0: cpu@10000 {
 272                         device_type = "cpu";
 273                         compatible = "arm,cortex-a72", "arm,armv8";
 274                         reg = <0x10000>;
 275                         enable-method = "psci";
 276                         next-level-cache = <&cluster0_l2>;
 277                         numa-node-id = <0>;
 278                 };
 279
 280                 cpu1: cpu@10001 {
 281                         device_type = "cpu";
 282                         compatible = "arm,cortex-a72", "arm,armv8";
 283                         reg = <0x10001>;
 284                         enable-method = "psci";
 285                         next-level-cache = <&cluster0_l2>;
 286                         numa-node-id = <0>;
 287                 };
 288
 289                 cpu2: cpu@10002 {
 290                         device_type = "cpu";
 291                         compatible = "arm,cortex-a72", "arm,armv8";
 292                         reg = <0x10002>;
 293                         enable-method = "psci";
 294                         next-level-cache = <&cluster0_l2>;
 295                         numa-node-id = <0>;
 296                 };
 297
 298                 cpu3: cpu@10003 {
 299                         device_type = "cpu";
 300                         compatible = "arm,cortex-a72", "arm,armv8";
 301                         reg = <0x10003>;
 302                         enable-method = "psci";
 303                         next-level-cache = <&cluster0_l2>;
 304                         numa-node-id = <0>;
 305                 };
 306
 307                 cpu4: cpu@10100 {
 308                         device_type = "cpu";
 309                         compatible = "arm,cortex-a72", "arm,armv8";
 310                         reg = <0x10100>;
 311                         enable-method = "psci";
 312                         next-level-cache = <&cluster1_l2>;
 313                         numa-node-id = <0>;
 314                 };
 315
 316                 cpu5: cpu@10101 {
 317                         device_type = "cpu";
 318                         compatible = "arm,cortex-a72", "arm,armv8";
 319                         reg = <0x10101>;
 320                         enable-method = "psci";
 321                         next-level-cache = <&cluster1_l2>;
 322                         numa-node-id = <0>;
 323                 };
 324
 325                 cpu6: cpu@10102 {
 326                         device_type = "cpu";
 327                         compatible = "arm,cortex-a72", "arm,armv8";
 328                         reg = <0x10102>;
 329                         enable-method = "psci";
 330                         next-level-cache = <&cluster1_l2>;
 331                         numa-node-id = <0>;
 332                 };
 333
 334                 cpu7: cpu@10103 {
 335                         device_type = "cpu";
 336                         compatible = "arm,cortex-a72", "arm,armv8";
 337                         reg = <0x10103>;
 338                         enable-method = "psci";
 339                         next-level-cache = <&cluster1_l2>;
 340                         numa-node-id = <0>;
 341                 };
 342
 343                 cpu8: cpu@10200 {
 344                         device_type = "cpu";
 345                         compatible = "arm,cortex-a72", "arm,armv8";
 346                         reg = <0x10200>;
 347                         enable-method = "psci";
 348                         next-level-cache = <&cluster2_l2>;
 349                         numa-node-id = <0>;
 350                 };
 351
 352                 cpu9: cpu@10201 {
 353                         device_type = "cpu";
 354                         compatible = "arm,cortex-a72", "arm,armv8";
 355                         reg = <0x10201>;
 356                         enable-method = "psci";
 357                         next-level-cache = <&cluster2_l2>;
 358                         numa-node-id = <0>;
 359                 };
 360
 361                 cpu10: cpu@10202 {
 362                         device_type = "cpu";
 363                         compatible = "arm,cortex-a72", "arm,armv8";
 364                         reg = <0x10202>;
 365                         enable-method = "psci";
 366                         next-level-cache = <&cluster2_l2>;
 367                         numa-node-id = <0>;
 368                 };
 369
 370                 cpu11: cpu@10203 {
 371                         device_type = "cpu";
 372                         compatible = "arm,cortex-a72", "arm,armv8";
 373                         reg = <0x10203>;
 374                         enable-method = "psci";
 375                         next-level-cache = <&cluster2_l2>;
 376                         numa-node-id = <0>;
 377                 };
 378
 379                 cpu12: cpu@10300 {
 380                         device_type = "cpu";
 381                         compatible = "arm,cortex-a72", "arm,armv8";
 382                         reg = <0x10300>;
 383                         enable-method = "psci";
 384                         next-level-cache = <&cluster3_l2>;
 385                         numa-node-id = <0>;
 386                 };
 387
 388                 cpu13: cpu@10301 {
 389                         device_type = "cpu";
 390                         compatible = "arm,cortex-a72", "arm,armv8";
 391                         reg = <0x10301>;
 392                         enable-method = "psci";
 393                         next-level-cache = <&cluster3_l2>;
 394                         numa-node-id = <0>;
 395                 };
 396
 397                 cpu14: cpu@10302 {
 398                         device_type = "cpu";
 399                         compatible = "arm,cortex-a72", "arm,armv8";
 400                         reg = <0x10302>;
 401                         enable-method = "psci";
 402                         next-level-cache = <&cluster3_l2>;
 403                         numa-node-id = <0>;
 404                 };
 405
 406                 cpu15: cpu@10303 {
 407                         device_type = "cpu";
 408                         compatible = "arm,cortex-a72", "arm,armv8";
 409                         reg = <0x10303>;
 410                         enable-method = "psci";
 411                         next-level-cache = <&cluster3_l2>;
 412                         numa-node-id = <0>;
 413                 };
 414
 415                 cpu16: cpu@30000 {
 416                         device_type = "cpu";
 417                         compatible = "arm,cortex-a72", "arm,armv8";
 418                         reg = <0x30000>;
 419                         enable-method = "psci";
 420                         next-level-cache = <&cluster4_l2>;
 421                         numa-node-id = <1>;
 422                 };
 423
 424                 cpu17: cpu@30001 {
 425                         device_type = "cpu";
 426                         compatible = "arm,cortex-a72", "arm,armv8";
 427                         reg = <0x30001>;
 428                         enable-method = "psci";
 429                         next-level-cache = <&cluster4_l2>;
 430                         numa-node-id = <1>;
 431                 };
 432
 433                 cpu18: cpu@30002 {
 434                         device_type = "cpu";
 435                         compatible = "arm,cortex-a72", "arm,armv8";
 436                         reg = <0x30002>;
 437                         enable-method = "psci";
 438                         next-level-cache = <&cluster4_l2>;
 439                         numa-node-id = <1>;
 440                 };
 441
 442                 cpu19: cpu@30003 {
 443                         device_type = "cpu";
 444                         compatible = "arm,cortex-a72", "arm,armv8";
 445                         reg = <0x30003>;
 446                         enable-method = "psci";
 447                         next-level-cache = <&cluster4_l2>;
 448                         numa-node-id = <1>;
 449                 };
 450
 451                 cpu20: cpu@30100 {
 452                         device_type = "cpu";
 453                         compatible = "arm,cortex-a72", "arm,armv8";
 454                         reg = <0x30100>;
 455                         enable-method = "psci";
 456                         next-level-cache = <&cluster5_l2>;
 457                         numa-node-id = <1>;
 458                 };
 459
 460                 cpu21: cpu@30101 {
 461                         device_type = "cpu";
 462                         compatible = "arm,cortex-a72", "arm,armv8";
 463                         reg = <0x30101>;
 464                         enable-method = "psci";
 465                         next-level-cache = <&cluster5_l2>;
 466                         numa-node-id = <1>;
 467                 };
 468
 469                 cpu22: cpu@30102 {
 470                         device_type = "cpu";
 471                         compatible = "arm,cortex-a72", "arm,armv8";
 472                         reg = <0x30102>;
 473                         enable-method = "psci";
 474                         next-level-cache = <&cluster5_l2>;
 475                         numa-node-id = <1>;
 476                 };
 477
 478                 cpu23: cpu@30103 {
 479                         device_type = "cpu";
 480                         compatible = "arm,cortex-a72", "arm,armv8";
 481                         reg = <0x30103>;
 482                         enable-method = "psci";
 483                         next-level-cache = <&cluster5_l2>;
 484                         numa-node-id = <1>;
 485                 };
 486
 487                 cpu24: cpu@30200 {
 488                         device_type = "cpu";
 489                         compatible = "arm,cortex-a72", "arm,armv8";
 490                         reg = <0x30200>;
 491                         enable-method = "psci";
 492                         next-level-cache = <&cluster6_l2>;
 493                         numa-node-id = <1>;
 494                 };
 495
 496                 cpu25: cpu@30201 {
 497                         device_type = "cpu";
 498                         compatible = "arm,cortex-a72", "arm,armv8";
 499                         reg = <0x30201>;
 500                         enable-method = "psci";
 501                         next-level-cache = <&cluster6_l2>;
 502                         numa-node-id = <1>;
 503                 };
 504
 505                 cpu26: cpu@30202 {
 506                         device_type = "cpu";
 507                         compatible = "arm,cortex-a72", "arm,armv8";
 508                         reg = <0x30202>;
 509                         enable-method = "psci";
 510                         next-level-cache = <&cluster6_l2>;
 511                         numa-node-id = <1>;
 512                 };
 513
 514                 cpu27: cpu@30203 {
 515                         device_type = "cpu";
 516                         compatible = "arm,cortex-a72", "arm,armv8";
 517                         reg = <0x30203>;
 518                         enable-method = "psci";
 519                         next-level-cache = <&cluster6_l2>;
 520                         numa-node-id = <1>;
 521                 };
 522
 523                 cpu28: cpu@30300 {
 524                         device_type = "cpu";
 525                         compatible = "arm,cortex-a72", "arm,armv8";
 526                         reg = <0x30300>;
 527                         enable-method = "psci";
 528                         next-level-cache = <&cluster7_l2>;
 529                         numa-node-id = <1>;
 530                 };
 531
 532                 cpu29: cpu@30301 {
 533                         device_type = "cpu";
 534                         compatible = "arm,cortex-a72", "arm,armv8";
 535                         reg = <0x30301>;
 536                         enable-method = "psci";
 537                         next-level-cache = <&cluster7_l2>;
 538                         numa-node-id = <1>;
 539                 };
 540
 541                 cpu30: cpu@30302 {
 542                         device_type = "cpu";
 543                         compatible = "arm,cortex-a72", "arm,armv8";
 544                         reg = <0x30302>;
 545                         enable-method = "psci";
 546                         next-level-cache = <&cluster7_l2>;
 547                         numa-node-id = <1>;
 548                 };
 549
 550                 cpu31: cpu@30303 {
 551                         device_type = "cpu";
 552                         compatible = "arm,cortex-a72", "arm,armv8";
 553                         reg = <0x30303>;
 554                         enable-method = "psci";
 555                         next-level-cache = <&cluster7_l2>;
 556                         numa-node-id = <1>;
 557                 };
 558
 559                 cpu32: cpu@50000 {
 560                         device_type = "cpu";
 561                         compatible = "arm,cortex-a72", "arm,armv8";
 562                         reg = <0x50000>;
 563                         enable-method = "psci";
 564                         next-level-cache = <&cluster8_l2>;
 565                         numa-node-id = <2>;
 566                 };
 567
 568                 cpu33: cpu@50001 {
 569                         device_type = "cpu";
 570                         compatible = "arm,cortex-a72", "arm,armv8";
 571                         reg = <0x50001>;
 572                         enable-method = "psci";
 573                         next-level-cache = <&cluster8_l2>;
 574                         numa-node-id = <2>;
 575                 };
 576
 577                 cpu34: cpu@50002 {
 578                         device_type = "cpu";
 579                         compatible = "arm,cortex-a72", "arm,armv8";
 580                         reg = <0x50002>;
 581                         enable-method = "psci";
 582                         next-level-cache = <&cluster8_l2>;
 583                         numa-node-id = <2>;
 584                 };
 585
 586                 cpu35: cpu@50003 {
 587                         device_type = "cpu";
 588                         compatible = "arm,cortex-a72", "arm,armv8";
 589                         reg = <0x50003>;
 590                         enable-method = "psci";
 591                         next-level-cache = <&cluster8_l2>;
 592                         numa-node-id = <2>;
 593                 };
 594
 595                 cpu36: cpu@50100 {
 596                         device_type = "cpu";
 597                         compatible = "arm,cortex-a72", "arm,armv8";
 598                         reg = <0x50100>;
 599                         enable-method = "psci";
 600                         next-level-cache = <&cluster9_l2>;
 601                         numa-node-id = <2>;
 602                 };
 603
 604                 cpu37: cpu@50101 {
 605                         device_type = "cpu";
 606                         compatible = "arm,cortex-a72", "arm,armv8";
 607                         reg = <0x50101>;
 608                         enable-method = "psci";
 609                         next-level-cache = <&cluster9_l2>;
 610                         numa-node-id = <2>;
 611                 };
 612
 613                 cpu38: cpu@50102 {
 614                         device_type = "cpu";
 615                         compatible = "arm,cortex-a72", "arm,armv8";
 616                         reg = <0x50102>;
 617                         enable-method = "psci";
 618                         next-level-cache = <&cluster9_l2>;
 619                         numa-node-id = <2>;
 620                 };
 621
 622                 cpu39: cpu@50103 {
 623                         device_type = "cpu";
 624                         compatible = "arm,cortex-a72", "arm,armv8";
 625                         reg = <0x50103>;
 626                         enable-method = "psci";
 627                         next-level-cache = <&cluster9_l2>;
 628                         numa-node-id = <2>;
 629                 };
 630
 631                 cpu40: cpu@50200 {
 632                         device_type = "cpu";
 633                         compatible = "arm,cortex-a72", "arm,armv8";
 634                         reg = <0x50200>;
 635                         enable-method = "psci";
 636                         next-level-cache = <&cluster10_l2>;
 637                         numa-node-id = <2>;
 638                 };
 639
 640                 cpu41: cpu@50201 {
 641                         device_type = "cpu";
 642                         compatible = "arm,cortex-a72", "arm,armv8";
 643                         reg = <0x50201>;
 644                         enable-method = "psci";
 645                         next-level-cache = <&cluster10_l2>;
 646                         numa-node-id = <2>;
 647                 };
 648
 649                 cpu42: cpu@50202 {
 650                         device_type = "cpu";
 651                         compatible = "arm,cortex-a72", "arm,armv8";
 652                         reg = <0x50202>;
 653                         enable-method = "psci";
 654                         next-level-cache = <&cluster10_l2>;
 655                         numa-node-id = <2>;
 656                 };
 657
 658                 cpu43: cpu@50203 {
 659                         device_type = "cpu";
 660                         compatible = "arm,cortex-a72", "arm,armv8";
 661                         reg = <0x50203>;
 662                         enable-method = "psci";
 663                         next-level-cache = <&cluster10_l2>;
 664                         numa-node-id = <2>;
 665                 };
 666
 667                 cpu44: cpu@50300 {
 668                         device_type = "cpu";
 669                         compatible = "arm,cortex-a72", "arm,armv8";
 670                         reg = <0x50300>;
 671                         enable-method = "psci";
 672                         next-level-cache = <&cluster11_l2>;
 673                         numa-node-id = <2>;
 674                 };
 675
 676                 cpu45: cpu@50301 {
 677                         device_type = "cpu";
 678                         compatible = "arm,cortex-a72", "arm,armv8";
 679                         reg = <0x50301>;
 680                         enable-method = "psci";
 681                         next-level-cache = <&cluster11_l2>;
 682                         numa-node-id = <2>;
 683                 };
 684
 685                 cpu46: cpu@50302 {
 686                         device_type = "cpu";
 687                         compatible = "arm,cortex-a72", "arm,armv8";
 688                         reg = <0x50302>;
 689                         enable-method = "psci";
 690                         next-level-cache = <&cluster11_l2>;
 691                         numa-node-id = <2>;
 692                 };
 693
 694                 cpu47: cpu@50303 {
 695                         device_type = "cpu";
 696                         compatible = "arm,cortex-a72", "arm,armv8";
 697                         reg = <0x50303>;
 698                         enable-method = "psci";
 699                         next-level-cache = <&cluster11_l2>;
 700                         numa-node-id = <2>;
 701                 };
 702
 703                 cpu48: cpu@70000 {
 704                         device_type = "cpu";
 705                         compatible = "arm,cortex-a72", "arm,armv8";
 706                         reg = <0x70000>;
 707                         enable-method = "psci";
 708                         next-level-cache = <&cluster12_l2>;
 709                         numa-node-id = <3>;
 710                 };
 711
 712                 cpu49: cpu@70001 {
 713                         device_type = "cpu";
 714                         compatible = "arm,cortex-a72", "arm,armv8";
 715                         reg = <0x70001>;
 716                         enable-method = "psci";
 717                         next-level-cache = <&cluster12_l2>;
 718                         numa-node-id = <3>;
 719                 };
 720
 721                 cpu50: cpu@70002 {
 722                         device_type = "cpu";
 723                         compatible = "arm,cortex-a72", "arm,armv8";
 724                         reg = <0x70002>;
 725                         enable-method = "psci";
 726                         next-level-cache = <&cluster12_l2>;
 727                         numa-node-id = <3>;
 728                 };
 729
 730                 cpu51: cpu@70003 {
 731                         device_type = "cpu";
 732                         compatible = "arm,cortex-a72", "arm,armv8";
 733                         reg = <0x70003>;
 734                         enable-method = "psci";
 735                         next-level-cache = <&cluster12_l2>;
 736                         numa-node-id = <3>;
 737                 };
 738
 739                 cpu52: cpu@70100 {
 740                         device_type = "cpu";
 741                         compatible = "arm,cortex-a72", "arm,armv8";
 742                         reg = <0x70100>;
 743                         enable-method = "psci";
 744                         next-level-cache = <&cluster13_l2>;
 745                         numa-node-id = <3>;
 746                 };
 747
 748                 cpu53: cpu@70101 {
 749                         device_type = "cpu";
 750                         compatible = "arm,cortex-a72", "arm,armv8";
 751                         reg = <0x70101>;
 752                         enable-method = "psci";
 753                         next-level-cache = <&cluster13_l2>;
 754                         numa-node-id = <3>;
 755                 };
 756
 757                 cpu54: cpu@70102 {
 758                         device_type = "cpu";
 759                         compatible = "arm,cortex-a72", "arm,armv8";
 760                         reg = <0x70102>;
 761                         enable-method = "psci";
 762                         next-level-cache = <&cluster13_l2>;
 763                         numa-node-id = <3>;
 764                 };
 765
 766                 cpu55: cpu@70103 {
 767                         device_type = "cpu";
 768                         compatible = "arm,cortex-a72", "arm,armv8";
 769                         reg = <0x70103>;
 770                         enable-method = "psci";
 771                         next-level-cache = <&cluster13_l2>;
 772                         numa-node-id = <3>;
 773                 };
 774
 775                 cpu56: cpu@70200 {
 776                         device_type = "cpu";
 777                         compatible = "arm,cortex-a72", "arm,armv8";
 778                         reg = <0x70200>;
 779                         enable-method = "psci";
 780                         next-level-cache = <&cluster14_l2>;
 781                         numa-node-id = <3>;
 782                 };
 783
 784                 cpu57: cpu@70201 {
 785                         device_type = "cpu";
 786                         compatible = "arm,cortex-a72", "arm,armv8";
 787                         reg = <0x70201>;
 788                         enable-method = "psci";
 789                         next-level-cache = <&cluster14_l2>;
 790                         numa-node-id = <3>;
 791                 };
 792
 793                 cpu58: cpu@70202 {
 794                         device_type = "cpu";
 795                         compatible = "arm,cortex-a72", "arm,armv8";
 796                         reg = <0x70202>;
 797                         enable-method = "psci";
 798                         next-level-cache = <&cluster14_l2>;
 799                         numa-node-id = <3>;
 800                 };
 801
 802                 cpu59: cpu@70203 {
 803                         device_type = "cpu";
 804                         compatible = "arm,cortex-a72", "arm,armv8";
 805                         reg = <0x70203>;
 806                         enable-method = "psci";
 807                         next-level-cache = <&cluster14_l2>;
 808                         numa-node-id = <3>;
 809                 };
 810
 811                 cpu60: cpu@70300 {
 812                         device_type = "cpu";
 813                         compatible = "arm,cortex-a72", "arm,armv8";
 814                         reg = <0x70300>;
 815                         enable-method = "psci";
 816                         next-level-cache = <&cluster15_l2>;
 817                         numa-node-id = <3>;
 818                 };
 819
 820                 cpu61: cpu@70301 {
 821                         device_type = "cpu";
 822                         compatible = "arm,cortex-a72", "arm,armv8";
 823                         reg = <0x70301>;
 824                         enable-method = "psci";
 825                         next-level-cache = <&cluster15_l2>;
 826                         numa-node-id = <3>;
 827                 };
 828
 829                 cpu62: cpu@70302 {
 830                         device_type = "cpu";
 831                         compatible = "arm,cortex-a72", "arm,armv8";
 832                         reg = <0x70302>;
 833                         enable-method = "psci";
 834                         next-level-cache = <&cluster15_l2>;
 835                         numa-node-id = <3>;
 836                 };
 837
 838                 cpu63: cpu@70303 {
 839                         device_type = "cpu";
 840                         compatible = "arm,cortex-a72", "arm,armv8";
 841                         reg = <0x70303>;
 842                         enable-method = "psci";
 843                         next-level-cache = <&cluster15_l2>;
 844                         numa-node-id = <3>;
 845                 };
 846
 847                 cluster0_l2: l2-cache0 {
 848                         compatible = "cache";
 849                 };
 850
 851                 cluster1_l2: l2-cache1 {
 852                         compatible = "cache";
 853                 };
 854
 855                 cluster2_l2: l2-cache2 {
 856                         compatible = "cache";
 857                 };
 858
 859                 cluster3_l2: l2-cache3 {
 860                         compatible = "cache";
 861                 };
 862
 863                 cluster4_l2: l2-cache4 {
 864                         compatible = "cache";
 865                 };
 866
 867                 cluster5_l2: l2-cache5 {
 868                         compatible = "cache";
 869                 };
 870
 871                 cluster6_l2: l2-cache6 {
 872                         compatible = "cache";
 873                 };
 874
 875                 cluster7_l2: l2-cache7 {
 876                         compatible = "cache";
 877                 };
 878
 879                 cluster8_l2: l2-cache8 {
 880                         compatible = "cache";
 881                 };
 882
 883                 cluster9_l2: l2-cache9 {
 884                         compatible = "cache";
 885                 };
 886
 887                 cluster10_l2: l2-cache10 {
 888                         compatible = "cache";
 889                 };
 890
 891                 cluster11_l2: l2-cache11 {
 892                         compatible = "cache";
 893                 };
 894
 895                 cluster12_l2: l2-cache12 {
 896                         compatible = "cache";
 897                 };
 898
 899                 cluster13_l2: l2-cache13 {
 900                         compatible = "cache";
 901                 };
 902
 903                 cluster14_l2: l2-cache14 {
 904                         compatible = "cache";
 905                 };
 906
 907                 cluster15_l2: l2-cache15 {
 908                         compatible = "cache";
 909                 };
 910         };
 911
 912         gic: interrupt-controller@4d000000 {
 913                 compatible = "arm,gic-v3";
 914                 #interrupt-cells = <3>;
 915                 #address-cells = <2>;
 916                 #size-cells = <2>;
 917                 ranges;
 918                 interrupt-controller;
 919                 #redistributor-regions = <4>;
 920                 redistributor-stride = <0x0 0x40000>;
 921                 reg = <0x0 0x4d000000 0x0 0x10000>,     /* GICD */
 922                       <0x0 0x4d100000 0x0 0x400000>,    /* p0 GICR node 0 */
 923                       <0x0 0x6d100000 0x0 0x400000>,    /* p0 GICR node 1 */
 924                       <0x400 0x4d100000 0x0 0x400000>,  /* p1 GICR node 2 */
 925                       <0x400 0x6d100000 0x0 0x400000>,  /* p1 GICR node 3 */
 926                       <0x0 0xfe000000 0x0 0x10000>,     /* GICC */
 927                       <0x0 0xfe010000 0x0 0x10000>,     /* GICH */
 928                       <0x0 0xfe020000 0x0 0x10000>;     /* GICV */
 929                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 930
 931                 p0_its_peri_a: interrupt-controller@4c000000 {
 932                         compatible = "arm,gic-v3-its";
 933                         msi-controller;
 934                         #msi-cells = <1>;
 935                         reg = <0x0 0x4c000000 0x0 0x40000>;
 936                 };
 937
 938                 p0_its_peri_b: interrupt-controller@6c000000 {
 939                         compatible = "arm,gic-v3-its";
 940                         msi-controller;
 941                         #msi-cells = <1>;
 942                         reg = <0x0 0x6c000000 0x0 0x40000>;
 943                 };
 944
 945                 p0_its_dsa_a: interrupt-controller@c6000000 {
 946                         compatible = "arm,gic-v3-its";
 947                         msi-controller;
 948                         #msi-cells = <1>;
 949                         reg = <0x0 0xc6000000 0x0 0x40000>;
 950                 };
 951
 952                 p0_its_dsa_b: interrupt-controller@8,c6000000 {
 953                         compatible = "arm,gic-v3-its";
 954                         msi-controller;
 955                         #msi-cells = <1>;
 956                         reg = <0x8 0xc6000000 0x0 0x40000>;
 957                 };
 958
 959                 p1_its_peri_a: interrupt-controller@400,4c000000 {
 960                         compatible = "arm,gic-v3-its";
 961                         msi-controller;
 962                         #msi-cells = <1>;
 963                         reg = <0x400 0x4c000000 0x0 0x40000>;
 964                 };
 965
 966                 p1_its_peri_b: interrupt-controller@400,6c000000 {
 967                         compatible = "arm,gic-v3-its";
 968                         msi-controller;
 969                         #msi-cells = <1>;
 970                         reg = <0x400 0x6c000000 0x0 0x40000>;
 971                 };
 972
 973                 p1_its_dsa_a: interrupt-controller@400,c6000000 {
 974                         compatible = "arm,gic-v3-its";
 975                         msi-controller;
 976                         #msi-cells = <1>;
 977                         reg = <0x400 0xc6000000 0x0 0x40000>;
 978                 };
 979
 980                 p1_its_dsa_b: interrupt-controller@408,c6000000 {
 981                         compatible = "arm,gic-v3-its";
 982                         msi-controller;
 983                         #msi-cells = <1>;
 984                         reg = <0x408 0xc6000000 0x0 0x40000>;
 985                 };
 986         };
 987
 988         timer {
 989                 compatible = "arm,armv8-timer";
 990                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 991                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 992                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 993                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 994         };
 995
 996         pmu {
 997                 compatible = "arm,cortex-a72-pmu";
 998                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 999         };
1000
1001         p0_mbigen_peri_b: interrupt-controller@60080000 {
1002                 compatible = "hisilicon,mbigen-v2";
1003                 reg = <0x0 0x60080000 0x0 0x10000>;
1004
1005                 mbigen_uart: uart_intc {
1006                         msi-parent = <&p0_its_peri_b 0x120c7>;
1007                         interrupt-controller;
1008                         #interrupt-cells = <2>;
1009                         num-pins = <1>;
1010                 };
1011         };
1012
1013         p0_mbigen_pcie_a: interrupt-controller@a0080000 {
1014                 compatible = "hisilicon,mbigen-v2";
1015                 reg = <0x0 0xa0080000 0x0 0x10000>;
1016
1017                 mbigen_pcie2_a: intc_pcie2_a {
1018                         msi-parent = <&p0_its_dsa_a 0x40087>;
1019                         interrupt-controller;
1020                         #interrupt-cells = <2>;
1021                         num-pins = <10>;
1022                 };
1023
1024                 mbigen_sas1: intc_sas1 {
1025                         msi-parent = <&p0_its_dsa_a 0x40000>;
1026                         interrupt-controller;
1027                         #interrupt-cells = <2>;
1028                         num-pins = <128>;
1029                 };
1030
1031                 mbigen_sas2: intc_sas2 {
1032                         msi-parent = <&p0_its_dsa_a 0x40040>;
1033                         interrupt-controller;
1034                         #interrupt-cells = <2>;
1035                         num-pins = <128>;
1036                 };
1037
1038                 mbigen_smmu_pcie: intc_smmu_pcie {
1039                         msi-parent = <&p0_its_dsa_a 0x40b0c>;
1040                         interrupt-controller;
1041                         #interrupt-cells = <2>;
1042                         num-pins = <3>;
1043                 };
1044
1045                 mbigen_usb: intc_usb {
1046                         msi-parent = <&p0_its_dsa_a 0x40080>;
1047                         interrupt-controller;
1048                         #interrupt-cells = <2>;
1049                         num-pins = <2>;
1050                 };
1051         };
1052
1053         p0_mbigen_dsa_a: interrupt-controller@c0080000 {
1054                 compatible = "hisilicon,mbigen-v2";
1055                 reg = <0x0 0xc0080000 0x0 0x10000>;
1056
1057                 mbigen_dsaf0: intc_dsaf0 {
1058                         msi-parent = <&p0_its_dsa_a 0x40800>;
1059                         interrupt-controller;
1060                         #interrupt-cells = <2>;
1061                         num-pins = <409>;
1062                 };
1063
1064                 mbigen_dsa_roce: intc-roce {
1065                         msi-parent = <&p0_its_dsa_a 0x40B1E>;
1066                         interrupt-controller;
1067                         #interrupt-cells = <2>;
1068                         num-pins = <34>;
1069                 };
1070
1071                 mbigen_sas0: intc-sas0 {
1072                         msi-parent = <&p0_its_dsa_a 0x40900>;
1073                         interrupt-controller;
1074                         #interrupt-cells = <2>;
1075                         num-pins = <128>;
1076                 };
1077
1078                 mbigen_smmu_dsa: intc_smmu_dsa {
1079                         msi-parent = <&p0_its_dsa_a 0x40b20>;
1080                         interrupt-controller;
1081                         #interrupt-cells = <2>;
1082                         num-pins = <3>;
1083                 };
1084         };
1085
1086         soc {
1087                 compatible = "simple-bus";
1088                 #address-cells = <2>;
1089                 #size-cells = <2>;
1090                 ranges;
1091
1092                 uart0: uart@602b0000 {
1093                         compatible = "arm,sbsa-uart";
1094                         reg = <0x0 0x602b0000 0x0 0x1000>;
1095                         interrupt-parent = <&mbigen_uart>;
1096                         interrupts = <807 4>;
1097                         current-speed = <115200>;
1098                         reg-io-width = <4>;
1099                         status = "disabled";
1100                 };
1101
1102                 usb_ohci: ohci@a7030000 {
1103                         compatible = "generic-ohci";
1104                         reg = <0x0 0xa7030000 0x0 0x10000>;
1105                         interrupt-parent = <&mbigen_usb>;
1106                         interrupts = <640 4>;
1107                         dma-coherent;
1108                         status = "disabled";
1109                 };
1110
1111                 usb_ehci: ehci@a7020000 {
1112                         compatible = "generic-ehci";
1113                         reg = <0x0 0xa7020000 0x0 0x10000>;
1114                         interrupt-parent = <&mbigen_usb>;
1115                         interrupts = <641 4>;
1116                         dma-coherent;
1117                         status = "disabled";
1118                 };
1119
1120                 peri_c_subctrl: sub_ctrl_c@60000000 {
1121                         compatible = "hisilicon,peri-subctrl","syscon";
1122                         reg = <0 0x60000000 0x0 0x10000>;
1123                 };
1124
1125                 dsa_subctrl: dsa_subctrl@c0000000 {
1126                         compatible = "hisilicon,dsa-subctrl", "syscon";
1127                         reg = <0x0 0xc0000000 0x0 0x10000>;
1128                 };
1129
1130                 pcie_subctl: pcie_subctl@a0000000 {
1131                         compatible = "hisilicon,pcie-sas-subctrl", "syscon";
1132                         reg = <0x0 0xa0000000 0x0 0x10000>;
1133                 };
1134
1135                 serdes_ctrl: sds_ctrl@c2200000 {
1136                         compatible = "syscon";
1137                         reg = <0 0xc2200000 0x0 0x80000>;
1138                 };
1139
1140                 mdio@603c0000 {
1141                         compatible = "hisilicon,hns-mdio";
1142                         reg = <0x0 0x603c0000 0x0 0x1000>;
1143                         subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
1144                                          0x531c 0x5a1c>;
1145                         #address-cells = <1>;
1146                         #size-cells = <0>;
1147
1148                         phy0: ethernet-phy@0 {
1149                                 compatible = "ethernet-phy-ieee802.3-c22";
1150                                 reg = <0>;
1151                         };
1152
1153                         phy1: ethernet-phy@1 {
1154                                 compatible = "ethernet-phy-ieee802.3-c22";
1155                                 reg = <1>;
1156                         };
1157                 };
1158
1159                 dsaf0: dsa@c7000000 {
1160                         #address-cells = <1>;
1161                         #size-cells = <0>;
1162                         compatible = "hisilicon,hns-dsaf-v2";
1163                         mode = "6port-16rss";
1164                         reg = <0x0 0xc5000000 0x0 0x890000
1165                                0x0 0xc7000000 0x0 0x600000>;
1166                         reg-names = "ppe-base", "dsaf-base";
1167                         interrupt-parent = <&mbigen_dsaf0>;
1168                         subctrl-syscon = <&dsa_subctrl>;
1169                         reset-field-offset = <0>;
1170                         interrupts =
1171                         <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
1172                         <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
1173                         <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
1174                         <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
1175                         <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
1176                         <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
1177                         <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
1178                         <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
1179                         <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
1180                         <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
1181                         <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
1182                         <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
1183                         <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
1184                         <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
1185                         <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
1186                         <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
1187                         <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
1188                         <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
1189                         <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
1190                         <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
1191                         <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
1192                         <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
1193                         <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
1194                         <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
1195                         <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
1196                         <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
1197                         <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
1198                         <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
1199                         <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
1200                         <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
1201                         <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
1202                         <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
1203                         <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
1204                         <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
1205                         <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
1206                         <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
1207                         <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
1208                         <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
1209                         <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
1210                         <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
1211                         <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
1212                         <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
1213                         <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
1214                         <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
1215                         <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
1216                         <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
1217                         <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
1218                         <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
1219                         <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
1220                         <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
1221                         <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
1222                         <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
1223                         <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
1224                         <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
1225                         <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
1226                         <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
1227                         <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
1228                         <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
1229                         <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
1230                         <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
1231                         <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
1232                         <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
1233                         <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
1234                         <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
1235                         <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
1236                         <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
1237                         <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
1238                         <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
1239                         <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
1240                         <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
1241                         <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
1242                         <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
1243                         <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
1244                         <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
1245                         <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
1246                         <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
1247                         <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
1248                         <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
1249                         <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
1250                         <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
1251                         <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
1252                         <1340 1>, <1341 1>, <1342 1>, <1343 1>;
1253
1254                         desc-num = <0x400>;
1255                         buf-size = <0x1000>;
1256                         dma-coherent;
1257
1258                         port@0 {
1259                                 reg = <0>;
1260                                 serdes-syscon = <&serdes_ctrl>;
1261                                 port-rst-offset = <0>;
1262                                 port-mode-offset = <0>;
1263                                 mc-mac-mask = [ff f0 00 00 00 00];
1264                                 media-type = "fiber";
1265                         };
1266
1267                         port@1 {
1268                                 reg = <1>;
1269                                 serdes-syscon= <&serdes_ctrl>;
1270                                 port-rst-offset = <1>;
1271                                 port-mode-offset = <1>;
1272                                 mc-mac-mask = [ff f0 00 00 00 00];
1273                                 media-type = "fiber";
1274                         };
1275
1276                         port@4 {
1277                                 reg = <4>;
1278                                 phy-handle = <&phy0>;
1279                                 serdes-syscon= <&serdes_ctrl>;
1280                                 port-rst-offset = <4>;
1281                                 port-mode-offset = <2>;
1282                                 mc-mac-mask = [ff f0 00 00 00 00];
1283                                 media-type = "copper";
1284                         };
1285
1286                         port@5 {
1287                                 reg = <5>;
1288                                 phy-handle = <&phy1>;
1289                                 serdes-syscon= <&serdes_ctrl>;
1290                                 port-rst-offset = <5>;
1291                                 port-mode-offset = <3>;
1292                                 mc-mac-mask = [ff f0 00 00 00 00];
1293                                 media-type = "copper";
1294                         };
1295                 };
1296
1297                 eth0: ethernet@4{
1298                         compatible = "hisilicon,hns-nic-v2";
1299                         ae-handle = <&dsaf0>;
1300                         port-idx-in-ae = <4>;
1301                         local-mac-address = [00 00 00 00 00 00];
1302                         status = "disabled";
1303                         dma-coherent;
1304                 };
1305
1306                 eth1: ethernet@5{
1307                         compatible = "hisilicon,hns-nic-v2";
1308                         ae-handle = <&dsaf0>;
1309                         port-idx-in-ae = <5>;
1310                         local-mac-address = [00 00 00 00 00 00];
1311                         status = "disabled";
1312                         dma-coherent;
1313                 };
1314
1315                 eth2: ethernet@0{
1316                         compatible = "hisilicon,hns-nic-v2";
1317                         ae-handle = <&dsaf0>;
1318                         port-idx-in-ae = <0>;
1319                         local-mac-address = [00 00 00 00 00 00];
1320                         status = "disabled";
1321                         dma-coherent;
1322                 };
1323
1324                 eth3: ethernet@1{
1325                         compatible = "hisilicon,hns-nic-v2";
1326                         ae-handle = <&dsaf0>;
1327                         port-idx-in-ae = <1>;
1328                         local-mac-address = [00 00 00 00 00 00];
1329                         status = "disabled";
1330                         dma-coherent;
1331                 };
1332
1333                 infiniband@c4000000 {
1334                         compatible = "hisilicon,hns-roce-v1";
1335                         reg = <0x0 0xc4000000 0x0 0x100000>;
1336                         dma-coherent;
1337                         eth-handle = <&eth2 &eth3 0 0 &eth0 &eth1>;
1338                         dsaf-handle = <&dsaf0>;
1339                         node-guid = [00 9A CD 00 00 01 02 03];
1340                         #address-cells = <2>;
1341                         #size-cells = <2>;
1342                         interrupt-parent = <&mbigen_dsa_roce>;
1343                         interrupts = <722 1>,
1344                                      <723 1>,
1345                                      <724 1>,
1346                                      <725 1>,
1347                                      <726 1>,
1348                                      <727 1>,
1349                                      <728 1>,
1350                                      <729 1>,
1351                                      <730 1>,
1352                                      <731 1>,
1353                                      <732 1>,
1354                                      <733 1>,
1355                                      <734 1>,
1356                                      <735 1>,
1357                                      <736 1>,
1358                                      <737 1>,
1359                                      <738 1>,
1360                                      <739 1>,
1361                                      <740 1>,
1362                                      <741 1>,
1363                                      <742 1>,
1364                                      <743 1>,
1365                                      <744 1>,
1366                                      <745 1>,
1367                                      <746 1>,
1368                                      <747 1>,
1369                                      <748 1>,
1370                                      <749 1>,
1371                                      <750 1>,
1372                                      <751 1>,
1373                                      <752 1>,
1374                                      <753 1>,
1375                                      <785 1>,
1376                                      <754 4>;
1377
1378                         interrupt-names = "hns-roce-comp-0",
1379                                           "hns-roce-comp-1",
1380                                           "hns-roce-comp-2",
1381                                           "hns-roce-comp-3",
1382                                           "hns-roce-comp-4",
1383                                           "hns-roce-comp-5",
1384                                           "hns-roce-comp-6",
1385                                           "hns-roce-comp-7",
1386                                           "hns-roce-comp-8",
1387                                           "hns-roce-comp-9",
1388                                           "hns-roce-comp-10",
1389                                           "hns-roce-comp-11",
1390                                           "hns-roce-comp-12",
1391                                           "hns-roce-comp-13",
1392                                           "hns-roce-comp-14",
1393                                           "hns-roce-comp-15",
1394                                           "hns-roce-comp-16",
1395                                           "hns-roce-comp-17",
1396                                           "hns-roce-comp-18",
1397                                           "hns-roce-comp-19",
1398                                           "hns-roce-comp-20",
1399                                           "hns-roce-comp-21",
1400                                           "hns-roce-comp-22",
1401                                           "hns-roce-comp-23",
1402                                           "hns-roce-comp-24",
1403                                           "hns-roce-comp-25",
1404                                           "hns-roce-comp-26",
1405                                           "hns-roce-comp-27",
1406                                           "hns-roce-comp-28",
1407                                           "hns-roce-comp-29",
1408                                           "hns-roce-comp-30",
1409                                           "hns-roce-comp-31",
1410                                           "hns-roce-async",
1411                                           "hns-roce-common";
1412                 };
1413
1414                 sas0: sas@c3000000 {
1415                         compatible = "hisilicon,hip07-sas-v2";
1416                         reg = <0 0xc3000000 0 0x10000>;
1417                         sas-addr = [50 01 88 20 16 00 00 00];
1418                         hisilicon,sas-syscon = <&dsa_subctrl>;
1419                         ctrl-reset-reg = <0xa60>;
1420                         ctrl-reset-sts-reg = <0x5a30>;
1421                         ctrl-clock-ena-reg = <0x338>;
1422                         queue-count = <16>;
1423                         phy-count = <8>;
1424                         dma-coherent;
1425                         interrupt-parent = <&mbigen_sas0>;
1426                         interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
1427                                      <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
1428                                      <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
1429                                      <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
1430                                      <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
1431                                      <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
1432                                      <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
1433                                      <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
1434                                      <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
1435                                      <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
1436                                      <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
1437                                      <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
1438                                      <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
1439                                      <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
1440                                      <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
1441                                      <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
1442                                      <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
1443                                      <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
1444                                      <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
1445                                      <159 4>,<601 1>,<602 1>,<603 1>,<604 1>,
1446                                      <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
1447                                      <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
1448                                      <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
1449                                      <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
1450                                      <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
1451                                      <630 1>,<631 1>,<632 1>;
1452                         status = "disabled";
1453                 };
1454
1455                 sas1: sas@a2000000 {
1456                         compatible = "hisilicon,hip07-sas-v2";
1457                         reg = <0 0xa2000000 0 0x10000>;
1458                         sas-addr = [50 01 88 20 16 00 00 00];
1459                         hisilicon,sas-syscon = <&pcie_subctl>;
1460                         hip06-sas-v2-quirk-amt;
1461                         ctrl-reset-reg = <0xa18>;
1462                         ctrl-reset-sts-reg = <0x5a0c>;
1463                         ctrl-clock-ena-reg = <0x318>;
1464                         queue-count = <16>;
1465                         phy-count = <8>;
1466                         dma-coherent;
1467                         interrupt-parent = <&mbigen_sas1>;
1468                         interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
1469                                      <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
1470                                      <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
1471                                      <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
1472                                      <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
1473                                      <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
1474                                      <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
1475                                      <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
1476                                      <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
1477                                      <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
1478                                      <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
1479                                      <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
1480                                      <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
1481                                      <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
1482                                      <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
1483                                      <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
1484                                      <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
1485                                      <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
1486                                      <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
1487                                      <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
1488                                      <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
1489                                      <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
1490                                      <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
1491                                      <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
1492                                      <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
1493                                      <605 1>,<606 1>,<607 1>;
1494                         status = "disabled";
1495                 };
1496
1497                 sas2: sas@a3000000 {
1498                         compatible = "hisilicon,hip07-sas-v2";
1499                         reg = <0 0xa3000000 0 0x10000>;
1500                         sas-addr = [50 01 88 20 16 00 00 00];
1501                         hisilicon,sas-syscon = <&pcie_subctl>;
1502                         ctrl-reset-reg = <0xae0>;
1503                         ctrl-reset-sts-reg = <0x5a70>;
1504                         ctrl-clock-ena-reg = <0x3a8>;
1505                         queue-count = <16>;
1506                         phy-count = <9>;
1507                         dma-coherent;
1508                         interrupt-parent = <&mbigen_sas2>;
1509                         interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
1510                                      <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
1511                                      <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
1512                                      <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
1513                                      <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
1514                                      <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
1515                                      <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
1516                                      <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
1517                                      <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
1518                                      <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
1519                                      <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
1520                                      <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
1521                                      <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
1522                                      <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
1523                                      <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
1524                                      <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
1525                                      <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
1526                                      <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
1527                                      <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
1528                                      <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
1529                                      <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
1530                                      <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
1531                                      <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
1532                                      <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
1533                                      <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
1534                                      <637 1>,<638 1>,<639 1>;
1535                         status = "disabled";
1536                 };
1537
1538                 p0_pcie2_a: pcie@a00a0000 {
1539                         compatible = "hisilicon,hip07-pcie-ecam";
1540                         reg = <0 0xaf800000 0 0x800000>,
1541                               <0 0xa00a0000 0 0x10000>;
1542                         bus-range = <0xf8 0xff>;
1543                         msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
1544                         msi-map-mask = <0xffff>;
1545                         #address-cells = <3>;
1546                         #size-cells = <2>;
1547                         device_type = "pci";
1548                         dma-coherent;
1549                         ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000
1550                                   0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
1551                         #interrupt-cells = <1>;
1552                         interrupt-map-mask = <0xf800 0 0 7>;
1553                         interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
1554                                          0x0 0 0 2 &mbigen_pcie2_a 671 4
1555                                          0x0 0 0 3 &mbigen_pcie2_a 671 4
1556                                          0x0 0 0 4 &mbigen_pcie2_a 671 4>;
1557                         status = "disabled";
1558                 };
1559         };
1560 };