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mtd: nand: atmel: Relax tADL_min constraint
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / boot / dts / marvell / armada-cp110-master.dtsi
1 /*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 /*
44 * Device Tree file for Marvell Armada CP110 Master.
45 */
46
47 #define ICU_GRP_NSR 0x0
48
49 / {
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&cpm_icu>;
55 ranges;
56
57 config-space@f2000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf2000000 0x2000000>;
62
63 cpm_ethernet: ethernet@0 {
64 compatible = "marvell,armada-7k-pp22";
65 reg = <0x0 0x100000>, <0x129000 0xb000>;
66 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
67 clock-names = "pp_clk", "gop_clk", "mg_clk";
68 status = "disabled";
69 dma-coherent;
70
71 cpm_eth0: eth0 {
72 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
73 port-id = <0>;
74 gop-port-id = <0>;
75 status = "disabled";
76 };
77
78 cpm_eth1: eth1 {
79 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
80 port-id = <1>;
81 gop-port-id = <2>;
82 status = "disabled";
83 };
84
85 cpm_eth2: eth2 {
86 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
87 port-id = <2>;
88 gop-port-id = <3>;
89 status = "disabled";
90 };
91 };
92
93 cpm_mdio: mdio@12a200 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 compatible = "marvell,orion-mdio";
97 reg = <0x12a200 0x10>;
98 clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
99 status = "disabled";
100 };
101
102 cpm_xmdio: mdio@12a600 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 compatible = "marvell,xmdio";
106 reg = <0x12a600 0x10>;
107 status = "disabled";
108 };
109
110 cpm_icu: interrupt-controller@1e0000 {
111 compatible = "marvell,cp110-icu";
112 reg = <0x1e0000 0x10>;
113 #interrupt-cells = <3>;
114 interrupt-controller;
115 msi-parent = <&gicp>;
116 };
117
118 cpm_syscon0: system-controller@440000 {
119 compatible = "syscon", "simple-mfd";
120 reg = <0x440000 0x1000>;
121
122 cpm_clk: clock {
123 compatible = "marvell,cp110-clock";
124 #clock-cells = <2>;
125 };
126
127 cpm_gpio1: gpio@100 {
128 compatible = "marvell,armada-8k-gpio";
129 offset = <0x100>;
130 ngpios = <32>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&cpm_pinctrl 0 0 32>;
134 status = "disabled";
135
136 };
137
138 cpm_gpio2: gpio@140 {
139 compatible = "marvell,armada-8k-gpio";
140 offset = <0x140>;
141 ngpios = <31>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 gpio-ranges = <&cpm_pinctrl 0 32 31>;
145 status = "disabled";
146 };
147 };
148
149 cpm_rtc: rtc@284000 {
150 compatible = "marvell,armada-8k-rtc";
151 reg = <0x284000 0x20>, <0x284080 0x24>;
152 reg-names = "rtc", "rtc-soc";
153 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
154 };
155
156 cpm_sata0: sata@540000 {
157 compatible = "marvell,armada-8k-ahci",
158 "generic-ahci";
159 reg = <0x540000 0x30000>;
160 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cpm_clk 1 15>;
162 status = "disabled";
163 };
164
165 cpm_usb3_0: usb3@500000 {
166 compatible = "marvell,armada-8k-xhci",
167 "generic-xhci";
168 reg = <0x500000 0x4000>;
169 dma-coherent;
170 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&cpm_clk 1 22>;
172 status = "disabled";
173 };
174
175 cpm_usb3_1: usb3@510000 {
176 compatible = "marvell,armada-8k-xhci",
177 "generic-xhci";
178 reg = <0x510000 0x4000>;
179 dma-coherent;
180 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cpm_clk 1 23>;
182 status = "disabled";
183 };
184
185 cpm_xor0: xor@6a0000 {
186 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
187 reg = <0x6a0000 0x1000>,
188 <0x6b0000 0x1000>;
189 dma-coherent;
190 msi-parent = <&gic_v2m0>;
191 clocks = <&cpm_clk 1 8>;
192 };
193
194 cpm_xor1: xor@6c0000 {
195 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
196 reg = <0x6c0000 0x1000>,
197 <0x6d0000 0x1000>;
198 dma-coherent;
199 msi-parent = <&gic_v2m0>;
200 clocks = <&cpm_clk 1 7>;
201 };
202
203 cpm_spi0: spi@700600 {
204 compatible = "marvell,armada-380-spi";
205 reg = <0x700600 0x50>;
206 #address-cells = <0x1>;
207 #size-cells = <0x0>;
208 cell-index = <1>;
209 clocks = <&cpm_clk 1 21>;
210 status = "disabled";
211 };
212
213 cpm_spi1: spi@700680 {
214 compatible = "marvell,armada-380-spi";
215 reg = <0x700680 0x50>;
216 #address-cells = <1>;
217 #size-cells = <0>;
218 cell-index = <2>;
219 clocks = <&cpm_clk 1 21>;
220 status = "disabled";
221 };
222
223 cpm_i2c0: i2c@701000 {
224 compatible = "marvell,mv78230-i2c";
225 reg = <0x701000 0x20>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&cpm_clk 1 21>;
230 status = "disabled";
231 };
232
233 cpm_i2c1: i2c@701100 {
234 compatible = "marvell,mv78230-i2c";
235 reg = <0x701100 0x20>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpm_clk 1 21>;
240 status = "disabled";
241 };
242
243 cpm_trng: trng@760000 {
244 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
245 reg = <0x760000 0x7d>;
246 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cpm_clk 1 25>;
248 status = "okay";
249 };
250
251 cpm_sdhci0: sdhci@780000 {
252 compatible = "marvell,armada-cp110-sdhci";
253 reg = <0x780000 0x300>;
254 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
255 clock-names = "core";
256 clocks = <&cpm_clk 1 4>;
257 dma-coherent;
258 status = "disabled";
259 };
260
261 cpm_crypto: crypto@800000 {
262 compatible = "inside-secure,safexcel-eip197";
263 reg = <0x800000 0x200000>;
264 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
265 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
266 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
267 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
268 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
269 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
270 interrupt-names = "mem", "ring0", "ring1",
271 "ring2", "ring3", "eip";
272 clocks = <&cpm_clk 1 26>;
273 };
274 };
275
276 cpm_pcie0: pcie@f2600000 {
277 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
278 reg = <0 0xf2600000 0 0x10000>,
279 <0 0xf6f00000 0 0x80000>;
280 reg-names = "ctrl", "config";
281 #address-cells = <3>;
282 #size-cells = <2>;
283 #interrupt-cells = <1>;
284 device_type = "pci";
285 dma-coherent;
286 msi-parent = <&gic_v2m0>;
287
288 bus-range = <0 0xff>;
289 ranges =
290 /* downstream I/O */
291 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
292 /* non-prefetchable memory */
293 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
294 interrupt-map-mask = <0 0 0 0>;
295 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
296 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
297 num-lanes = <1>;
298 clocks = <&cpm_clk 1 13>;
299 status = "disabled";
300 };
301
302 cpm_pcie1: pcie@f2620000 {
303 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
304 reg = <0 0xf2620000 0 0x10000>,
305 <0 0xf7f00000 0 0x80000>;
306 reg-names = "ctrl", "config";
307 #address-cells = <3>;
308 #size-cells = <2>;
309 #interrupt-cells = <1>;
310 device_type = "pci";
311 dma-coherent;
312 msi-parent = <&gic_v2m0>;
313
314 bus-range = <0 0xff>;
315 ranges =
316 /* downstream I/O */
317 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
318 /* non-prefetchable memory */
319 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
320 interrupt-map-mask = <0 0 0 0>;
321 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
322 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
323
324 num-lanes = <1>;
325 clocks = <&cpm_clk 1 11>;
326 status = "disabled";
327 };
328
329 cpm_pcie2: pcie@f2640000 {
330 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
331 reg = <0 0xf2640000 0 0x10000>,
332 <0 0xf8f00000 0 0x80000>;
333 reg-names = "ctrl", "config";
334 #address-cells = <3>;
335 #size-cells = <2>;
336 #interrupt-cells = <1>;
337 device_type = "pci";
338 dma-coherent;
339 msi-parent = <&gic_v2m0>;
340
341 bus-range = <0 0xff>;
342 ranges =
343 /* downstream I/O */
344 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
345 /* non-prefetchable memory */
346 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
347 interrupt-map-mask = <0 0 0 0>;
348 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
349 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
350
351 num-lanes = <1>;
352 clocks = <&cpm_clk 1 12>;
353 status = "disabled";
354 };
355 };
356 };
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