2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
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14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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44 * Device Tree file for Marvell Armada CP110 Master.
47 #define ICU_GRP_NSR 0x0
53 compatible = "simple-bus";
54 interrupt-parent = <&cpm_icu>;
57 config-space@f2000000 {
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf2000000 0x2000000>;
63 cpm_ethernet: ethernet@0 {
64 compatible = "marvell,armada-7k-pp22";
65 reg = <0x0 0x100000>, <0x129000 0xb000>;
66 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
67 clock-names = "pp_clk", "gop_clk", "mg_clk";
72 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
79 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
86 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
93 cpm_mdio: mdio@12a200 {
96 compatible = "marvell,orion-mdio";
97 reg = <0x12a200 0x10>;
98 clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
102 cpm_xmdio: mdio@12a600 {
103 #address-cells = <1>;
105 compatible = "marvell,xmdio";
106 reg = <0x12a600 0x10>;
110 cpm_icu: interrupt-controller@1e0000 {
111 compatible = "marvell,cp110-icu";
112 reg = <0x1e0000 0x10>;
113 #interrupt-cells = <3>;
114 interrupt-controller;
115 msi-parent = <&gicp>;
118 cpm_syscon0: system-controller@440000 {
119 compatible = "syscon", "simple-mfd";
120 reg = <0x440000 0x1000>;
123 compatible = "marvell,cp110-clock";
127 cpm_gpio1: gpio@100 {
128 compatible = "marvell,armada-8k-gpio";
133 gpio-ranges = <&cpm_pinctrl 0 0 32>;
138 cpm_gpio2: gpio@140 {
139 compatible = "marvell,armada-8k-gpio";
144 gpio-ranges = <&cpm_pinctrl 0 32 31>;
149 cpm_rtc: rtc@284000 {
150 compatible = "marvell,armada-8k-rtc";
151 reg = <0x284000 0x20>, <0x284080 0x24>;
152 reg-names = "rtc", "rtc-soc";
153 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
156 cpm_sata0: sata@540000 {
157 compatible = "marvell,armada-8k-ahci",
159 reg = <0x540000 0x30000>;
160 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cpm_clk 1 15>;
165 cpm_usb3_0: usb3@500000 {
166 compatible = "marvell,armada-8k-xhci",
168 reg = <0x500000 0x4000>;
170 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&cpm_clk 1 22>;
175 cpm_usb3_1: usb3@510000 {
176 compatible = "marvell,armada-8k-xhci",
178 reg = <0x510000 0x4000>;
180 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cpm_clk 1 23>;
185 cpm_xor0: xor@6a0000 {
186 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
187 reg = <0x6a0000 0x1000>,
190 msi-parent = <&gic_v2m0>;
191 clocks = <&cpm_clk 1 8>;
194 cpm_xor1: xor@6c0000 {
195 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
196 reg = <0x6c0000 0x1000>,
199 msi-parent = <&gic_v2m0>;
200 clocks = <&cpm_clk 1 7>;
203 cpm_spi0: spi@700600 {
204 compatible = "marvell,armada-380-spi";
205 reg = <0x700600 0x50>;
206 #address-cells = <0x1>;
209 clocks = <&cpm_clk 1 21>;
213 cpm_spi1: spi@700680 {
214 compatible = "marvell,armada-380-spi";
215 reg = <0x700680 0x50>;
216 #address-cells = <1>;
219 clocks = <&cpm_clk 1 21>;
223 cpm_i2c0: i2c@701000 {
224 compatible = "marvell,mv78230-i2c";
225 reg = <0x701000 0x20>;
226 #address-cells = <1>;
228 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&cpm_clk 1 21>;
233 cpm_i2c1: i2c@701100 {
234 compatible = "marvell,mv78230-i2c";
235 reg = <0x701100 0x20>;
236 #address-cells = <1>;
238 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpm_clk 1 21>;
243 cpm_trng: trng@760000 {
244 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
245 reg = <0x760000 0x7d>;
246 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cpm_clk 1 25>;
251 cpm_sdhci0: sdhci@780000 {
252 compatible = "marvell,armada-cp110-sdhci";
253 reg = <0x780000 0x300>;
254 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
255 clock-names = "core";
256 clocks = <&cpm_clk 1 4>;
261 cpm_crypto: crypto@800000 {
262 compatible = "inside-secure,safexcel-eip197";
263 reg = <0x800000 0x200000>;
264 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
265 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
266 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
267 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
268 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
269 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
270 interrupt-names = "mem", "ring0", "ring1",
271 "ring2", "ring3", "eip";
272 clocks = <&cpm_clk 1 26>;
277 cpm_pcie0: pcie@f2600000 {
278 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
279 reg = <0 0xf2600000 0 0x10000>,
280 <0 0xf6f00000 0 0x80000>;
281 reg-names = "ctrl", "config";
282 #address-cells = <3>;
284 #interrupt-cells = <1>;
287 msi-parent = <&gic_v2m0>;
289 bus-range = <0 0xff>;
292 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
293 /* non-prefetchable memory */
294 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
295 interrupt-map-mask = <0 0 0 0>;
296 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
297 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cpm_clk 1 13>;
303 cpm_pcie1: pcie@f2620000 {
304 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
305 reg = <0 0xf2620000 0 0x10000>,
306 <0 0xf7f00000 0 0x80000>;
307 reg-names = "ctrl", "config";
308 #address-cells = <3>;
310 #interrupt-cells = <1>;
313 msi-parent = <&gic_v2m0>;
315 bus-range = <0 0xff>;
318 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
319 /* non-prefetchable memory */
320 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
321 interrupt-map-mask = <0 0 0 0>;
322 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
323 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&cpm_clk 1 11>;
330 cpm_pcie2: pcie@f2640000 {
331 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
332 reg = <0 0xf2640000 0 0x10000>,
333 <0 0xf8f00000 0 0x80000>;
334 reg-names = "ctrl", "config";
335 #address-cells = <3>;
337 #interrupt-cells = <1>;
340 msi-parent = <&gic_v2m0>;
342 bus-range = <0 0xff>;
345 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
346 /* non-prefetchable memory */
347 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
348 interrupt-map-mask = <0 0 0 0>;
349 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
350 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cpm_clk 1 12>;