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Merge tag 'fbdev-v4.14' of git://github.com/bzolnier/linux
[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / marvell / armada-cp110-master.dtsi
1 /*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 /*
44 * Device Tree file for Marvell Armada CP110 Master.
45 */
46
47 #define ICU_GRP_NSR 0x0
48
49 / {
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&cpm_icu>;
55 ranges;
56
57 config-space@f2000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf2000000 0x2000000>;
62
63 cpm_ethernet: ethernet@0 {
64 compatible = "marvell,armada-7k-pp22";
65 reg = <0x0 0x100000>, <0x129000 0xb000>;
66 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
67 clock-names = "pp_clk", "gop_clk", "mg_clk";
68 marvell,system-controller = <&cpm_syscon0>;
69 status = "disabled";
70 dma-coherent;
71
72 cpm_eth0: eth0 {
73 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
74 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
75 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
76 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
77 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
79 "tx-cpu3", "rx-shared";
80 port-id = <0>;
81 gop-port-id = <0>;
82 status = "disabled";
83 };
84
85 cpm_eth1: eth1 {
86 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
87 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
88 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
89 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
90 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
91 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
92 "tx-cpu3", "rx-shared";
93 port-id = <1>;
94 gop-port-id = <2>;
95 status = "disabled";
96 };
97
98 cpm_eth2: eth2 {
99 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
100 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
101 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
102 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
103 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
104 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
105 "tx-cpu3", "rx-shared";
106 port-id = <2>;
107 gop-port-id = <3>;
108 status = "disabled";
109 };
110 };
111
112 cpm_mdio: mdio@12a200 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 compatible = "marvell,orion-mdio";
116 reg = <0x12a200 0x10>;
117 clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
118 status = "disabled";
119 };
120
121 cpm_xmdio: mdio@12a600 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 compatible = "marvell,xmdio";
125 reg = <0x12a600 0x10>;
126 status = "disabled";
127 };
128
129 cpm_icu: interrupt-controller@1e0000 {
130 compatible = "marvell,cp110-icu";
131 reg = <0x1e0000 0x10>;
132 #interrupt-cells = <3>;
133 interrupt-controller;
134 msi-parent = <&gicp>;
135 };
136
137 cpm_rtc: rtc@284000 {
138 compatible = "marvell,armada-8k-rtc";
139 reg = <0x284000 0x20>, <0x284080 0x24>;
140 reg-names = "rtc", "rtc-soc";
141 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
142 };
143
144 cpm_syscon0: system-controller@440000 {
145 compatible = "syscon", "simple-mfd";
146 reg = <0x440000 0x1000>;
147
148 cpm_clk: clock {
149 compatible = "marvell,cp110-clock";
150 #clock-cells = <2>;
151 };
152
153 cpm_gpio1: gpio@100 {
154 compatible = "marvell,armada-8k-gpio";
155 offset = <0x100>;
156 ngpios = <32>;
157 gpio-controller;
158 #gpio-cells = <2>;
159 gpio-ranges = <&cpm_pinctrl 0 0 32>;
160 interrupt-controller;
161 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
162 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
163 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
164 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
165 status = "disabled";
166 };
167
168 cpm_gpio2: gpio@140 {
169 compatible = "marvell,armada-8k-gpio";
170 offset = <0x140>;
171 ngpios = <31>;
172 gpio-controller;
173 #gpio-cells = <2>;
174 gpio-ranges = <&cpm_pinctrl 0 32 31>;
175 interrupt-controller;
176 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
177 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
178 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
179 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
180 status = "disabled";
181 };
182 };
183
184 cpm_usb3_0: usb3@500000 {
185 compatible = "marvell,armada-8k-xhci",
186 "generic-xhci";
187 reg = <0x500000 0x4000>;
188 dma-coherent;
189 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&cpm_clk 1 22>;
191 status = "disabled";
192 };
193
194 cpm_usb3_1: usb3@510000 {
195 compatible = "marvell,armada-8k-xhci",
196 "generic-xhci";
197 reg = <0x510000 0x4000>;
198 dma-coherent;
199 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cpm_clk 1 23>;
201 status = "disabled";
202 };
203
204 cpm_sata0: sata@540000 {
205 compatible = "marvell,armada-8k-ahci",
206 "generic-ahci";
207 reg = <0x540000 0x30000>;
208 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&cpm_clk 1 15>;
210 status = "disabled";
211 };
212
213 cpm_xor0: xor@6a0000 {
214 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
215 reg = <0x6a0000 0x1000>,
216 <0x6b0000 0x1000>;
217 dma-coherent;
218 msi-parent = <&gic_v2m0>;
219 clocks = <&cpm_clk 1 8>;
220 };
221
222 cpm_xor1: xor@6c0000 {
223 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
224 reg = <0x6c0000 0x1000>,
225 <0x6d0000 0x1000>;
226 dma-coherent;
227 msi-parent = <&gic_v2m0>;
228 clocks = <&cpm_clk 1 7>;
229 };
230
231 cpm_spi0: spi@700600 {
232 compatible = "marvell,armada-380-spi";
233 reg = <0x700600 0x50>;
234 #address-cells = <0x1>;
235 #size-cells = <0x0>;
236 cell-index = <1>;
237 clocks = <&cpm_clk 1 21>;
238 status = "disabled";
239 };
240
241 cpm_spi1: spi@700680 {
242 compatible = "marvell,armada-380-spi";
243 reg = <0x700680 0x50>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 cell-index = <2>;
247 clocks = <&cpm_clk 1 21>;
248 status = "disabled";
249 };
250
251 cpm_i2c0: i2c@701000 {
252 compatible = "marvell,mv78230-i2c";
253 reg = <0x701000 0x20>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cpm_clk 1 21>;
258 status = "disabled";
259 };
260
261 cpm_i2c1: i2c@701100 {
262 compatible = "marvell,mv78230-i2c";
263 reg = <0x701100 0x20>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&cpm_clk 1 21>;
268 status = "disabled";
269 };
270
271 cpm_nand: nand@720000 {
272 /*
273 * Due to the limiation of the pin available
274 * this controller is only usable on the CPM
275 * for A7K and on the CPS for A8K.
276 */
277 compatible = "marvell,armada370-nand";
278 reg = <0x720000 0x54>;
279 #address-cells = <1>;
280 #size-cells = <1>;
281 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&cpm_clk 1 2>;
283 status = "disabled";
284 };
285
286 cpm_trng: trng@760000 {
287 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
288 reg = <0x760000 0x7d>;
289 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&cpm_clk 1 25>;
291 status = "okay";
292 };
293
294 cpm_sdhci0: sdhci@780000 {
295 compatible = "marvell,armada-cp110-sdhci";
296 reg = <0x780000 0x300>;
297 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
298 clock-names = "core";
299 clocks = <&cpm_clk 1 4>;
300 dma-coherent;
301 status = "disabled";
302 };
303
304 cpm_crypto: crypto@800000 {
305 compatible = "inside-secure,safexcel-eip197";
306 reg = <0x800000 0x200000>;
307 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
308 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
309 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
310 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
311 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
312 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-names = "mem", "ring0", "ring1",
314 "ring2", "ring3", "eip";
315 clocks = <&cpm_clk 1 26>;
316 dma-coherent;
317 };
318 };
319
320 cpm_pcie0: pcie@f2600000 {
321 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
322 reg = <0 0xf2600000 0 0x10000>,
323 <0 0xf6f00000 0 0x80000>;
324 reg-names = "ctrl", "config";
325 #address-cells = <3>;
326 #size-cells = <2>;
327 #interrupt-cells = <1>;
328 device_type = "pci";
329 dma-coherent;
330 msi-parent = <&gic_v2m0>;
331
332 bus-range = <0 0xff>;
333 ranges =
334 /* downstream I/O */
335 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
336 /* non-prefetchable memory */
337 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
338 interrupt-map-mask = <0 0 0 0>;
339 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
340 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
341 num-lanes = <1>;
342 clocks = <&cpm_clk 1 13>;
343 status = "disabled";
344 };
345
346 cpm_pcie1: pcie@f2620000 {
347 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
348 reg = <0 0xf2620000 0 0x10000>,
349 <0 0xf7f00000 0 0x80000>;
350 reg-names = "ctrl", "config";
351 #address-cells = <3>;
352 #size-cells = <2>;
353 #interrupt-cells = <1>;
354 device_type = "pci";
355 dma-coherent;
356 msi-parent = <&gic_v2m0>;
357
358 bus-range = <0 0xff>;
359 ranges =
360 /* downstream I/O */
361 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
362 /* non-prefetchable memory */
363 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
364 interrupt-map-mask = <0 0 0 0>;
365 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
366 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
367
368 num-lanes = <1>;
369 clocks = <&cpm_clk 1 11>;
370 status = "disabled";
371 };
372
373 cpm_pcie2: pcie@f2640000 {
374 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
375 reg = <0 0xf2640000 0 0x10000>,
376 <0 0xf8f00000 0 0x80000>;
377 reg-names = "ctrl", "config";
378 #address-cells = <3>;
379 #size-cells = <2>;
380 #interrupt-cells = <1>;
381 device_type = "pci";
382 dma-coherent;
383 msi-parent = <&gic_v2m0>;
384
385 bus-range = <0 0xff>;
386 ranges =
387 /* downstream I/O */
388 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
389 /* non-prefetchable memory */
390 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
391 interrupt-map-mask = <0 0 0 0>;
392 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
393 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
394
395 num-lanes = <1>;
396 clocks = <&cpm_clk 1 12>;
397 status = "disabled";
398 };
399 };
400 };
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