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mtd: nand: atmel: Relax tADL_min constraint
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / boot / dts / marvell / armada-cp110-slave.dtsi
1 /*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 /*
44 * Device Tree file for Marvell Armada CP110 Slave.
45 */
46
47 #define ICU_GRP_NSR 0x0
48
49 / {
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&cps_icu>;
55 ranges;
56
57 config-space@f4000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf4000000 0x2000000>;
62
63 cps_rtc: rtc@284000 {
64 compatible = "marvell,armada-8k-rtc";
65 reg = <0x284000 0x20>, <0x284080 0x24>;
66 reg-names = "rtc", "rtc-soc";
67 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
68 };
69
70 cps_ethernet: ethernet@0 {
71 compatible = "marvell,armada-7k-pp22";
72 reg = <0x0 0x100000>, <0x129000 0xb000>;
73 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
74 clock-names = "pp_clk", "gop_clk", "mg_clk";
75 status = "disabled";
76 dma-coherent;
77
78 cps_eth0: eth0 {
79 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
80 port-id = <0>;
81 gop-port-id = <0>;
82 status = "disabled";
83 };
84
85 cps_eth1: eth1 {
86 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
87 port-id = <1>;
88 gop-port-id = <2>;
89 status = "disabled";
90 };
91
92 cps_eth2: eth2 {
93 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
94 port-id = <2>;
95 gop-port-id = <3>;
96 status = "disabled";
97 };
98 };
99
100 cps_mdio: mdio@12a200 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "marvell,orion-mdio";
104 reg = <0x12a200 0x10>;
105 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
106 status = "disabled";
107 };
108
109 cps_xmdio: mdio@12a600 {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "marvell,xmdio";
113 reg = <0x12a600 0x10>;
114 status = "disabled";
115 };
116
117 cps_icu: interrupt-controller@1e0000 {
118 compatible = "marvell,cp110-icu";
119 reg = <0x1e0000 0x10>;
120 #interrupt-cells = <3>;
121 interrupt-controller;
122 msi-parent = <&gicp>;
123 };
124
125 cps_syscon0: system-controller@440000 {
126 compatible = "syscon", "simple-mfd";
127 reg = <0x440000 0x1000>;
128
129 cps_clk: clock {
130 compatible = "marvell,cp110-clock";
131 #clock-cells = <2>;
132 };
133
134 cps_gpio1: gpio@100 {
135 compatible = "marvell,armada-8k-gpio";
136 offset = <0x100>;
137 ngpios = <32>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 gpio-ranges = <&cps_pinctrl 0 0 32>;
141 status = "disabled";
142
143 };
144
145 cps_gpio2: gpio@140 {
146 compatible = "marvell,armada-8k-gpio";
147 offset = <0x140>;
148 ngpios = <31>;
149 gpio-controller;
150 #gpio-cells = <2>;
151 gpio-ranges = <&cps_pinctrl 0 32 31>;
152 status = "disabled";
153 };
154
155 };
156
157 cps_sata0: sata@540000 {
158 compatible = "marvell,armada-8k-ahci",
159 "generic-ahci";
160 reg = <0x540000 0x30000>;
161 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&cps_clk 1 15>;
163 status = "disabled";
164 };
165
166 cps_usb3_0: usb3@500000 {
167 compatible = "marvell,armada-8k-xhci",
168 "generic-xhci";
169 reg = <0x500000 0x4000>;
170 dma-coherent;
171 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&cps_clk 1 22>;
173 status = "disabled";
174 };
175
176 cps_usb3_1: usb3@510000 {
177 compatible = "marvell,armada-8k-xhci",
178 "generic-xhci";
179 reg = <0x510000 0x4000>;
180 dma-coherent;
181 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cps_clk 1 23>;
183 status = "disabled";
184 };
185
186 cps_xor0: xor@6a0000 {
187 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
188 reg = <0x6a0000 0x1000>,
189 <0x6b0000 0x1000>;
190 dma-coherent;
191 msi-parent = <&gic_v2m0>;
192 clocks = <&cps_clk 1 8>;
193 };
194
195 cps_xor1: xor@6c0000 {
196 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
197 reg = <0x6c0000 0x1000>,
198 <0x6d0000 0x1000>;
199 dma-coherent;
200 msi-parent = <&gic_v2m0>;
201 clocks = <&cps_clk 1 7>;
202 };
203
204 cps_spi0: spi@700600 {
205 compatible = "marvell,armada-380-spi";
206 reg = <0x700600 0x50>;
207 #address-cells = <0x1>;
208 #size-cells = <0x0>;
209 cell-index = <3>;
210 clocks = <&cps_clk 1 21>;
211 status = "disabled";
212 };
213
214 cps_spi1: spi@700680 {
215 compatible = "marvell,armada-380-spi";
216 reg = <0x700680 0x50>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 cell-index = <4>;
220 clocks = <&cps_clk 1 21>;
221 status = "disabled";
222 };
223
224 cps_i2c0: i2c@701000 {
225 compatible = "marvell,mv78230-i2c";
226 reg = <0x701000 0x20>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cps_clk 1 21>;
231 status = "disabled";
232 };
233
234 cps_i2c1: i2c@701100 {
235 compatible = "marvell,mv78230-i2c";
236 reg = <0x701100 0x20>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cps_clk 1 21>;
241 status = "disabled";
242 };
243
244 cps_trng: trng@760000 {
245 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
246 reg = <0x760000 0x7d>;
247 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cps_clk 1 25>;
249 status = "okay";
250 };
251
252 cps_crypto: crypto@800000 {
253 compatible = "inside-secure,safexcel-eip197";
254 reg = <0x800000 0x200000>;
255 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
256 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
257 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
258 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
259 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
260 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "mem", "ring0", "ring1",
262 "ring2", "ring3", "eip";
263 clocks = <&cps_clk 1 26>;
264 /*
265 * The cryptographic engine found on the cp110
266 * master is enabled by default at the SoC
267 * level. Because it is not possible as of now
268 * to enable two cryptographic engines in
269 * parallel, disable this one by default.
270 */
271 status = "disabled";
272 };
273 };
274
275 cps_pcie0: pcie@f4600000 {
276 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
277 reg = <0 0xf4600000 0 0x10000>,
278 <0 0xfaf00000 0 0x80000>;
279 reg-names = "ctrl", "config";
280 #address-cells = <3>;
281 #size-cells = <2>;
282 #interrupt-cells = <1>;
283 device_type = "pci";
284 dma-coherent;
285 msi-parent = <&gic_v2m0>;
286
287 bus-range = <0 0xff>;
288 ranges =
289 /* downstream I/O */
290 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
291 /* non-prefetchable memory */
292 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
293 interrupt-map-mask = <0 0 0 0>;
294 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
295 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
296 num-lanes = <1>;
297 clocks = <&cps_clk 1 13>;
298 status = "disabled";
299 };
300
301 cps_pcie1: pcie@f4620000 {
302 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
303 reg = <0 0xf4620000 0 0x10000>,
304 <0 0xfbf00000 0 0x80000>;
305 reg-names = "ctrl", "config";
306 #address-cells = <3>;
307 #size-cells = <2>;
308 #interrupt-cells = <1>;
309 device_type = "pci";
310 dma-coherent;
311 msi-parent = <&gic_v2m0>;
312
313 bus-range = <0 0xff>;
314 ranges =
315 /* downstream I/O */
316 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
317 /* non-prefetchable memory */
318 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
319 interrupt-map-mask = <0 0 0 0>;
320 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
321 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
322
323 num-lanes = <1>;
324 clocks = <&cps_clk 1 11>;
325 status = "disabled";
326 };
327
328 cps_pcie2: pcie@f4640000 {
329 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
330 reg = <0 0xf4640000 0 0x10000>,
331 <0 0xfcf00000 0 0x80000>;
332 reg-names = "ctrl", "config";
333 #address-cells = <3>;
334 #size-cells = <2>;
335 #interrupt-cells = <1>;
336 device_type = "pci";
337 dma-coherent;
338 msi-parent = <&gic_v2m0>;
339
340 bus-range = <0 0xff>;
341 ranges =
342 /* downstream I/O */
343 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
344 /* non-prefetchable memory */
345 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
346 interrupt-map-mask = <0 0 0 0>;
347 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
348 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
349
350 num-lanes = <1>;
351 clocks = <&cps_clk 1 12>;
352 status = "disabled";
353 };
354 };
355 };
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