2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
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14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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22 * obtaining a copy of this software and associated documentation
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44 * Device Tree file for Marvell Armada CP110 Slave.
47 #define ICU_GRP_NSR 0x0
53 compatible = "simple-bus";
54 interrupt-parent = <&cps_icu>;
57 config-space@f4000000 {
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 compatible = "marvell,armada-8k-rtc";
65 reg = <0x284000 0x20>, <0x284080 0x24>;
66 reg-names = "rtc", "rtc-soc";
67 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
70 cps_ethernet: ethernet@0 {
71 compatible = "marvell,armada-7k-pp22";
72 reg = <0x0 0x100000>, <0x129000 0xb000>;
73 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
74 clock-names = "pp_clk", "gop_clk", "mg_clk";
79 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
86 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
93 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
100 cps_mdio: mdio@12a200 {
101 #address-cells = <1>;
103 compatible = "marvell,orion-mdio";
104 reg = <0x12a200 0x10>;
105 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
109 cps_xmdio: mdio@12a600 {
110 #address-cells = <1>;
112 compatible = "marvell,xmdio";
113 reg = <0x12a600 0x10>;
117 cps_icu: interrupt-controller@1e0000 {
118 compatible = "marvell,cp110-icu";
119 reg = <0x1e0000 0x10>;
120 #interrupt-cells = <3>;
121 interrupt-controller;
122 msi-parent = <&gicp>;
125 cps_syscon0: system-controller@440000 {
126 compatible = "syscon", "simple-mfd";
127 reg = <0x440000 0x1000>;
130 compatible = "marvell,cp110-clock";
134 cps_gpio1: gpio@100 {
135 compatible = "marvell,armada-8k-gpio";
140 gpio-ranges = <&cps_pinctrl 0 0 32>;
145 cps_gpio2: gpio@140 {
146 compatible = "marvell,armada-8k-gpio";
151 gpio-ranges = <&cps_pinctrl 0 32 31>;
157 cps_sata0: sata@540000 {
158 compatible = "marvell,armada-8k-ahci",
160 reg = <0x540000 0x30000>;
161 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&cps_clk 1 15>;
166 cps_usb3_0: usb3@500000 {
167 compatible = "marvell,armada-8k-xhci",
169 reg = <0x500000 0x4000>;
171 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&cps_clk 1 22>;
176 cps_usb3_1: usb3@510000 {
177 compatible = "marvell,armada-8k-xhci",
179 reg = <0x510000 0x4000>;
181 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cps_clk 1 23>;
186 cps_xor0: xor@6a0000 {
187 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
188 reg = <0x6a0000 0x1000>,
191 msi-parent = <&gic_v2m0>;
192 clocks = <&cps_clk 1 8>;
195 cps_xor1: xor@6c0000 {
196 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
197 reg = <0x6c0000 0x1000>,
200 msi-parent = <&gic_v2m0>;
201 clocks = <&cps_clk 1 7>;
204 cps_spi0: spi@700600 {
205 compatible = "marvell,armada-380-spi";
206 reg = <0x700600 0x50>;
207 #address-cells = <0x1>;
210 clocks = <&cps_clk 1 21>;
214 cps_spi1: spi@700680 {
215 compatible = "marvell,armada-380-spi";
216 reg = <0x700680 0x50>;
217 #address-cells = <1>;
220 clocks = <&cps_clk 1 21>;
224 cps_i2c0: i2c@701000 {
225 compatible = "marvell,mv78230-i2c";
226 reg = <0x701000 0x20>;
227 #address-cells = <1>;
229 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cps_clk 1 21>;
234 cps_i2c1: i2c@701100 {
235 compatible = "marvell,mv78230-i2c";
236 reg = <0x701100 0x20>;
237 #address-cells = <1>;
239 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cps_clk 1 21>;
244 cps_trng: trng@760000 {
245 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
246 reg = <0x760000 0x7d>;
247 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cps_clk 1 25>;
252 cps_crypto: crypto@800000 {
253 compatible = "inside-secure,safexcel-eip197";
254 reg = <0x800000 0x200000>;
255 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
256 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
257 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
258 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
259 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
260 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "mem", "ring0", "ring1",
262 "ring2", "ring3", "eip";
263 clocks = <&cps_clk 1 26>;
265 * The cryptographic engine found on the cp110
266 * master is enabled by default at the SoC
267 * level. Because it is not possible as of now
268 * to enable two cryptographic engines in
269 * parallel, disable this one by default.
275 cps_pcie0: pcie@f4600000 {
276 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
277 reg = <0 0xf4600000 0 0x10000>,
278 <0 0xfaf00000 0 0x80000>;
279 reg-names = "ctrl", "config";
280 #address-cells = <3>;
282 #interrupt-cells = <1>;
285 msi-parent = <&gic_v2m0>;
287 bus-range = <0 0xff>;
290 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
291 /* non-prefetchable memory */
292 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
293 interrupt-map-mask = <0 0 0 0>;
294 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
295 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cps_clk 1 13>;
301 cps_pcie1: pcie@f4620000 {
302 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
303 reg = <0 0xf4620000 0 0x10000>,
304 <0 0xfbf00000 0 0x80000>;
305 reg-names = "ctrl", "config";
306 #address-cells = <3>;
308 #interrupt-cells = <1>;
311 msi-parent = <&gic_v2m0>;
313 bus-range = <0 0xff>;
316 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
317 /* non-prefetchable memory */
318 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
319 interrupt-map-mask = <0 0 0 0>;
320 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
321 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&cps_clk 1 11>;
328 cps_pcie2: pcie@f4640000 {
329 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
330 reg = <0 0xf4640000 0 0x10000>,
331 <0 0xfcf00000 0 0x80000>;
332 reg-names = "ctrl", "config";
333 #address-cells = <3>;
335 #interrupt-cells = <1>;
338 msi-parent = <&gic_v2m0>;
340 bus-range = <0 0xff>;
343 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
344 /* non-prefetchable memory */
345 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
346 interrupt-map-mask = <0 0 0 0>;
347 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
348 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&cps_clk 1 12>;