arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include "mt8173-pinfunc.h"
  22
  23 / {
  24         compatible = "mediatek,mt8173";
  25         interrupt-parent = <&sysirq>;
  26         #address-cells = <2>;
  27         #size-cells = <2>;
  28
  29         aliases {
  30                 ovl0 = &ovl0;
  31                 ovl1 = &ovl1;
  32                 rdma0 = &rdma0;
  33                 rdma1 = &rdma1;
  34                 rdma2 = &rdma2;
  35                 wdma0 = &wdma0;
  36                 wdma1 = &wdma1;
  37                 color0 = &color0;
  38                 color1 = &color1;
  39                 split0 = &split0;
  40                 split1 = &split1;
  41                 dpi0 = &dpi0;
  42                 dsi0 = &dsi0;
  43                 dsi1 = &dsi1;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu-map {
  51                         cluster0 {
  52                                 core0 {
  53                                         cpu = <&cpu0>;
  54                                 };
  55                                 core1 {
  56                                         cpu = <&cpu1>;
  57                                 };
  58                         };
  59
  60                         cluster1 {
  61                                 core0 {
  62                                         cpu = <&cpu2>;
  63                                 };
  64                                 core1 {
  65                                         cpu = <&cpu3>;
  66                                 };
  67                         };
  68                 };
  69
  70                 cpu0: cpu@0 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53";
  73                         reg = <0x000>;
  74                         enable-method = "psci";
  75                         cpu-idle-states = <&CPU_SLEEP_0>;
  76                 };
  77
  78                 cpu1: cpu@1 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53";
  81                         reg = <0x001>;
  82                         enable-method = "psci";
  83                         cpu-idle-states = <&CPU_SLEEP_0>;
  84                 };
  85
  86                 cpu2: cpu@100 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a57";
  89                         reg = <0x100>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93
  94                 cpu3: cpu@101 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a57";
  97                         reg = <0x101>;
  98                         enable-method = "psci";
  99                         cpu-idle-states = <&CPU_SLEEP_0>;
 100                 };
 101
 102                 idle-states {
 103                         entry-method = "psci";
 104
 105                         CPU_SLEEP_0: cpu-sleep-0 {
 106                                 compatible = "arm,idle-state";
 107                                 local-timer-stop;
 108                                 entry-latency-us = <639>;
 109                                 exit-latency-us = <680>;
 110                                 min-residency-us = <1088>;
 111                                 arm,psci-suspend-param = <0x0010000>;
 112                         };
 113                 };
 114         };
 115
 116         psci {
 117                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 118                 method = "smc";
 119                 cpu_suspend   = <0x84000001>;
 120                 cpu_off       = <0x84000002>;
 121                 cpu_on        = <0x84000003>;
 122         };
 123
 124         clk26m: oscillator@0 {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <26000000>;
 128                 clock-output-names = "clk26m";
 129         };
 130
 131         clk32k: oscillator@1 {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency = <32000>;
 135                 clock-output-names = "clk32k";
 136         };
 137
 138         cpum_ck: oscillator@2 {
 139                 compatible = "fixed-clock";
 140                 #clock-cells = <0>;
 141                 clock-frequency = <0>;
 142                 clock-output-names = "cpum_ck";
 143         };
 144
 145         thermal-zones {
 146                 cpu_thermal: cpu_thermal {
 147                         polling-delay-passive = <1000>; /* milliseconds */
 148                         polling-delay = <1000>; /* milliseconds */
 149
 150                         thermal-sensors = <&thermal>;
 151                         sustainable-power = <1500>; /* milliwatts */
 152
 153                         trips {
 154                                 threshold: trip-point@0 {
 155                                         temperature = <68000>;
 156                                         hysteresis = <2000>;
 157                                         type = "passive";
 158                                 };
 159
 160                                 target: trip-point@1 {
 161                                         temperature = <85000>;
 162                                         hysteresis = <2000>;
 163                                         type = "passive";
 164                                 };
 165
 166                                 cpu_crit: cpu_crit@0 {
 167                                         temperature = <115000>;
 168                                         hysteresis = <2000>;
 169                                         type = "critical";
 170                                 };
 171                         };
 172
 173                         cooling-maps {
 174                                 map@0 {
 175                                         trip = <&target>;
 176                                         cooling-device = <&cpu0 0 0>;
 177                                         contribution = <1024>;
 178                                 };
 179                                 map@1 {
 180                                         trip = <&target>;
 181                                         cooling-device = <&cpu2 0 0>;
 182                                         contribution = <2048>;
 183                                 };
 184                         };
 185                 };
 186         };
 187
 188         reserved-memory {
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 ranges;
 192                 vpu_dma_reserved: vpu_dma_mem_region {
 193                         compatible = "shared-dma-pool";
 194                         reg = <0 0xb7000000 0 0x500000>;
 195                         alignment = <0x1000>;
 196                         no-map;
 197                 };
 198         };
 199
 200         timer {
 201                 compatible = "arm,armv8-timer";
 202                 interrupt-parent = <&gic>;
 203                 interrupts = <GIC_PPI 13
 204                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 205                              <GIC_PPI 14
 206                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 207                              <GIC_PPI 11
 208                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <GIC_PPI 10
 210                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 211         };
 212
 213         soc {
 214                 #address-cells = <2>;
 215                 #size-cells = <2>;
 216                 compatible = "simple-bus";
 217                 ranges;
 218
 219                 topckgen: clock-controller@10000000 {
 220                         compatible = "mediatek,mt8173-topckgen";
 221                         reg = <0 0x10000000 0 0x1000>;
 222                         #clock-cells = <1>;
 223                 };
 224
 225                 infracfg: power-controller@10001000 {
 226                         compatible = "mediatek,mt8173-infracfg", "syscon";
 227                         reg = <0 0x10001000 0 0x1000>;
 228                         #clock-cells = <1>;
 229                         #reset-cells = <1>;
 230                 };
 231
 232                 pericfg: power-controller@10003000 {
 233                         compatible = "mediatek,mt8173-pericfg", "syscon";
 234                         reg = <0 0x10003000 0 0x1000>;
 235                         #clock-cells = <1>;
 236                         #reset-cells = <1>;
 237                 };
 238
 239                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 240                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 241                         reg = <0 0x10005000 0 0x1000>;
 242                 };
 243
 244                 pio: pinctrl@0x10005000 {
 245                         compatible = "mediatek,mt8173-pinctrl";
 246                         reg = <0 0x1000b000 0 0x1000>;
 247                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 248                         pins-are-numbered;
 249                         gpio-controller;
 250                         #gpio-cells = <2>;
 251                         interrupt-controller;
 252                         #interrupt-cells = <2>;
 253                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 256
 257                         hdmi_pin: xxx {
 258
 259                                 /*hdmi htplg pin*/
 260                                 pins1 {
 261                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 262                                         input-enable;
 263                                         bias-pull-down;
 264                                 };
 265                         };
 266
 267                         i2c0_pins_a: i2c0 {
 268                                 pins1 {
 269                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 270                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 271                                         bias-disable;
 272                                 };
 273                         };
 274
 275                         i2c1_pins_a: i2c1 {
 276                                 pins1 {
 277                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 278                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 279                                         bias-disable;
 280                                 };
 281                         };
 282
 283                         i2c2_pins_a: i2c2 {
 284                                 pins1 {
 285                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 286                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 287                                         bias-disable;
 288                                 };
 289                         };
 290
 291                         i2c3_pins_a: i2c3 {
 292                                 pins1 {
 293                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 294                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 295                                         bias-disable;
 296                                 };
 297                         };
 298
 299                         i2c4_pins_a: i2c4 {
 300                                 pins1 {
 301                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 302                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 303                                         bias-disable;
 304                                 };
 305                         };
 306
 307                         i2c6_pins_a: i2c6 {
 308                                 pins1 {
 309                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 310                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 311                                         bias-disable;
 312                                 };
 313                         };
 314                 };
 315
 316                 scpsys: scpsys@10006000 {
 317                         compatible = "mediatek,mt8173-scpsys";
 318                         #power-domain-cells = <1>;
 319                         reg = <0 0x10006000 0 0x1000>;
 320                         clocks = <&clk26m>,
 321                                  <&topckgen CLK_TOP_MM_SEL>,
 322                                  <&topckgen CLK_TOP_VENC_SEL>,
 323                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 324                         clock-names = "mfg", "mm", "venc", "venc_lt";
 325                         infracfg = <&infracfg>;
 326                 };
 327
 328                 watchdog: watchdog@10007000 {
 329                         compatible = "mediatek,mt8173-wdt",
 330                                      "mediatek,mt6589-wdt";
 331                         reg = <0 0x10007000 0 0x100>;
 332                 };
 333
 334                 timer: timer@10008000 {
 335                         compatible = "mediatek,mt8173-timer",
 336                                      "mediatek,mt6577-timer";
 337                         reg = <0 0x10008000 0 0x1000>;
 338                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 339                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 340                                  <&topckgen CLK_TOP_RTC_SEL>;
 341                 };
 342
 343                 pwrap: pwrap@1000d000 {
 344                         compatible = "mediatek,mt8173-pwrap";
 345                         reg = <0 0x1000d000 0 0x1000>;
 346                         reg-names = "pwrap";
 347                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 348                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 349                         reset-names = "pwrap";
 350                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 351                         clock-names = "spi", "wrap";
 352                 };
 353
 354                 cec: cec@10013000 {
 355                         compatible = "mediatek,mt8173-cec";
 356                         reg = <0 0x10013000 0 0xbc>;
 357                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 358                         clocks = <&infracfg CLK_INFRA_CEC>;
 359                         status = "disabled";
 360                 };
 361
 362                 vpu: vpu@10020000 {
 363                         compatible = "mediatek,mt8173-vpu";
 364                         reg = <0 0x10020000 0 0x30000>,
 365                               <0 0x10050000 0 0x100>;
 366                         reg-names = "tcm", "cfg_reg";
 367                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 369                         clock-names = "main";
 370                         memory-region = <&vpu_dma_reserved>;
 371                 };
 372
 373                 sysirq: intpol-controller@10200620 {
 374                         compatible = "mediatek,mt8173-sysirq",
 375                                      "mediatek,mt6577-sysirq";
 376                         interrupt-controller;
 377                         #interrupt-cells = <3>;
 378                         interrupt-parent = <&gic>;
 379                         reg = <0 0x10200620 0 0x20>;
 380                 };
 381
 382                 iommu: iommu@10205000 {
 383                         compatible = "mediatek,mt8173-m4u";
 384                         reg = <0 0x10205000 0 0x1000>;
 385                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 386                         clocks = <&infracfg CLK_INFRA_M4U>;
 387                         clock-names = "bclk";
 388                         mediatek,larbs = <&larb0 &larb1 &larb2
 389                                           &larb3 &larb4 &larb5>;
 390                         #iommu-cells = <1>;
 391                 };
 392
 393                 efuse: efuse@10206000 {
 394                         compatible = "mediatek,mt8173-efuse";
 395                         reg = <0 0x10206000 0 0x1000>;
 396                 };
 397
 398                 apmixedsys: clock-controller@10209000 {
 399                         compatible = "mediatek,mt8173-apmixedsys";
 400                         reg = <0 0x10209000 0 0x1000>;
 401                         #clock-cells = <1>;
 402                 };
 403
 404                 hdmi_phy: hdmi-phy@10209100 {
 405                         compatible = "mediatek,mt8173-hdmi-phy";
 406                         reg = <0 0x10209100 0 0x24>;
 407                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 408                         clock-names = "pll_ref";
 409                         clock-output-names = "hdmitx_dig_cts";
 410                         mediatek,ibias = <0xa>;
 411                         mediatek,ibias_up = <0x1c>;
 412                         #clock-cells = <0>;
 413                         #phy-cells = <0>;
 414                         status = "disabled";
 415                 };
 416
 417                 mipi_tx0: mipi-dphy@10215000 {
 418                         compatible = "mediatek,mt8173-mipi-tx";
 419                         reg = <0 0x10215000 0 0x1000>;
 420                         clocks = <&clk26m>;
 421                         clock-output-names = "mipi_tx0_pll";
 422                         #clock-cells = <0>;
 423                         #phy-cells = <0>;
 424                         status = "disabled";
 425                 };
 426
 427                 mipi_tx1: mipi-dphy@10216000 {
 428                         compatible = "mediatek,mt8173-mipi-tx";
 429                         reg = <0 0x10216000 0 0x1000>;
 430                         clocks = <&clk26m>;
 431                         clock-output-names = "mipi_tx1_pll";
 432                         #clock-cells = <0>;
 433                         #phy-cells = <0>;
 434                         status = "disabled";
 435                 };
 436
 437                 gic: interrupt-controller@10220000 {
 438                         compatible = "arm,gic-400";
 439                         #interrupt-cells = <3>;
 440                         interrupt-parent = <&gic>;
 441                         interrupt-controller;
 442                         reg = <0 0x10221000 0 0x1000>,
 443                               <0 0x10222000 0 0x2000>,
 444                               <0 0x10224000 0 0x2000>,
 445                               <0 0x10226000 0 0x2000>;
 446                         interrupts = <GIC_PPI 9
 447                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 448                 };
 449
 450                 auxadc: auxadc@11001000 {
 451                         compatible = "mediatek,mt8173-auxadc";
 452                         reg = <0 0x11001000 0 0x1000>;
 453                         clocks = <&pericfg CLK_PERI_AUXADC>;
 454                         clock-names = "main";
 455                         #io-channel-cells = <1>;
 456                 };
 457
 458                 uart0: serial@11002000 {
 459                         compatible = "mediatek,mt8173-uart",
 460                                      "mediatek,mt6577-uart";
 461                         reg = <0 0x11002000 0 0x400>;
 462                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 463                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 464                         clock-names = "baud", "bus";
 465                         status = "disabled";
 466                 };
 467
 468                 uart1: serial@11003000 {
 469                         compatible = "mediatek,mt8173-uart",
 470                                      "mediatek,mt6577-uart";
 471                         reg = <0 0x11003000 0 0x400>;
 472                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 473                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 474                         clock-names = "baud", "bus";
 475                         status = "disabled";
 476                 };
 477
 478                 uart2: serial@11004000 {
 479                         compatible = "mediatek,mt8173-uart",
 480                                      "mediatek,mt6577-uart";
 481                         reg = <0 0x11004000 0 0x400>;
 482                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 483                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 484                         clock-names = "baud", "bus";
 485                         status = "disabled";
 486                 };
 487
 488                 uart3: serial@11005000 {
 489                         compatible = "mediatek,mt8173-uart",
 490                                      "mediatek,mt6577-uart";
 491                         reg = <0 0x11005000 0 0x400>;
 492                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 493                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 494                         clock-names = "baud", "bus";
 495                         status = "disabled";
 496                 };
 497
 498                 i2c0: i2c@11007000 {
 499                         compatible = "mediatek,mt8173-i2c";
 500                         reg = <0 0x11007000 0 0x70>,
 501                               <0 0x11000100 0 0x80>;
 502                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 503                         clock-div = <16>;
 504                         clocks = <&pericfg CLK_PERI_I2C0>,
 505                                  <&pericfg CLK_PERI_AP_DMA>;
 506                         clock-names = "main", "dma";
 507                         pinctrl-names = "default";
 508                         pinctrl-0 = <&i2c0_pins_a>;
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         status = "disabled";
 512                 };
 513
 514                 i2c1: i2c@11008000 {
 515                         compatible = "mediatek,mt8173-i2c";
 516                         reg = <0 0x11008000 0 0x70>,
 517                               <0 0x11000180 0 0x80>;
 518                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 519                         clock-div = <16>;
 520                         clocks = <&pericfg CLK_PERI_I2C1>,
 521                                  <&pericfg CLK_PERI_AP_DMA>;
 522                         clock-names = "main", "dma";
 523                         pinctrl-names = "default";
 524                         pinctrl-0 = <&i2c1_pins_a>;
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         status = "disabled";
 528                 };
 529
 530                 i2c2: i2c@11009000 {
 531                         compatible = "mediatek,mt8173-i2c";
 532                         reg = <0 0x11009000 0 0x70>,
 533                               <0 0x11000200 0 0x80>;
 534                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 535                         clock-div = <16>;
 536                         clocks = <&pericfg CLK_PERI_I2C2>,
 537                                  <&pericfg CLK_PERI_AP_DMA>;
 538                         clock-names = "main", "dma";
 539                         pinctrl-names = "default";
 540                         pinctrl-0 = <&i2c2_pins_a>;
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         status = "disabled";
 544                 };
 545
 546                 spi: spi@1100a000 {
 547                         compatible = "mediatek,mt8173-spi";
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                         reg = <0 0x1100a000 0 0x1000>;
 551                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 552                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 553                                  <&topckgen CLK_TOP_SPI_SEL>,
 554                                  <&pericfg CLK_PERI_SPI0>;
 555                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 556                         status = "disabled";
 557                 };
 558
 559                 thermal: thermal@1100b000 {
 560                         #thermal-sensor-cells = <0>;
 561                         compatible = "mediatek,mt8173-thermal";
 562                         reg = <0 0x1100b000 0 0x1000>;
 563                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 564                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 565                         clock-names = "therm", "auxadc";
 566                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 567                         mediatek,auxadc = <&auxadc>;
 568                         mediatek,apmixedsys = <&apmixedsys>;
 569                 };
 570
 571                 nor_flash: spi@1100d000 {
 572                         compatible = "mediatek,mt8173-nor";
 573                         reg = <0 0x1100d000 0 0xe0>;
 574                         clocks = <&pericfg CLK_PERI_SPI>,
 575                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 576                         clock-names = "spi", "sf";
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                         status = "disabled";
 580                 };
 581
 582                 i2c3: i2c@11010000 {
 583                         compatible = "mediatek,mt8173-i2c";
 584                         reg = <0 0x11010000 0 0x70>,
 585                               <0 0x11000280 0 0x80>;
 586                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 587                         clock-div = <16>;
 588                         clocks = <&pericfg CLK_PERI_I2C3>,
 589                                  <&pericfg CLK_PERI_AP_DMA>;
 590                         clock-names = "main", "dma";
 591                         pinctrl-names = "default";
 592                         pinctrl-0 = <&i2c3_pins_a>;
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         status = "disabled";
 596                 };
 597
 598                 i2c4: i2c@11011000 {
 599                         compatible = "mediatek,mt8173-i2c";
 600                         reg = <0 0x11011000 0 0x70>,
 601                               <0 0x11000300 0 0x80>;
 602                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 603                         clock-div = <16>;
 604                         clocks = <&pericfg CLK_PERI_I2C4>,
 605                                  <&pericfg CLK_PERI_AP_DMA>;
 606                         clock-names = "main", "dma";
 607                         pinctrl-names = "default";
 608                         pinctrl-0 = <&i2c4_pins_a>;
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611                         status = "disabled";
 612                 };
 613
 614                 hdmiddc0: i2c@11012000 {
 615                         compatible = "mediatek,mt8173-hdmi-ddc";
 616                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 617                         reg = <0 0x11012000 0 0x1C>;
 618                         clocks = <&pericfg CLK_PERI_I2C5>;
 619                         clock-names = "ddc-i2c";
 620                 };
 621
 622                 i2c6: i2c@11013000 {
 623                         compatible = "mediatek,mt8173-i2c";
 624                         reg = <0 0x11013000 0 0x70>,
 625                               <0 0x11000080 0 0x80>;
 626                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 627                         clock-div = <16>;
 628                         clocks = <&pericfg CLK_PERI_I2C6>,
 629                                  <&pericfg CLK_PERI_AP_DMA>;
 630                         clock-names = "main", "dma";
 631                         pinctrl-names = "default";
 632                         pinctrl-0 = <&i2c6_pins_a>;
 633                         #address-cells = <1>;
 634                         #size-cells = <0>;
 635                         status = "disabled";
 636                 };
 637
 638                 afe: audio-controller@11220000  {
 639                         compatible = "mediatek,mt8173-afe-pcm";
 640                         reg = <0 0x11220000 0 0x1000>;
 641                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 642                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 643                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 644                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 645                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 646                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 647                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 648                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 649                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 650                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 651                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 652                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 653                         clock-names = "infra_sys_audio_clk",
 654                                       "top_pdn_audio",
 655                                       "top_pdn_aud_intbus",
 656                                       "bck0",
 657                                       "bck1",
 658                                       "i2s0_m",
 659                                       "i2s1_m",
 660                                       "i2s2_m",
 661                                       "i2s3_m",
 662                                       "i2s3_b";
 663                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 664                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 665                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 666                                                  <&topckgen CLK_TOP_APLL2>;
 667                 };
 668
 669                 mmc0: mmc@11230000 {
 670                         compatible = "mediatek,mt8173-mmc",
 671                                      "mediatek,mt8135-mmc";
 672                         reg = <0 0x11230000 0 0x1000>;
 673                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 674                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 675                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 676                         clock-names = "source", "hclk";
 677                         status = "disabled";
 678                 };
 679
 680                 mmc1: mmc@11240000 {
 681                         compatible = "mediatek,mt8173-mmc",
 682                                      "mediatek,mt8135-mmc";
 683                         reg = <0 0x11240000 0 0x1000>;
 684                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 685                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 686                                  <&topckgen CLK_TOP_AXI_SEL>;
 687                         clock-names = "source", "hclk";
 688                         status = "disabled";
 689                 };
 690
 691                 mmc2: mmc@11250000 {
 692                         compatible = "mediatek,mt8173-mmc",
 693                                      "mediatek,mt8135-mmc";
 694                         reg = <0 0x11250000 0 0x1000>;
 695                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 696                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 697                                  <&topckgen CLK_TOP_AXI_SEL>;
 698                         clock-names = "source", "hclk";
 699                         status = "disabled";
 700                 };
 701
 702                 mmc3: mmc@11260000 {
 703                         compatible = "mediatek,mt8173-mmc",
 704                                      "mediatek,mt8135-mmc";
 705                         reg = <0 0x11260000 0 0x1000>;
 706                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 707                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 708                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 709                         clock-names = "source", "hclk";
 710                         status = "disabled";
 711                 };
 712
 713                 ssusb: usb@11271000 {
 714                         compatible = "mediatek,mt8173-mtu3";
 715                         reg = <0 0x11271000 0 0x3000>,
 716                               <0 0x11280700 0 0x0100>;
 717                         reg-names = "mac", "ippc";
 718                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 719                         phys = <&phy_port0 PHY_TYPE_USB3>,
 720                                <&phy_port1 PHY_TYPE_USB2>;
 721                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 722                         clocks = <&topckgen CLK_TOP_USB30_SEL>,
 723                                  <&pericfg CLK_PERI_USB0>,
 724                                  <&pericfg CLK_PERI_USB1>;
 725                         clock-names = "sys_ck",
 726                                       "wakeup_deb_p0",
 727                                       "wakeup_deb_p1";
 728                         mediatek,syscon-wakeup = <&pericfg>;
 729                         #address-cells = <2>;
 730                         #size-cells = <2>;
 731                         ranges;
 732                         status = "disabled";
 733
 734                         usb_host: xhci@11270000 {
 735                                 compatible = "mediatek,mt8173-xhci";
 736                                 reg = <0 0x11270000 0 0x1000>;
 737                                 reg-names = "mac";
 738                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 739                                 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 740                                 clocks = <&topckgen CLK_TOP_USB30_SEL>;
 741                                 clock-names = "sys_ck";
 742                                 status = "disabled";
 743                         };
 744                 };
 745
 746                 u3phy: usb-phy@11290000 {
 747                         compatible = "mediatek,mt8173-u3phy";
 748                         reg = <0 0x11290000 0 0x800>;
 749                         clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 750                         clock-names = "u3phya_ref";
 751                         #address-cells = <2>;
 752                         #size-cells = <2>;
 753                         ranges;
 754                         status = "okay";
 755
 756                         phy_port0: port@11290800 {
 757                                 reg = <0 0x11290800 0 0x800>;
 758                                 #phy-cells = <1>;
 759                                 status = "okay";
 760                         };
 761
 762                         phy_port1: port@11291000 {
 763                                 reg = <0 0x11291000 0 0x800>;
 764                                 #phy-cells = <1>;
 765                                 status = "okay";
 766                         };
 767                 };
 768
 769                 mmsys: clock-controller@14000000 {
 770                         compatible = "mediatek,mt8173-mmsys", "syscon";
 771                         reg = <0 0x14000000 0 0x1000>;
 772                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 773                         #clock-cells = <1>;
 774                 };
 775
 776                 ovl0: ovl@1400c000 {
 777                         compatible = "mediatek,mt8173-disp-ovl";
 778                         reg = <0 0x1400c000 0 0x1000>;
 779                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
 780                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 781                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
 782                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
 783                         mediatek,larb = <&larb0>;
 784                 };
 785
 786                 ovl1: ovl@1400d000 {
 787                         compatible = "mediatek,mt8173-disp-ovl";
 788                         reg = <0 0x1400d000 0 0x1000>;
 789                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
 790                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 791                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
 792                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
 793                         mediatek,larb = <&larb4>;
 794                 };
 795
 796                 rdma0: rdma@1400e000 {
 797                         compatible = "mediatek,mt8173-disp-rdma";
 798                         reg = <0 0x1400e000 0 0x1000>;
 799                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
 800                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 801                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 802                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
 803                         mediatek,larb = <&larb0>;
 804                 };
 805
 806                 rdma1: rdma@1400f000 {
 807                         compatible = "mediatek,mt8173-disp-rdma";
 808                         reg = <0 0x1400f000 0 0x1000>;
 809                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
 810                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 811                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 812                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
 813                         mediatek,larb = <&larb4>;
 814                 };
 815
 816                 rdma2: rdma@14010000 {
 817                         compatible = "mediatek,mt8173-disp-rdma";
 818                         reg = <0 0x14010000 0 0x1000>;
 819                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
 820                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 821                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
 822                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
 823                         mediatek,larb = <&larb4>;
 824                 };
 825
 826                 wdma0: wdma@14011000 {
 827                         compatible = "mediatek,mt8173-disp-wdma";
 828                         reg = <0 0x14011000 0 0x1000>;
 829                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
 830                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 831                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
 832                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
 833                         mediatek,larb = <&larb0>;
 834                 };
 835
 836                 wdma1: wdma@14012000 {
 837                         compatible = "mediatek,mt8173-disp-wdma";
 838                         reg = <0 0x14012000 0 0x1000>;
 839                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
 840                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 841                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
 842                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
 843                         mediatek,larb = <&larb4>;
 844                 };
 845
 846                 color0: color@14013000 {
 847                         compatible = "mediatek,mt8173-disp-color";
 848                         reg = <0 0x14013000 0 0x1000>;
 849                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
 850                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 851                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
 852                 };
 853
 854                 color1: color@14014000 {
 855                         compatible = "mediatek,mt8173-disp-color";
 856                         reg = <0 0x14014000 0 0x1000>;
 857                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
 858                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 859                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
 860                 };
 861
 862                 aal@14015000 {
 863                         compatible = "mediatek,mt8173-disp-aal";
 864                         reg = <0 0x14015000 0 0x1000>;
 865                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
 866                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 867                         clocks = <&mmsys CLK_MM_DISP_AAL>;
 868                 };
 869
 870                 gamma@14016000 {
 871                         compatible = "mediatek,mt8173-disp-gamma";
 872                         reg = <0 0x14016000 0 0x1000>;
 873                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
 874                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 875                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
 876                 };
 877
 878                 merge@14017000 {
 879                         compatible = "mediatek,mt8173-disp-merge";
 880                         reg = <0 0x14017000 0 0x1000>;
 881                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 882                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
 883                 };
 884
 885                 split0: split@14018000 {
 886                         compatible = "mediatek,mt8173-disp-split";
 887                         reg = <0 0x14018000 0 0x1000>;
 888                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 889                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
 890                 };
 891
 892                 split1: split@14019000 {
 893                         compatible = "mediatek,mt8173-disp-split";
 894                         reg = <0 0x14019000 0 0x1000>;
 895                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 896                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
 897                 };
 898
 899                 ufoe@1401a000 {
 900                         compatible = "mediatek,mt8173-disp-ufoe";
 901                         reg = <0 0x1401a000 0 0x1000>;
 902                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
 903                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 904                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
 905                 };
 906
 907                 dsi0: dsi@1401b000 {
 908                         compatible = "mediatek,mt8173-dsi";
 909                         reg = <0 0x1401b000 0 0x1000>;
 910                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
 911                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 912                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
 913                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
 914                                  <&mipi_tx0>;
 915                         clock-names = "engine", "digital", "hs";
 916                         phys = <&mipi_tx0>;
 917                         phy-names = "dphy";
 918                         status = "disabled";
 919                 };
 920
 921                 dsi1: dsi@1401c000 {
 922                         compatible = "mediatek,mt8173-dsi";
 923                         reg = <0 0x1401c000 0 0x1000>;
 924                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
 925                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 926                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
 927                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
 928                                  <&mipi_tx1>;
 929                         clock-names = "engine", "digital", "hs";
 930                         phy = <&mipi_tx1>;
 931                         phy-names = "dphy";
 932                         status = "disabled";
 933                 };
 934
 935                 dpi0: dpi@1401d000 {
 936                         compatible = "mediatek,mt8173-dpi";
 937                         reg = <0 0x1401d000 0 0x1000>;
 938                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
 939                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 940                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
 941                                  <&mmsys CLK_MM_DPI_ENGINE>,
 942                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
 943                         clock-names = "pixel", "engine", "pll";
 944                         status = "disabled";
 945
 946                         port {
 947                                 dpi0_out: endpoint {
 948                                         remote-endpoint = <&hdmi0_in>;
 949                                 };
 950                         };
 951                 };
 952
 953                 pwm0: pwm@1401e000 {
 954                         compatible = "mediatek,mt8173-disp-pwm",
 955                                      "mediatek,mt6595-disp-pwm";
 956                         reg = <0 0x1401e000 0 0x1000>;
 957                         #pwm-cells = <2>;
 958                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
 959                                  <&mmsys CLK_MM_DISP_PWM0MM>;
 960                         clock-names = "main", "mm";
 961                         status = "disabled";
 962                 };
 963
 964                 pwm1: pwm@1401f000 {
 965                         compatible = "mediatek,mt8173-disp-pwm",
 966                                      "mediatek,mt6595-disp-pwm";
 967                         reg = <0 0x1401f000 0 0x1000>;
 968                         #pwm-cells = <2>;
 969                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
 970                                  <&mmsys CLK_MM_DISP_PWM1MM>;
 971                         clock-names = "main", "mm";
 972                         status = "disabled";
 973                 };
 974
 975                 mutex: mutex@14020000 {
 976                         compatible = "mediatek,mt8173-disp-mutex";
 977                         reg = <0 0x14020000 0 0x1000>;
 978                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
 979                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 980                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
 981                 };
 982
 983                 larb0: larb@14021000 {
 984                         compatible = "mediatek,mt8173-smi-larb";
 985                         reg = <0 0x14021000 0 0x1000>;
 986                         mediatek,smi = <&smi_common>;
 987                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 988                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
 989                                  <&mmsys CLK_MM_SMI_LARB0>;
 990                         clock-names = "apb", "smi";
 991                 };
 992
 993                 smi_common: smi@14022000 {
 994                         compatible = "mediatek,mt8173-smi-common";
 995                         reg = <0 0x14022000 0 0x1000>;
 996                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 997                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
 998                                  <&mmsys CLK_MM_SMI_COMMON>;
 999                         clock-names = "apb", "smi";
1000                 };
1001
1002                 od@14023000 {
1003                         compatible = "mediatek,mt8173-disp-od";
1004                         reg = <0 0x14023000 0 0x1000>;
1005                         clocks = <&mmsys CLK_MM_DISP_OD>;
1006                 };
1007
1008                 hdmi0: hdmi@14025000 {
1009                         compatible = "mediatek,mt8173-hdmi";
1010                         reg = <0 0x14025000 0 0x400>;
1011                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1012                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1013                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1014                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1015                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1016                         clock-names = "pixel", "pll", "bclk", "spdif";
1017                         pinctrl-names = "default";
1018                         pinctrl-0 = <&hdmi_pin>;
1019                         phys = <&hdmi_phy>;
1020                         phy-names = "hdmi";
1021                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1022                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1023                         assigned-clock-parents = <&hdmi_phy>;
1024                         status = "disabled";
1025
1026                         ports {
1027                                 #address-cells = <1>;
1028                                 #size-cells = <0>;
1029
1030                                 port@0 {
1031                                         reg = <0>;
1032
1033                                         hdmi0_in: endpoint {
1034                                                 remote-endpoint = <&dpi0_out>;
1035                                         };
1036                                 };
1037                         };
1038                 };
1039
1040                 larb4: larb@14027000 {
1041                         compatible = "mediatek,mt8173-smi-larb";
1042                         reg = <0 0x14027000 0 0x1000>;
1043                         mediatek,smi = <&smi_common>;
1044                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1045                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1046                                  <&mmsys CLK_MM_SMI_LARB4>;
1047                         clock-names = "apb", "smi";
1048                 };
1049
1050                 imgsys: clock-controller@15000000 {
1051                         compatible = "mediatek,mt8173-imgsys", "syscon";
1052                         reg = <0 0x15000000 0 0x1000>;
1053                         #clock-cells = <1>;
1054                 };
1055
1056                 larb2: larb@15001000 {
1057                         compatible = "mediatek,mt8173-smi-larb";
1058                         reg = <0 0x15001000 0 0x1000>;
1059                         mediatek,smi = <&smi_common>;
1060                         power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1061                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1062                                  <&imgsys CLK_IMG_LARB2_SMI>;
1063                         clock-names = "apb", "smi";
1064                 };
1065
1066                 vdecsys: clock-controller@16000000 {
1067                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1068                         reg = <0 0x16000000 0 0x1000>;
1069                         #clock-cells = <1>;
1070                 };
1071
1072                 larb1: larb@16010000 {
1073                         compatible = "mediatek,mt8173-smi-larb";
1074                         reg = <0 0x16010000 0 0x1000>;
1075                         mediatek,smi = <&smi_common>;
1076                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1077                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1078                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1079                         clock-names = "apb", "smi";
1080                 };
1081
1082                 vencsys: clock-controller@18000000 {
1083                         compatible = "mediatek,mt8173-vencsys", "syscon";
1084                         reg = <0 0x18000000 0 0x1000>;
1085                         #clock-cells = <1>;
1086                 };
1087
1088                 larb3: larb@18001000 {
1089                         compatible = "mediatek,mt8173-smi-larb";
1090                         reg = <0 0x18001000 0 0x1000>;
1091                         mediatek,smi = <&smi_common>;
1092                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1093                         clocks = <&vencsys CLK_VENC_CKE1>,
1094                                  <&vencsys CLK_VENC_CKE0>;
1095                         clock-names = "apb", "smi";
1096                 };
1097
1098                 vcodec_enc: vcodec@18002000 {
1099                         compatible = "mediatek,mt8173-vcodec-enc";
1100                         reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
1101                               <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
1102                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1103                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1104                         mediatek,larb = <&larb3>,
1105                                         <&larb5>;
1106                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1107                                  <&iommu M4U_PORT_VENC_REC>,
1108                                  <&iommu M4U_PORT_VENC_BSDMA>,
1109                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1110                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1111                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1112                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1113                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1114                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1115                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1116                                  <&iommu M4U_PORT_VENC_NBM_WDMA>,
1117                                  <&iommu M4U_PORT_VENC_RCPU_SET2>,
1118                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1119                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1120                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1121                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1122                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1123                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1124                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1125                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1126                         mediatek,vpu = <&vpu>;
1127                         clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1128                                  <&topckgen CLK_TOP_VENC_SEL>,
1129                                  <&topckgen CLK_TOP_UNIVPLL1_D2>,
1130                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
1131                         clock-names = "venc_sel_src",
1132                                       "venc_sel",
1133                                       "venc_lt_sel_src",
1134                                       "venc_lt_sel";
1135                 };
1136
1137                 vencltsys: clock-controller@19000000 {
1138                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1139                         reg = <0 0x19000000 0 0x1000>;
1140                         #clock-cells = <1>;
1141                 };
1142
1143                 larb5: larb@19001000 {
1144                         compatible = "mediatek,mt8173-smi-larb";
1145                         reg = <0 0x19001000 0 0x1000>;
1146                         mediatek,smi = <&smi_common>;
1147                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1148                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1149                                  <&vencltsys CLK_VENCLT_CKE0>;
1150                         clock-names = "apb", "smi";
1151                 };
1152         };
1153 };
1154