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Merge tag 'socfpga_updates_for_v4.20_part3' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / nvidia / tegra186.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12 / {
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 misc@100000 {
19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
22 };
23
24 gpio: gpio@2200000 {
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
39 };
40
41 ethernet@2490000 {
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
62 reset-names = "eqos";
63 status = "disabled";
64
65 snps,write-requests = <1>;
66 snps,read-requests = <3>;
67 snps,burst-map = <0x7>;
68 snps,txpbl = <32>;
69 snps,rxpbl = <8>;
70 };
71
72 memory-controller@2c00000 {
73 compatible = "nvidia,tegra186-mc";
74 reg = <0x0 0x02c00000 0x0 0xb0000>;
75 status = "disabled";
76 };
77
78 uarta: serial@3100000 {
79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
80 reg = <0x0 0x03100000 0x0 0x40>;
81 reg-shift = <2>;
82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&bpmp TEGRA186_CLK_UARTA>;
84 clock-names = "serial";
85 resets = <&bpmp TEGRA186_RESET_UARTA>;
86 reset-names = "serial";
87 status = "disabled";
88 };
89
90 uartb: serial@3110000 {
91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
92 reg = <0x0 0x03110000 0x0 0x40>;
93 reg-shift = <2>;
94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&bpmp TEGRA186_CLK_UARTB>;
96 clock-names = "serial";
97 resets = <&bpmp TEGRA186_RESET_UARTB>;
98 reset-names = "serial";
99 status = "disabled";
100 };
101
102 uartd: serial@3130000 {
103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
104 reg = <0x0 0x03130000 0x0 0x40>;
105 reg-shift = <2>;
106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&bpmp TEGRA186_CLK_UARTD>;
108 clock-names = "serial";
109 resets = <&bpmp TEGRA186_RESET_UARTD>;
110 reset-names = "serial";
111 status = "disabled";
112 };
113
114 uarte: serial@3140000 {
115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
116 reg = <0x0 0x03140000 0x0 0x40>;
117 reg-shift = <2>;
118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&bpmp TEGRA186_CLK_UARTE>;
120 clock-names = "serial";
121 resets = <&bpmp TEGRA186_RESET_UARTE>;
122 reset-names = "serial";
123 status = "disabled";
124 };
125
126 uartf: serial@3150000 {
127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
128 reg = <0x0 0x03150000 0x0 0x40>;
129 reg-shift = <2>;
130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&bpmp TEGRA186_CLK_UARTF>;
132 clock-names = "serial";
133 resets = <&bpmp TEGRA186_RESET_UARTF>;
134 reset-names = "serial";
135 status = "disabled";
136 };
137
138 gen1_i2c: i2c@3160000 {
139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
140 reg = <0x0 0x03160000 0x0 0x10000>;
141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 clocks = <&bpmp TEGRA186_CLK_I2C1>;
145 clock-names = "div-clk";
146 resets = <&bpmp TEGRA186_RESET_I2C1>;
147 reset-names = "i2c";
148 status = "disabled";
149 };
150
151 cam_i2c: i2c@3180000 {
152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
153 reg = <0x0 0x03180000 0x0 0x10000>;
154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 clocks = <&bpmp TEGRA186_CLK_I2C3>;
158 clock-names = "div-clk";
159 resets = <&bpmp TEGRA186_RESET_I2C3>;
160 reset-names = "i2c";
161 status = "disabled";
162 };
163
164 /* shares pads with dpaux1 */
165 dp_aux_ch1_i2c: i2c@3190000 {
166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
167 reg = <0x0 0x03190000 0x0 0x10000>;
168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 clocks = <&bpmp TEGRA186_CLK_I2C4>;
172 clock-names = "div-clk";
173 resets = <&bpmp TEGRA186_RESET_I2C4>;
174 reset-names = "i2c";
175 status = "disabled";
176 };
177
178 /* controlled by BPMP, should not be enabled */
179 pwr_i2c: i2c@31a0000 {
180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
181 reg = <0x0 0x031a0000 0x0 0x10000>;
182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 clocks = <&bpmp TEGRA186_CLK_I2C5>;
186 clock-names = "div-clk";
187 resets = <&bpmp TEGRA186_RESET_I2C5>;
188 reset-names = "i2c";
189 status = "disabled";
190 };
191
192 /* shares pads with dpaux0 */
193 dp_aux_ch0_i2c: i2c@31b0000 {
194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
195 reg = <0x0 0x031b0000 0x0 0x10000>;
196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 clocks = <&bpmp TEGRA186_CLK_I2C6>;
200 clock-names = "div-clk";
201 resets = <&bpmp TEGRA186_RESET_I2C6>;
202 reset-names = "i2c";
203 status = "disabled";
204 };
205
206 gen7_i2c: i2c@31c0000 {
207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
208 reg = <0x0 0x031c0000 0x0 0x10000>;
209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 clocks = <&bpmp TEGRA186_CLK_I2C7>;
213 clock-names = "div-clk";
214 resets = <&bpmp TEGRA186_RESET_I2C7>;
215 reset-names = "i2c";
216 status = "disabled";
217 };
218
219 gen9_i2c: i2c@31e0000 {
220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
221 reg = <0x0 0x031e0000 0x0 0x10000>;
222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 clocks = <&bpmp TEGRA186_CLK_I2C9>;
226 clock-names = "div-clk";
227 resets = <&bpmp TEGRA186_RESET_I2C9>;
228 reset-names = "i2c";
229 status = "disabled";
230 };
231
232 sdmmc1: sdhci@3400000 {
233 compatible = "nvidia,tegra186-sdhci";
234 reg = <0x0 0x03400000 0x0 0x10000>;
235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
237 clock-names = "sdhci";
238 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
239 reset-names = "sdhci";
240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
241 pinctrl-0 = <&sdmmc1_3v3>;
242 pinctrl-1 = <&sdmmc1_1v8>;
243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
249 nvidia,default-tap = <0x5>;
250 nvidia,default-trim = <0xb>;
251 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
252 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
253 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
254 status = "disabled";
255 };
256
257 sdmmc2: sdhci@3420000 {
258 compatible = "nvidia,tegra186-sdhci";
259 reg = <0x0 0x03420000 0x0 0x10000>;
260 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
262 clock-names = "sdhci";
263 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
264 reset-names = "sdhci";
265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
266 pinctrl-0 = <&sdmmc2_3v3>;
267 pinctrl-1 = <&sdmmc2_1v8>;
268 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
269 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
270 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
271 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
272 nvidia,default-tap = <0x5>;
273 nvidia,default-trim = <0xb>;
274 status = "disabled";
275 };
276
277 sdmmc3: sdhci@3440000 {
278 compatible = "nvidia,tegra186-sdhci";
279 reg = <0x0 0x03440000 0x0 0x10000>;
280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
282 clock-names = "sdhci";
283 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
284 reset-names = "sdhci";
285 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
286 pinctrl-0 = <&sdmmc3_3v3>;
287 pinctrl-1 = <&sdmmc3_1v8>;
288 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
289 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
290 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
291 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
292 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
293 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
294 nvidia,default-tap = <0x5>;
295 nvidia,default-trim = <0xb>;
296 status = "disabled";
297 };
298
299 sdmmc4: sdhci@3460000 {
300 compatible = "nvidia,tegra186-sdhci";
301 reg = <0x0 0x03460000 0x0 0x10000>;
302 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
304 clock-names = "sdhci";
305 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
306 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
307 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
308 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
309 reset-names = "sdhci";
310 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
311 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
312 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
313 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
314 nvidia,default-tap = <0x5>;
315 nvidia,default-trim = <0x9>;
316 nvidia,dqs-trim = <63>;
317 mmc-hs400-1_8v;
318 status = "disabled";
319 };
320
321 fuse@3820000 {
322 compatible = "nvidia,tegra186-efuse";
323 reg = <0x0 0x03820000 0x0 0x10000>;
324 clocks = <&bpmp TEGRA186_CLK_FUSE>;
325 clock-names = "fuse";
326 };
327
328 gic: interrupt-controller@3881000 {
329 compatible = "arm,gic-400";
330 #interrupt-cells = <3>;
331 interrupt-controller;
332 reg = <0x0 0x03881000 0x0 0x1000>,
333 <0x0 0x03882000 0x0 0x2000>;
334 interrupts = <GIC_PPI 9
335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
336 interrupt-parent = <&gic>;
337 };
338
339 hsp_top0: hsp@3c00000 {
340 compatible = "nvidia,tegra186-hsp";
341 reg = <0x0 0x03c00000 0x0 0xa0000>;
342 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-names = "doorbell";
344 #mbox-cells = <2>;
345 status = "disabled";
346 };
347
348 gen2_i2c: i2c@c240000 {
349 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
350 reg = <0x0 0x0c240000 0x0 0x10000>;
351 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354 clocks = <&bpmp TEGRA186_CLK_I2C2>;
355 clock-names = "div-clk";
356 resets = <&bpmp TEGRA186_RESET_I2C2>;
357 reset-names = "i2c";
358 status = "disabled";
359 };
360
361 gen8_i2c: i2c@c250000 {
362 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
363 reg = <0x0 0x0c250000 0x0 0x10000>;
364 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 clocks = <&bpmp TEGRA186_CLK_I2C8>;
368 clock-names = "div-clk";
369 resets = <&bpmp TEGRA186_RESET_I2C8>;
370 reset-names = "i2c";
371 status = "disabled";
372 };
373
374 uartc: serial@c280000 {
375 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
376 reg = <0x0 0x0c280000 0x0 0x40>;
377 reg-shift = <2>;
378 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&bpmp TEGRA186_CLK_UARTC>;
380 clock-names = "serial";
381 resets = <&bpmp TEGRA186_RESET_UARTC>;
382 reset-names = "serial";
383 status = "disabled";
384 };
385
386 uartg: serial@c290000 {
387 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
388 reg = <0x0 0x0c290000 0x0 0x40>;
389 reg-shift = <2>;
390 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&bpmp TEGRA186_CLK_UARTG>;
392 clock-names = "serial";
393 resets = <&bpmp TEGRA186_RESET_UARTG>;
394 reset-names = "serial";
395 status = "disabled";
396 };
397
398 gpio_aon: gpio@c2f0000 {
399 compatible = "nvidia,tegra186-gpio-aon";
400 reg-names = "security", "gpio";
401 reg = <0x0 0xc2f0000 0x0 0x1000>,
402 <0x0 0xc2f1000 0x0 0x1000>;
403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
404 gpio-controller;
405 #gpio-cells = <2>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 };
409
410 pmc@c360000 {
411 compatible = "nvidia,tegra186-pmc";
412 reg = <0 0x0c360000 0 0x10000>,
413 <0 0x0c370000 0 0x10000>,
414 <0 0x0c380000 0 0x10000>,
415 <0 0x0c390000 0 0x10000>;
416 reg-names = "pmc", "wake", "aotag", "scratch";
417
418 sdmmc1_3v3: sdmmc1-3v3 {
419 pins = "sdmmc1-hv";
420 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
421 };
422
423 sdmmc1_1v8: sdmmc1-1v8 {
424 pins = "sdmmc1-hv";
425 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
426 };
427
428 sdmmc2_3v3: sdmmc2-3v3 {
429 pins = "sdmmc2-hv";
430 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
431 };
432
433 sdmmc2_1v8: sdmmc2-1v8 {
434 pins = "sdmmc2-hv";
435 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
436 };
437
438 sdmmc3_3v3: sdmmc3-3v3 {
439 pins = "sdmmc3-hv";
440 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
441 };
442
443 sdmmc3_1v8: sdmmc3-1v8 {
444 pins = "sdmmc3-hv";
445 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
446 };
447 };
448
449 ccplex@e000000 {
450 compatible = "nvidia,tegra186-ccplex-cluster";
451 reg = <0x0 0x0e000000 0x0 0x3fffff>;
452
453 nvidia,bpmp = <&bpmp>;
454 };
455
456 pcie@10003000 {
457 compatible = "nvidia,tegra186-pcie";
458 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
459 device_type = "pci";
460 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
461 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
462 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
463 reg-names = "pads", "afi", "cs";
464
465 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
466 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
467 interrupt-names = "intr", "msi";
468
469 #interrupt-cells = <1>;
470 interrupt-map-mask = <0 0 0 0>;
471 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
472
473 bus-range = <0x00 0xff>;
474 #address-cells = <3>;
475 #size-cells = <2>;
476
477 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
478 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
479 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
480 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
481 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
482 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
483
484 clocks = <&bpmp TEGRA186_CLK_AFI>,
485 <&bpmp TEGRA186_CLK_PCIE>,
486 <&bpmp TEGRA186_CLK_PLLE>;
487 clock-names = "afi", "pex", "pll_e";
488
489 resets = <&bpmp TEGRA186_RESET_AFI>,
490 <&bpmp TEGRA186_RESET_PCIE>,
491 <&bpmp TEGRA186_RESET_PCIEXCLK>;
492 reset-names = "afi", "pex", "pcie_x";
493
494 status = "disabled";
495
496 pci@1,0 {
497 device_type = "pci";
498 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
499 reg = <0x000800 0 0 0 0>;
500 status = "disabled";
501
502 #address-cells = <3>;
503 #size-cells = <2>;
504 ranges;
505
506 nvidia,num-lanes = <2>;
507 };
508
509 pci@2,0 {
510 device_type = "pci";
511 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
512 reg = <0x001000 0 0 0 0>;
513 status = "disabled";
514
515 #address-cells = <3>;
516 #size-cells = <2>;
517 ranges;
518
519 nvidia,num-lanes = <1>;
520 };
521
522 pci@3,0 {
523 device_type = "pci";
524 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
525 reg = <0x001800 0 0 0 0>;
526 status = "disabled";
527
528 #address-cells = <3>;
529 #size-cells = <2>;
530 ranges;
531
532 nvidia,num-lanes = <1>;
533 };
534 };
535
536 smmu: iommu@12000000 {
537 compatible = "arm,mmu-500";
538 reg = <0 0x12000000 0 0x800000>;
539 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
604 stream-match-mask = <0x7f80>;
605 #global-interrupts = <1>;
606 #iommu-cells = <1>;
607 };
608
609 host1x@13e00000 {
610 compatible = "nvidia,tegra186-host1x", "simple-bus";
611 reg = <0x0 0x13e00000 0x0 0x10000>,
612 <0x0 0x13e10000 0x0 0x10000>;
613 reg-names = "hypervisor", "vm";
614 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
617 clock-names = "host1x";
618 resets = <&bpmp TEGRA186_RESET_HOST1X>;
619 reset-names = "host1x";
620
621 #address-cells = <1>;
622 #size-cells = <1>;
623
624 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
625 iommus = <&smmu TEGRA186_SID_HOST1X>;
626
627 dpaux1: dpaux@15040000 {
628 compatible = "nvidia,tegra186-dpaux";
629 reg = <0x15040000 0x10000>;
630 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
632 <&bpmp TEGRA186_CLK_PLLDP>;
633 clock-names = "dpaux", "parent";
634 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
635 reset-names = "dpaux";
636 status = "disabled";
637
638 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
639
640 state_dpaux1_aux: pinmux-aux {
641 groups = "dpaux-io";
642 function = "aux";
643 };
644
645 state_dpaux1_i2c: pinmux-i2c {
646 groups = "dpaux-io";
647 function = "i2c";
648 };
649
650 state_dpaux1_off: pinmux-off {
651 groups = "dpaux-io";
652 function = "off";
653 };
654
655 i2c-bus {
656 #address-cells = <1>;
657 #size-cells = <0>;
658 };
659 };
660
661 display-hub@15200000 {
662 compatible = "nvidia,tegra186-display", "simple-bus";
663 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
664 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
665 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
666 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
667 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
668 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
669 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
670 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
671 "wgrp3", "wgrp4", "wgrp5";
672 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
673 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
674 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
675 clock-names = "disp", "dsc", "hub";
676 status = "disabled";
677
678 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
679
680 #address-cells = <1>;
681 #size-cells = <1>;
682
683 ranges = <0x15200000 0x15200000 0x40000>;
684
685 display@15200000 {
686 compatible = "nvidia,tegra186-dc";
687 reg = <0x15200000 0x10000>;
688 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
690 clock-names = "dc";
691 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
692 reset-names = "dc";
693
694 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
695 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
696
697 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
698 nvidia,head = <0>;
699 };
700
701 display@15210000 {
702 compatible = "nvidia,tegra186-dc";
703 reg = <0x15210000 0x10000>;
704 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
706 clock-names = "dc";
707 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
708 reset-names = "dc";
709
710 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
711 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
712
713 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
714 nvidia,head = <1>;
715 };
716
717 display@15220000 {
718 compatible = "nvidia,tegra186-dc";
719 reg = <0x15220000 0x10000>;
720 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
722 clock-names = "dc";
723 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
724 reset-names = "dc";
725
726 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
727 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
728
729 nvidia,outputs = <&sor0 &sor1>;
730 nvidia,head = <2>;
731 };
732 };
733
734 dsia: dsi@15300000 {
735 compatible = "nvidia,tegra186-dsi";
736 reg = <0x15300000 0x10000>;
737 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&bpmp TEGRA186_CLK_DSI>,
739 <&bpmp TEGRA186_CLK_DSIA_LP>,
740 <&bpmp TEGRA186_CLK_PLLD>;
741 clock-names = "dsi", "lp", "parent";
742 resets = <&bpmp TEGRA186_RESET_DSI>;
743 reset-names = "dsi";
744 status = "disabled";
745
746 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
747 };
748
749 vic@15340000 {
750 compatible = "nvidia,tegra186-vic";
751 reg = <0x15340000 0x40000>;
752 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&bpmp TEGRA186_CLK_VIC>;
754 clock-names = "vic";
755 resets = <&bpmp TEGRA186_RESET_VIC>;
756 reset-names = "vic";
757
758 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
759 };
760
761 dsib: dsi@15400000 {
762 compatible = "nvidia,tegra186-dsi";
763 reg = <0x15400000 0x10000>;
764 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&bpmp TEGRA186_CLK_DSIB>,
766 <&bpmp TEGRA186_CLK_DSIB_LP>,
767 <&bpmp TEGRA186_CLK_PLLD>;
768 clock-names = "dsi", "lp", "parent";
769 resets = <&bpmp TEGRA186_RESET_DSIB>;
770 reset-names = "dsi";
771 status = "disabled";
772
773 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
774 };
775
776 sor0: sor@15540000 {
777 compatible = "nvidia,tegra186-sor";
778 reg = <0x15540000 0x10000>;
779 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&bpmp TEGRA186_CLK_SOR0>,
781 <&bpmp TEGRA186_CLK_SOR0_OUT>,
782 <&bpmp TEGRA186_CLK_PLLD2>,
783 <&bpmp TEGRA186_CLK_PLLDP>,
784 <&bpmp TEGRA186_CLK_SOR_SAFE>,
785 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
786 clock-names = "sor", "out", "parent", "dp", "safe",
787 "pad";
788 resets = <&bpmp TEGRA186_RESET_SOR0>;
789 reset-names = "sor";
790 pinctrl-0 = <&state_dpaux_aux>;
791 pinctrl-1 = <&state_dpaux_i2c>;
792 pinctrl-2 = <&state_dpaux_off>;
793 pinctrl-names = "aux", "i2c", "off";
794 status = "disabled";
795
796 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
797 nvidia,interface = <0>;
798 };
799
800 sor1: sor@15580000 {
801 compatible = "nvidia,tegra186-sor1";
802 reg = <0x15580000 0x10000>;
803 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&bpmp TEGRA186_CLK_SOR1>,
805 <&bpmp TEGRA186_CLK_SOR1_OUT>,
806 <&bpmp TEGRA186_CLK_PLLD3>,
807 <&bpmp TEGRA186_CLK_PLLDP>,
808 <&bpmp TEGRA186_CLK_SOR_SAFE>,
809 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
810 clock-names = "sor", "out", "parent", "dp", "safe",
811 "pad";
812 resets = <&bpmp TEGRA186_RESET_SOR1>;
813 reset-names = "sor";
814 pinctrl-0 = <&state_dpaux1_aux>;
815 pinctrl-1 = <&state_dpaux1_i2c>;
816 pinctrl-2 = <&state_dpaux1_off>;
817 pinctrl-names = "aux", "i2c", "off";
818 status = "disabled";
819
820 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
821 nvidia,interface = <1>;
822 };
823
824 dpaux: dpaux@155c0000 {
825 compatible = "nvidia,tegra186-dpaux";
826 reg = <0x155c0000 0x10000>;
827 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
829 <&bpmp TEGRA186_CLK_PLLDP>;
830 clock-names = "dpaux", "parent";
831 resets = <&bpmp TEGRA186_RESET_DPAUX>;
832 reset-names = "dpaux";
833 status = "disabled";
834
835 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
836
837 state_dpaux_aux: pinmux-aux {
838 groups = "dpaux-io";
839 function = "aux";
840 };
841
842 state_dpaux_i2c: pinmux-i2c {
843 groups = "dpaux-io";
844 function = "i2c";
845 };
846
847 state_dpaux_off: pinmux-off {
848 groups = "dpaux-io";
849 function = "off";
850 };
851
852 i2c-bus {
853 #address-cells = <1>;
854 #size-cells = <0>;
855 };
856 };
857
858 padctl@15880000 {
859 compatible = "nvidia,tegra186-dsi-padctl";
860 reg = <0x15880000 0x10000>;
861 resets = <&bpmp TEGRA186_RESET_DSI>;
862 reset-names = "dsi";
863 status = "disabled";
864 };
865
866 dsic: dsi@15900000 {
867 compatible = "nvidia,tegra186-dsi";
868 reg = <0x15900000 0x10000>;
869 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&bpmp TEGRA186_CLK_DSIC>,
871 <&bpmp TEGRA186_CLK_DSIC_LP>,
872 <&bpmp TEGRA186_CLK_PLLD>;
873 clock-names = "dsi", "lp", "parent";
874 resets = <&bpmp TEGRA186_RESET_DSIC>;
875 reset-names = "dsi";
876 status = "disabled";
877
878 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
879 };
880
881 dsid: dsi@15940000 {
882 compatible = "nvidia,tegra186-dsi";
883 reg = <0x15940000 0x10000>;
884 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&bpmp TEGRA186_CLK_DSID>,
886 <&bpmp TEGRA186_CLK_DSID_LP>,
887 <&bpmp TEGRA186_CLK_PLLD>;
888 clock-names = "dsi", "lp", "parent";
889 resets = <&bpmp TEGRA186_RESET_DSID>;
890 reset-names = "dsi";
891 status = "disabled";
892
893 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
894 };
895 };
896
897 gpu@17000000 {
898 compatible = "nvidia,gp10b";
899 reg = <0x0 0x17000000 0x0 0x1000000>,
900 <0x0 0x18000000 0x0 0x1000000>;
901 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
902 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "stall", "nonstall";
904
905 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
906 <&bpmp TEGRA186_CLK_GPU>;
907 clock-names = "gpu", "pwr";
908 resets = <&bpmp TEGRA186_RESET_GPU>;
909 reset-names = "gpu";
910 status = "disabled";
911
912 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
913 };
914
915 sysram@30000000 {
916 compatible = "nvidia,tegra186-sysram", "mmio-sram";
917 reg = <0x0 0x30000000 0x0 0x50000>;
918 #address-cells = <2>;
919 #size-cells = <2>;
920 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
921
922 cpu_bpmp_tx: shmem@4e000 {
923 compatible = "nvidia,tegra186-bpmp-shmem";
924 reg = <0x0 0x4e000 0x0 0x1000>;
925 label = "cpu-bpmp-tx";
926 pool;
927 };
928
929 cpu_bpmp_rx: shmem@4f000 {
930 compatible = "nvidia,tegra186-bpmp-shmem";
931 reg = <0x0 0x4f000 0x0 0x1000>;
932 label = "cpu-bpmp-rx";
933 pool;
934 };
935 };
936
937 cpus {
938 #address-cells = <1>;
939 #size-cells = <0>;
940
941 cpu@0 {
942 compatible = "nvidia,tegra186-denver", "arm,armv8";
943 device_type = "cpu";
944 reg = <0x000>;
945 };
946
947 cpu@1 {
948 compatible = "nvidia,tegra186-denver", "arm,armv8";
949 device_type = "cpu";
950 reg = <0x001>;
951 };
952
953 cpu@2 {
954 compatible = "arm,cortex-a57", "arm,armv8";
955 device_type = "cpu";
956 reg = <0x100>;
957 };
958
959 cpu@3 {
960 compatible = "arm,cortex-a57", "arm,armv8";
961 device_type = "cpu";
962 reg = <0x101>;
963 };
964
965 cpu@4 {
966 compatible = "arm,cortex-a57", "arm,armv8";
967 device_type = "cpu";
968 reg = <0x102>;
969 };
970
971 cpu@5 {
972 compatible = "arm,cortex-a57", "arm,armv8";
973 device_type = "cpu";
974 reg = <0x103>;
975 };
976 };
977
978 bpmp: bpmp {
979 compatible = "nvidia,tegra186-bpmp";
980 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
981 TEGRA_HSP_DB_MASTER_BPMP>;
982 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
983 #clock-cells = <1>;
984 #reset-cells = <1>;
985 #power-domain-cells = <1>;
986
987 bpmp_i2c: i2c {
988 compatible = "nvidia,tegra186-bpmp-i2c";
989 nvidia,bpmp-bus-id = <5>;
990 #address-cells = <1>;
991 #size-cells = <0>;
992 status = "disabled";
993 };
994
995 bpmp_thermal: thermal {
996 compatible = "nvidia,tegra186-bpmp-thermal";
997 #thermal-sensor-cells = <1>;
998 };
999 };
1000
1001 thermal-zones {
1002 a57 {
1003 polling-delay = <0>;
1004 polling-delay-passive = <1000>;
1005
1006 thermal-sensors =
1007 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1008
1009 trips {
1010 critical {
1011 temperature = <101000>;
1012 hysteresis = <0>;
1013 type = "critical";
1014 };
1015 };
1016
1017 cooling-maps {
1018 };
1019 };
1020
1021 denver {
1022 polling-delay = <0>;
1023 polling-delay-passive = <1000>;
1024
1025 thermal-sensors =
1026 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1027
1028 trips {
1029 critical {
1030 temperature = <101000>;
1031 hysteresis = <0>;
1032 type = "critical";
1033 };
1034 };
1035
1036 cooling-maps {
1037 };
1038 };
1039
1040 gpu {
1041 polling-delay = <0>;
1042 polling-delay-passive = <1000>;
1043
1044 thermal-sensors =
1045 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1046
1047 trips {
1048 critical {
1049 temperature = <101000>;
1050 hysteresis = <0>;
1051 type = "critical";
1052 };
1053 };
1054
1055 cooling-maps {
1056 };
1057 };
1058
1059 pll {
1060 polling-delay = <0>;
1061 polling-delay-passive = <1000>;
1062
1063 thermal-sensors =
1064 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1065
1066 trips {
1067 critical {
1068 temperature = <101000>;
1069 hysteresis = <0>;
1070 type = "critical";
1071 };
1072 };
1073
1074 cooling-maps {
1075 };
1076 };
1077
1078 always_on {
1079 polling-delay = <0>;
1080 polling-delay-passive = <1000>;
1081
1082 thermal-sensors =
1083 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1084
1085 trips {
1086 critical {
1087 temperature = <101000>;
1088 hysteresis = <0>;
1089 type = "critical";
1090 };
1091 };
1092
1093 cooling-maps {
1094 };
1095 };
1096 };
1097
1098 timer {
1099 compatible = "arm,armv8-timer";
1100 interrupts = <GIC_PPI 13
1101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1102 <GIC_PPI 14
1103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1104 <GIC_PPI 11
1105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1106 <GIC_PPI 10
1107 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1108 interrupt-parent = <&gic>;
1109 };
1110 };
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