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[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / boot / dts / nvidia / tegra186.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12 / {
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 misc@100000 {
19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
22 };
23
24 gpio: gpio@2200000 {
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
39 };
40
41 ethernet@2490000 {
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
62 reset-names = "eqos";
63 status = "disabled";
64
65 snps,write-requests = <1>;
66 snps,read-requests = <3>;
67 snps,burst-map = <0x7>;
68 snps,txpbl = <32>;
69 snps,rxpbl = <8>;
70 };
71
72 memory-controller@2c00000 {
73 compatible = "nvidia,tegra186-mc";
74 reg = <0x0 0x02c00000 0x0 0xb0000>;
75 status = "disabled";
76 };
77
78 uarta: serial@3100000 {
79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
80 reg = <0x0 0x03100000 0x0 0x40>;
81 reg-shift = <2>;
82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&bpmp TEGRA186_CLK_UARTA>;
84 clock-names = "serial";
85 resets = <&bpmp TEGRA186_RESET_UARTA>;
86 reset-names = "serial";
87 status = "disabled";
88 };
89
90 uartb: serial@3110000 {
91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
92 reg = <0x0 0x03110000 0x0 0x40>;
93 reg-shift = <2>;
94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&bpmp TEGRA186_CLK_UARTB>;
96 clock-names = "serial";
97 resets = <&bpmp TEGRA186_RESET_UARTB>;
98 reset-names = "serial";
99 status = "disabled";
100 };
101
102 uartd: serial@3130000 {
103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
104 reg = <0x0 0x03130000 0x0 0x40>;
105 reg-shift = <2>;
106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&bpmp TEGRA186_CLK_UARTD>;
108 clock-names = "serial";
109 resets = <&bpmp TEGRA186_RESET_UARTD>;
110 reset-names = "serial";
111 status = "disabled";
112 };
113
114 uarte: serial@3140000 {
115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
116 reg = <0x0 0x03140000 0x0 0x40>;
117 reg-shift = <2>;
118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&bpmp TEGRA186_CLK_UARTE>;
120 clock-names = "serial";
121 resets = <&bpmp TEGRA186_RESET_UARTE>;
122 reset-names = "serial";
123 status = "disabled";
124 };
125
126 uartf: serial@3150000 {
127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
128 reg = <0x0 0x03150000 0x0 0x40>;
129 reg-shift = <2>;
130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&bpmp TEGRA186_CLK_UARTF>;
132 clock-names = "serial";
133 resets = <&bpmp TEGRA186_RESET_UARTF>;
134 reset-names = "serial";
135 status = "disabled";
136 };
137
138 gen1_i2c: i2c@3160000 {
139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
140 reg = <0x0 0x03160000 0x0 0x10000>;
141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 clocks = <&bpmp TEGRA186_CLK_I2C1>;
145 clock-names = "div-clk";
146 resets = <&bpmp TEGRA186_RESET_I2C1>;
147 reset-names = "i2c";
148 status = "disabled";
149 };
150
151 cam_i2c: i2c@3180000 {
152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
153 reg = <0x0 0x03180000 0x0 0x10000>;
154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 clocks = <&bpmp TEGRA186_CLK_I2C3>;
158 clock-names = "div-clk";
159 resets = <&bpmp TEGRA186_RESET_I2C3>;
160 reset-names = "i2c";
161 status = "disabled";
162 };
163
164 /* shares pads with dpaux1 */
165 dp_aux_ch1_i2c: i2c@3190000 {
166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
167 reg = <0x0 0x03190000 0x0 0x10000>;
168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 clocks = <&bpmp TEGRA186_CLK_I2C4>;
172 clock-names = "div-clk";
173 resets = <&bpmp TEGRA186_RESET_I2C4>;
174 reset-names = "i2c";
175 status = "disabled";
176 };
177
178 /* controlled by BPMP, should not be enabled */
179 pwr_i2c: i2c@31a0000 {
180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
181 reg = <0x0 0x031a0000 0x0 0x10000>;
182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 clocks = <&bpmp TEGRA186_CLK_I2C5>;
186 clock-names = "div-clk";
187 resets = <&bpmp TEGRA186_RESET_I2C5>;
188 reset-names = "i2c";
189 status = "disabled";
190 };
191
192 /* shares pads with dpaux0 */
193 dp_aux_ch0_i2c: i2c@31b0000 {
194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
195 reg = <0x0 0x031b0000 0x0 0x10000>;
196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 clocks = <&bpmp TEGRA186_CLK_I2C6>;
200 clock-names = "div-clk";
201 resets = <&bpmp TEGRA186_RESET_I2C6>;
202 reset-names = "i2c";
203 status = "disabled";
204 };
205
206 gen7_i2c: i2c@31c0000 {
207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
208 reg = <0x0 0x031c0000 0x0 0x10000>;
209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 clocks = <&bpmp TEGRA186_CLK_I2C7>;
213 clock-names = "div-clk";
214 resets = <&bpmp TEGRA186_RESET_I2C7>;
215 reset-names = "i2c";
216 status = "disabled";
217 };
218
219 gen9_i2c: i2c@31e0000 {
220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
221 reg = <0x0 0x031e0000 0x0 0x10000>;
222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 clocks = <&bpmp TEGRA186_CLK_I2C9>;
226 clock-names = "div-clk";
227 resets = <&bpmp TEGRA186_RESET_I2C9>;
228 reset-names = "i2c";
229 status = "disabled";
230 };
231
232 sdmmc1: sdhci@3400000 {
233 compatible = "nvidia,tegra186-sdhci";
234 reg = <0x0 0x03400000 0x0 0x10000>;
235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
237 clock-names = "sdhci";
238 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
239 reset-names = "sdhci";
240 iommus = <&smmu TEGRA186_SID_SDMMC1>;
241 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
242 pinctrl-0 = <&sdmmc1_3v3>;
243 pinctrl-1 = <&sdmmc1_1v8>;
244 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
245 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
246 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
247 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
248 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
249 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
250 nvidia,default-tap = <0x5>;
251 nvidia,default-trim = <0xb>;
252 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
253 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
254 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
255 status = "disabled";
256 };
257
258 sdmmc2: sdhci@3420000 {
259 compatible = "nvidia,tegra186-sdhci";
260 reg = <0x0 0x03420000 0x0 0x10000>;
261 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
263 clock-names = "sdhci";
264 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
265 reset-names = "sdhci";
266 iommus = <&smmu TEGRA186_SID_SDMMC2>;
267 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
268 pinctrl-0 = <&sdmmc2_3v3>;
269 pinctrl-1 = <&sdmmc2_1v8>;
270 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
271 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
272 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
273 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
274 nvidia,default-tap = <0x5>;
275 nvidia,default-trim = <0xb>;
276 status = "disabled";
277 };
278
279 sdmmc3: sdhci@3440000 {
280 compatible = "nvidia,tegra186-sdhci";
281 reg = <0x0 0x03440000 0x0 0x10000>;
282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
284 clock-names = "sdhci";
285 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
286 reset-names = "sdhci";
287 iommus = <&smmu TEGRA186_SID_SDMMC3>;
288 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
289 pinctrl-0 = <&sdmmc3_3v3>;
290 pinctrl-1 = <&sdmmc3_1v8>;
291 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
292 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
293 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
294 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
295 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
296 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
297 nvidia,default-tap = <0x5>;
298 nvidia,default-trim = <0xb>;
299 status = "disabled";
300 };
301
302 sdmmc4: sdhci@3460000 {
303 compatible = "nvidia,tegra186-sdhci";
304 reg = <0x0 0x03460000 0x0 0x10000>;
305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
307 clock-names = "sdhci";
308 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
309 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
310 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
311 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
312 reset-names = "sdhci";
313 iommus = <&smmu TEGRA186_SID_SDMMC4>;
314 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
315 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
316 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
317 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
318 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
319 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
320 nvidia,default-tap = <0x5>;
321 nvidia,default-trim = <0x9>;
322 nvidia,dqs-trim = <63>;
323 mmc-hs400-1_8v;
324 status = "disabled";
325 };
326
327 hda@3510000 {
328 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
329 reg = <0x0 0x03510000 0x0 0x10000>;
330 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&bpmp TEGRA186_CLK_HDA>,
332 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
333 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
334 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
335 resets = <&bpmp TEGRA186_RESET_HDA>,
336 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
337 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
338 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
339 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
340 status = "disabled";
341 };
342
343 fuse@3820000 {
344 compatible = "nvidia,tegra186-efuse";
345 reg = <0x0 0x03820000 0x0 0x10000>;
346 clocks = <&bpmp TEGRA186_CLK_FUSE>;
347 clock-names = "fuse";
348 };
349
350 gic: interrupt-controller@3881000 {
351 compatible = "arm,gic-400";
352 #interrupt-cells = <3>;
353 interrupt-controller;
354 reg = <0x0 0x03881000 0x0 0x1000>,
355 <0x0 0x03882000 0x0 0x2000>;
356 interrupts = <GIC_PPI 9
357 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
358 interrupt-parent = <&gic>;
359 };
360
361 cec@3960000 {
362 compatible = "nvidia,tegra186-cec";
363 reg = <0x0 0x03960000 0x0 0x10000>;
364 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&bpmp TEGRA186_CLK_CEC>;
366 clock-names = "cec";
367 status = "disabled";
368 };
369
370 hsp_top0: hsp@3c00000 {
371 compatible = "nvidia,tegra186-hsp";
372 reg = <0x0 0x03c00000 0x0 0xa0000>;
373 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
374 interrupt-names = "doorbell";
375 #mbox-cells = <2>;
376 status = "disabled";
377 };
378
379 gen2_i2c: i2c@c240000 {
380 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
381 reg = <0x0 0x0c240000 0x0 0x10000>;
382 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clocks = <&bpmp TEGRA186_CLK_I2C2>;
386 clock-names = "div-clk";
387 resets = <&bpmp TEGRA186_RESET_I2C2>;
388 reset-names = "i2c";
389 status = "disabled";
390 };
391
392 gen8_i2c: i2c@c250000 {
393 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
394 reg = <0x0 0x0c250000 0x0 0x10000>;
395 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 clocks = <&bpmp TEGRA186_CLK_I2C8>;
399 clock-names = "div-clk";
400 resets = <&bpmp TEGRA186_RESET_I2C8>;
401 reset-names = "i2c";
402 status = "disabled";
403 };
404
405 uartc: serial@c280000 {
406 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
407 reg = <0x0 0x0c280000 0x0 0x40>;
408 reg-shift = <2>;
409 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&bpmp TEGRA186_CLK_UARTC>;
411 clock-names = "serial";
412 resets = <&bpmp TEGRA186_RESET_UARTC>;
413 reset-names = "serial";
414 status = "disabled";
415 };
416
417 uartg: serial@c290000 {
418 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
419 reg = <0x0 0x0c290000 0x0 0x40>;
420 reg-shift = <2>;
421 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&bpmp TEGRA186_CLK_UARTG>;
423 clock-names = "serial";
424 resets = <&bpmp TEGRA186_RESET_UARTG>;
425 reset-names = "serial";
426 status = "disabled";
427 };
428
429 rtc: rtc@c2a0000 {
430 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
431 reg = <0 0x0c2a0000 0 0x10000>;
432 interrupt-parent = <&pmc>;
433 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
435 clock-names = "rtc";
436 status = "disabled";
437 };
438
439 gpio_aon: gpio@c2f0000 {
440 compatible = "nvidia,tegra186-gpio-aon";
441 reg-names = "security", "gpio";
442 reg = <0x0 0xc2f0000 0x0 0x1000>,
443 <0x0 0xc2f1000 0x0 0x1000>;
444 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
445 gpio-controller;
446 #gpio-cells = <2>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 };
450
451 pmc: pmc@c360000 {
452 compatible = "nvidia,tegra186-pmc";
453 reg = <0 0x0c360000 0 0x10000>,
454 <0 0x0c370000 0 0x10000>,
455 <0 0x0c380000 0 0x10000>,
456 <0 0x0c390000 0 0x10000>;
457 reg-names = "pmc", "wake", "aotag", "scratch";
458
459 #interrupt-cells = <2>;
460 interrupt-controller;
461
462 sdmmc1_3v3: sdmmc1-3v3 {
463 pins = "sdmmc1-hv";
464 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
465 };
466
467 sdmmc1_1v8: sdmmc1-1v8 {
468 pins = "sdmmc1-hv";
469 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
470 };
471
472 sdmmc2_3v3: sdmmc2-3v3 {
473 pins = "sdmmc2-hv";
474 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
475 };
476
477 sdmmc2_1v8: sdmmc2-1v8 {
478 pins = "sdmmc2-hv";
479 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
480 };
481
482 sdmmc3_3v3: sdmmc3-3v3 {
483 pins = "sdmmc3-hv";
484 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
485 };
486
487 sdmmc3_1v8: sdmmc3-1v8 {
488 pins = "sdmmc3-hv";
489 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
490 };
491 };
492
493 ccplex@e000000 {
494 compatible = "nvidia,tegra186-ccplex-cluster";
495 reg = <0x0 0x0e000000 0x0 0x3fffff>;
496
497 nvidia,bpmp = <&bpmp>;
498 };
499
500 pcie@10003000 {
501 compatible = "nvidia,tegra186-pcie";
502 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
503 device_type = "pci";
504 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
505 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
506 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
507 reg-names = "pads", "afi", "cs";
508
509 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
510 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
511 interrupt-names = "intr", "msi";
512
513 #interrupt-cells = <1>;
514 interrupt-map-mask = <0 0 0 0>;
515 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
516
517 bus-range = <0x00 0xff>;
518 #address-cells = <3>;
519 #size-cells = <2>;
520
521 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
522 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
523 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
524 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
525 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
526 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
527
528 clocks = <&bpmp TEGRA186_CLK_AFI>,
529 <&bpmp TEGRA186_CLK_PCIE>,
530 <&bpmp TEGRA186_CLK_PLLE>;
531 clock-names = "afi", "pex", "pll_e";
532
533 resets = <&bpmp TEGRA186_RESET_AFI>,
534 <&bpmp TEGRA186_RESET_PCIE>,
535 <&bpmp TEGRA186_RESET_PCIEXCLK>;
536 reset-names = "afi", "pex", "pcie_x";
537
538 status = "disabled";
539
540 pci@1,0 {
541 device_type = "pci";
542 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
543 reg = <0x000800 0 0 0 0>;
544 status = "disabled";
545
546 #address-cells = <3>;
547 #size-cells = <2>;
548 ranges;
549
550 nvidia,num-lanes = <2>;
551 };
552
553 pci@2,0 {
554 device_type = "pci";
555 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
556 reg = <0x001000 0 0 0 0>;
557 status = "disabled";
558
559 #address-cells = <3>;
560 #size-cells = <2>;
561 ranges;
562
563 nvidia,num-lanes = <1>;
564 };
565
566 pci@3,0 {
567 device_type = "pci";
568 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
569 reg = <0x001800 0 0 0 0>;
570 status = "disabled";
571
572 #address-cells = <3>;
573 #size-cells = <2>;
574 ranges;
575
576 nvidia,num-lanes = <1>;
577 };
578 };
579
580 smmu: iommu@12000000 {
581 compatible = "arm,mmu-500";
582 reg = <0 0x12000000 0 0x800000>;
583 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
648 stream-match-mask = <0x7f80>;
649 #global-interrupts = <1>;
650 #iommu-cells = <1>;
651 };
652
653 host1x@13e00000 {
654 compatible = "nvidia,tegra186-host1x", "simple-bus";
655 reg = <0x0 0x13e00000 0x0 0x10000>,
656 <0x0 0x13e10000 0x0 0x10000>;
657 reg-names = "hypervisor", "vm";
658 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
661 clock-names = "host1x";
662 resets = <&bpmp TEGRA186_RESET_HOST1X>;
663 reset-names = "host1x";
664
665 #address-cells = <1>;
666 #size-cells = <1>;
667
668 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
669 iommus = <&smmu TEGRA186_SID_HOST1X>;
670
671 dpaux1: dpaux@15040000 {
672 compatible = "nvidia,tegra186-dpaux";
673 reg = <0x15040000 0x10000>;
674 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
676 <&bpmp TEGRA186_CLK_PLLDP>;
677 clock-names = "dpaux", "parent";
678 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
679 reset-names = "dpaux";
680 status = "disabled";
681
682 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
683
684 state_dpaux1_aux: pinmux-aux {
685 groups = "dpaux-io";
686 function = "aux";
687 };
688
689 state_dpaux1_i2c: pinmux-i2c {
690 groups = "dpaux-io";
691 function = "i2c";
692 };
693
694 state_dpaux1_off: pinmux-off {
695 groups = "dpaux-io";
696 function = "off";
697 };
698
699 i2c-bus {
700 #address-cells = <1>;
701 #size-cells = <0>;
702 };
703 };
704
705 display-hub@15200000 {
706 compatible = "nvidia,tegra186-display", "simple-bus";
707 reg = <0x15200000 0x00040000>;
708 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
709 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
710 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
711 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
712 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
713 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
714 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
715 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
716 "wgrp3", "wgrp4", "wgrp5";
717 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
718 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
719 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
720 clock-names = "disp", "dsc", "hub";
721 status = "disabled";
722
723 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
724
725 #address-cells = <1>;
726 #size-cells = <1>;
727
728 ranges = <0x15200000 0x15200000 0x40000>;
729
730 display@15200000 {
731 compatible = "nvidia,tegra186-dc";
732 reg = <0x15200000 0x10000>;
733 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
735 clock-names = "dc";
736 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
737 reset-names = "dc";
738
739 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
740 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
741
742 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
743 nvidia,head = <0>;
744 };
745
746 display@15210000 {
747 compatible = "nvidia,tegra186-dc";
748 reg = <0x15210000 0x10000>;
749 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
751 clock-names = "dc";
752 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
753 reset-names = "dc";
754
755 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
756 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
757
758 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
759 nvidia,head = <1>;
760 };
761
762 display@15220000 {
763 compatible = "nvidia,tegra186-dc";
764 reg = <0x15220000 0x10000>;
765 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
767 clock-names = "dc";
768 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
769 reset-names = "dc";
770
771 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
772 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
773
774 nvidia,outputs = <&sor0 &sor1>;
775 nvidia,head = <2>;
776 };
777 };
778
779 dsia: dsi@15300000 {
780 compatible = "nvidia,tegra186-dsi";
781 reg = <0x15300000 0x10000>;
782 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&bpmp TEGRA186_CLK_DSI>,
784 <&bpmp TEGRA186_CLK_DSIA_LP>,
785 <&bpmp TEGRA186_CLK_PLLD>;
786 clock-names = "dsi", "lp", "parent";
787 resets = <&bpmp TEGRA186_RESET_DSI>;
788 reset-names = "dsi";
789 status = "disabled";
790
791 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
792 };
793
794 vic@15340000 {
795 compatible = "nvidia,tegra186-vic";
796 reg = <0x15340000 0x40000>;
797 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&bpmp TEGRA186_CLK_VIC>;
799 clock-names = "vic";
800 resets = <&bpmp TEGRA186_RESET_VIC>;
801 reset-names = "vic";
802
803 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
804 };
805
806 dsib: dsi@15400000 {
807 compatible = "nvidia,tegra186-dsi";
808 reg = <0x15400000 0x10000>;
809 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&bpmp TEGRA186_CLK_DSIB>,
811 <&bpmp TEGRA186_CLK_DSIB_LP>,
812 <&bpmp TEGRA186_CLK_PLLD>;
813 clock-names = "dsi", "lp", "parent";
814 resets = <&bpmp TEGRA186_RESET_DSIB>;
815 reset-names = "dsi";
816 status = "disabled";
817
818 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
819 };
820
821 sor0: sor@15540000 {
822 compatible = "nvidia,tegra186-sor";
823 reg = <0x15540000 0x10000>;
824 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&bpmp TEGRA186_CLK_SOR0>,
826 <&bpmp TEGRA186_CLK_SOR0_OUT>,
827 <&bpmp TEGRA186_CLK_PLLD2>,
828 <&bpmp TEGRA186_CLK_PLLDP>,
829 <&bpmp TEGRA186_CLK_SOR_SAFE>,
830 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
831 clock-names = "sor", "out", "parent", "dp", "safe",
832 "pad";
833 resets = <&bpmp TEGRA186_RESET_SOR0>;
834 reset-names = "sor";
835 pinctrl-0 = <&state_dpaux_aux>;
836 pinctrl-1 = <&state_dpaux_i2c>;
837 pinctrl-2 = <&state_dpaux_off>;
838 pinctrl-names = "aux", "i2c", "off";
839 status = "disabled";
840
841 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
842 nvidia,interface = <0>;
843 };
844
845 sor1: sor@15580000 {
846 compatible = "nvidia,tegra186-sor1";
847 reg = <0x15580000 0x10000>;
848 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&bpmp TEGRA186_CLK_SOR1>,
850 <&bpmp TEGRA186_CLK_SOR1_OUT>,
851 <&bpmp TEGRA186_CLK_PLLD3>,
852 <&bpmp TEGRA186_CLK_PLLDP>,
853 <&bpmp TEGRA186_CLK_SOR_SAFE>,
854 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
855 clock-names = "sor", "out", "parent", "dp", "safe",
856 "pad";
857 resets = <&bpmp TEGRA186_RESET_SOR1>;
858 reset-names = "sor";
859 pinctrl-0 = <&state_dpaux1_aux>;
860 pinctrl-1 = <&state_dpaux1_i2c>;
861 pinctrl-2 = <&state_dpaux1_off>;
862 pinctrl-names = "aux", "i2c", "off";
863 status = "disabled";
864
865 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
866 nvidia,interface = <1>;
867 };
868
869 dpaux: dpaux@155c0000 {
870 compatible = "nvidia,tegra186-dpaux";
871 reg = <0x155c0000 0x10000>;
872 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
874 <&bpmp TEGRA186_CLK_PLLDP>;
875 clock-names = "dpaux", "parent";
876 resets = <&bpmp TEGRA186_RESET_DPAUX>;
877 reset-names = "dpaux";
878 status = "disabled";
879
880 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
881
882 state_dpaux_aux: pinmux-aux {
883 groups = "dpaux-io";
884 function = "aux";
885 };
886
887 state_dpaux_i2c: pinmux-i2c {
888 groups = "dpaux-io";
889 function = "i2c";
890 };
891
892 state_dpaux_off: pinmux-off {
893 groups = "dpaux-io";
894 function = "off";
895 };
896
897 i2c-bus {
898 #address-cells = <1>;
899 #size-cells = <0>;
900 };
901 };
902
903 padctl@15880000 {
904 compatible = "nvidia,tegra186-dsi-padctl";
905 reg = <0x15880000 0x10000>;
906 resets = <&bpmp TEGRA186_RESET_DSI>;
907 reset-names = "dsi";
908 status = "disabled";
909 };
910
911 dsic: dsi@15900000 {
912 compatible = "nvidia,tegra186-dsi";
913 reg = <0x15900000 0x10000>;
914 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&bpmp TEGRA186_CLK_DSIC>,
916 <&bpmp TEGRA186_CLK_DSIC_LP>,
917 <&bpmp TEGRA186_CLK_PLLD>;
918 clock-names = "dsi", "lp", "parent";
919 resets = <&bpmp TEGRA186_RESET_DSIC>;
920 reset-names = "dsi";
921 status = "disabled";
922
923 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
924 };
925
926 dsid: dsi@15940000 {
927 compatible = "nvidia,tegra186-dsi";
928 reg = <0x15940000 0x10000>;
929 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&bpmp TEGRA186_CLK_DSID>,
931 <&bpmp TEGRA186_CLK_DSID_LP>,
932 <&bpmp TEGRA186_CLK_PLLD>;
933 clock-names = "dsi", "lp", "parent";
934 resets = <&bpmp TEGRA186_RESET_DSID>;
935 reset-names = "dsi";
936 status = "disabled";
937
938 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
939 };
940 };
941
942 gpu@17000000 {
943 compatible = "nvidia,gp10b";
944 reg = <0x0 0x17000000 0x0 0x1000000>,
945 <0x0 0x18000000 0x0 0x1000000>;
946 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
947 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
948 interrupt-names = "stall", "nonstall";
949
950 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
951 <&bpmp TEGRA186_CLK_GPU>;
952 clock-names = "gpu", "pwr";
953 resets = <&bpmp TEGRA186_RESET_GPU>;
954 reset-names = "gpu";
955 status = "disabled";
956
957 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
958 };
959
960 sysram@30000000 {
961 compatible = "nvidia,tegra186-sysram", "mmio-sram";
962 reg = <0x0 0x30000000 0x0 0x50000>;
963 #address-cells = <2>;
964 #size-cells = <2>;
965 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
966
967 cpu_bpmp_tx: shmem@4e000 {
968 compatible = "nvidia,tegra186-bpmp-shmem";
969 reg = <0x0 0x4e000 0x0 0x1000>;
970 label = "cpu-bpmp-tx";
971 pool;
972 };
973
974 cpu_bpmp_rx: shmem@4f000 {
975 compatible = "nvidia,tegra186-bpmp-shmem";
976 reg = <0x0 0x4f000 0x0 0x1000>;
977 label = "cpu-bpmp-rx";
978 pool;
979 };
980 };
981
982 cpus {
983 #address-cells = <1>;
984 #size-cells = <0>;
985
986 cpu@0 {
987 compatible = "nvidia,tegra186-denver";
988 device_type = "cpu";
989 reg = <0x000>;
990 };
991
992 cpu@1 {
993 compatible = "nvidia,tegra186-denver";
994 device_type = "cpu";
995 reg = <0x001>;
996 };
997
998 cpu@2 {
999 compatible = "arm,cortex-a57";
1000 device_type = "cpu";
1001 reg = <0x100>;
1002 };
1003
1004 cpu@3 {
1005 compatible = "arm,cortex-a57";
1006 device_type = "cpu";
1007 reg = <0x101>;
1008 };
1009
1010 cpu@4 {
1011 compatible = "arm,cortex-a57";
1012 device_type = "cpu";
1013 reg = <0x102>;
1014 };
1015
1016 cpu@5 {
1017 compatible = "arm,cortex-a57";
1018 device_type = "cpu";
1019 reg = <0x103>;
1020 };
1021 };
1022
1023 bpmp: bpmp {
1024 compatible = "nvidia,tegra186-bpmp";
1025 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1026 TEGRA_HSP_DB_MASTER_BPMP>;
1027 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1028 #clock-cells = <1>;
1029 #reset-cells = <1>;
1030 #power-domain-cells = <1>;
1031
1032 bpmp_i2c: i2c {
1033 compatible = "nvidia,tegra186-bpmp-i2c";
1034 nvidia,bpmp-bus-id = <5>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 status = "disabled";
1038 };
1039
1040 bpmp_thermal: thermal {
1041 compatible = "nvidia,tegra186-bpmp-thermal";
1042 #thermal-sensor-cells = <1>;
1043 };
1044 };
1045
1046 thermal-zones {
1047 a57 {
1048 polling-delay = <0>;
1049 polling-delay-passive = <1000>;
1050
1051 thermal-sensors =
1052 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1053
1054 trips {
1055 critical {
1056 temperature = <101000>;
1057 hysteresis = <0>;
1058 type = "critical";
1059 };
1060 };
1061
1062 cooling-maps {
1063 };
1064 };
1065
1066 denver {
1067 polling-delay = <0>;
1068 polling-delay-passive = <1000>;
1069
1070 thermal-sensors =
1071 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1072
1073 trips {
1074 critical {
1075 temperature = <101000>;
1076 hysteresis = <0>;
1077 type = "critical";
1078 };
1079 };
1080
1081 cooling-maps {
1082 };
1083 };
1084
1085 gpu {
1086 polling-delay = <0>;
1087 polling-delay-passive = <1000>;
1088
1089 thermal-sensors =
1090 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1091
1092 trips {
1093 critical {
1094 temperature = <101000>;
1095 hysteresis = <0>;
1096 type = "critical";
1097 };
1098 };
1099
1100 cooling-maps {
1101 };
1102 };
1103
1104 pll {
1105 polling-delay = <0>;
1106 polling-delay-passive = <1000>;
1107
1108 thermal-sensors =
1109 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1110
1111 trips {
1112 critical {
1113 temperature = <101000>;
1114 hysteresis = <0>;
1115 type = "critical";
1116 };
1117 };
1118
1119 cooling-maps {
1120 };
1121 };
1122
1123 always_on {
1124 polling-delay = <0>;
1125 polling-delay-passive = <1000>;
1126
1127 thermal-sensors =
1128 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1129
1130 trips {
1131 critical {
1132 temperature = <101000>;
1133 hysteresis = <0>;
1134 type = "critical";
1135 };
1136 };
1137
1138 cooling-maps {
1139 };
1140 };
1141 };
1142
1143 timer {
1144 compatible = "arm,armv8-timer";
1145 interrupts = <GIC_PPI 13
1146 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1147 <GIC_PPI 14
1148 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1149 <GIC_PPI 11
1150 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1151 <GIC_PPI 10
1152 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1153 interrupt-parent = <&gic>;
1154 };
1155 };
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