arch/arm64/boot/dts/nvidia/tegra210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra210-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra210-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/thermal/tegra124-soctherm.h>
   9
  10 / {
  11         compatible = "nvidia,tegra210";
  12         interrupt-parent = <&lic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         pcie@1003000 {
  17                 compatible = "nvidia,tegra210-pcie";
  18                 device_type = "pci";
  19                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  20                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  21                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  22                 reg-names = "pads", "afi", "cs";
  23                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  24                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  25                 interrupt-names = "intr", "msi";
  26
  27                 #interrupt-cells = <1>;
  28                 interrupt-map-mask = <0 0 0 0>;
  29                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  30
  31                 bus-range = <0x00 0xff>;
  32                 #address-cells = <3>;
  33                 #size-cells = <2>;
  34
  35                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  36                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  37                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  38                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  39                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  40
  41                 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
  42                          <&tegra_car TEGRA210_CLK_AFI>,
  43                          <&tegra_car TEGRA210_CLK_PLL_E>,
  44                          <&tegra_car TEGRA210_CLK_CML0>;
  45                 clock-names = "pex", "afi", "pll_e", "cml";
  46                 resets = <&tegra_car 70>,
  47                          <&tegra_car 72>,
  48                          <&tegra_car 74>;
  49                 reset-names = "pex", "afi", "pcie_x";
  50                 status = "disabled";
  51
  52                 pci@1,0 {
  53                         device_type = "pci";
  54                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  55                         reg = <0x000800 0 0 0 0>;
  56                         bus-range = <0x00 0xff>;
  57                         status = "disabled";
  58
  59                         #address-cells = <3>;
  60                         #size-cells = <2>;
  61                         ranges;
  62
  63                         nvidia,num-lanes = <4>;
  64                 };
  65
  66                 pci@2,0 {
  67                         device_type = "pci";
  68                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  69                         reg = <0x001000 0 0 0 0>;
  70                         bus-range = <0x00 0xff>;
  71                         status = "disabled";
  72
  73                         #address-cells = <3>;
  74                         #size-cells = <2>;
  75                         ranges;
  76
  77                         nvidia,num-lanes = <1>;
  78                 };
  79         };
  80
  81         host1x@50000000 {
  82                 compatible = "nvidia,tegra210-host1x", "simple-bus";
  83                 reg = <0x0 0x50000000 0x0 0x00034000>;
  84                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  85                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  86                 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
  87                 clock-names = "host1x";
  88                 resets = <&tegra_car 28>;
  89                 reset-names = "host1x";
  90
  91                 #address-cells = <2>;
  92                 #size-cells = <2>;
  93
  94                 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
  95
  96                 iommus = <&mc TEGRA_SWGROUP_HC>;
  97
  98                 dpaux1: dpaux@54040000 {
  99                         compatible = "nvidia,tegra210-dpaux";
 100                         reg = <0x0 0x54040000 0x0 0x00040000>;
 101                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
 103                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 104                         clock-names = "dpaux", "parent";
 105                         resets = <&tegra_car 207>;
 106                         reset-names = "dpaux";
 107                         power-domains = <&pd_sor>;
 108                         status = "disabled";
 109
 110                         state_dpaux1_aux: pinmux-aux {
 111                                 groups = "dpaux-io";
 112                                 function = "aux";
 113                         };
 114
 115                         state_dpaux1_i2c: pinmux-i2c {
 116                                 groups = "dpaux-io";
 117                                 function = "i2c";
 118                         };
 119
 120                         state_dpaux1_off: pinmux-off {
 121                                 groups = "dpaux-io";
 122                                 function = "off";
 123                         };
 124
 125                         i2c-bus {
 126                                 #address-cells = <1>;
 127                                 #size-cells = <0>;
 128                         };
 129                 };
 130
 131                 vi@54080000 {
 132                         compatible = "nvidia,tegra210-vi";
 133                         reg = <0x0 0x54080000 0x0 0x00040000>;
 134                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 135                         status = "disabled";
 136                 };
 137
 138                 tsec@54100000 {
 139                         compatible = "nvidia,tegra210-tsec";
 140                         reg = <0x0 0x54100000 0x0 0x00040000>;
 141                 };
 142
 143                 dc@54200000 {
 144                         compatible = "nvidia,tegra210-dc";
 145                         reg = <0x0 0x54200000 0x0 0x00040000>;
 146                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&tegra_car TEGRA210_CLK_DISP1>,
 148                                  <&tegra_car TEGRA210_CLK_PLL_P>;
 149                         clock-names = "dc", "parent";
 150                         resets = <&tegra_car 27>;
 151                         reset-names = "dc";
 152
 153                         iommus = <&mc TEGRA_SWGROUP_DC>;
 154
 155                         nvidia,head = <0>;
 156                 };
 157
 158                 dc@54240000 {
 159                         compatible = "nvidia,tegra210-dc";
 160                         reg = <0x0 0x54240000 0x0 0x00040000>;
 161                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 162                         clocks = <&tegra_car TEGRA210_CLK_DISP2>,
 163                                  <&tegra_car TEGRA210_CLK_PLL_P>;
 164                         clock-names = "dc", "parent";
 165                         resets = <&tegra_car 26>;
 166                         reset-names = "dc";
 167
 168                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 169
 170                         nvidia,head = <1>;
 171                 };
 172
 173                 dsi@54300000 {
 174                         compatible = "nvidia,tegra210-dsi";
 175                         reg = <0x0 0x54300000 0x0 0x00040000>;
 176                         clocks = <&tegra_car TEGRA210_CLK_DSIA>,
 177                                  <&tegra_car TEGRA210_CLK_DSIALP>,
 178                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 179                         clock-names = "dsi", "lp", "parent";
 180                         resets = <&tegra_car 48>;
 181                         reset-names = "dsi";
 182                         power-domains = <&pd_sor>;
 183                         nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
 184
 185                         status = "disabled";
 186
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                 };
 190
 191                 vic@54340000 {
 192                         compatible = "nvidia,tegra210-vic";
 193                         reg = <0x0 0x54340000 0x0 0x00040000>;
 194                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 195                         clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 196                         clock-names = "vic";
 197                         resets = <&tegra_car 178>;
 198                         reset-names = "vic";
 199
 200                         iommus = <&mc TEGRA_SWGROUP_VIC>;
 201                         power-domains = <&pd_vic>;
 202                 };
 203
 204                 nvjpg@54380000 {
 205                         compatible = "nvidia,tegra210-nvjpg";
 206                         reg = <0x0 0x54380000 0x0 0x00040000>;
 207                         status = "disabled";
 208                 };
 209
 210                 dsi@54400000 {
 211                         compatible = "nvidia,tegra210-dsi";
 212                         reg = <0x0 0x54400000 0x0 0x00040000>;
 213                         clocks = <&tegra_car TEGRA210_CLK_DSIB>,
 214                                  <&tegra_car TEGRA210_CLK_DSIBLP>,
 215                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 216                         clock-names = "dsi", "lp", "parent";
 217                         resets = <&tegra_car 82>;
 218                         reset-names = "dsi";
 219                         power-domains = <&pd_sor>;
 220                         nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
 221
 222                         status = "disabled";
 223
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                 };
 227
 228                 nvdec@54480000 {
 229                         compatible = "nvidia,tegra210-nvdec";
 230                         reg = <0x0 0x54480000 0x0 0x00040000>;
 231                         status = "disabled";
 232                 };
 233
 234                 nvenc@544c0000 {
 235                         compatible = "nvidia,tegra210-nvenc";
 236                         reg = <0x0 0x544c0000 0x0 0x00040000>;
 237                         status = "disabled";
 238                 };
 239
 240                 tsec@54500000 {
 241                         compatible = "nvidia,tegra210-tsec";
 242                         reg = <0x0 0x54500000 0x0 0x00040000>;
 243                         status = "disabled";
 244                 };
 245
 246                 sor@54540000 {
 247                         compatible = "nvidia,tegra210-sor";
 248                         reg = <0x0 0x54540000 0x0 0x00040000>;
 249                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 251                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
 252                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 253                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 254                         clock-names = "sor", "parent", "dp", "safe";
 255                         resets = <&tegra_car 182>;
 256                         reset-names = "sor";
 257                         pinctrl-0 = <&state_dpaux_aux>;
 258                         pinctrl-1 = <&state_dpaux_i2c>;
 259                         pinctrl-2 = <&state_dpaux_off>;
 260                         pinctrl-names = "aux", "i2c", "off";
 261                         power-domains = <&pd_sor>;
 262                         status = "disabled";
 263                 };
 264
 265                 sor@54580000 {
 266                         compatible = "nvidia,tegra210-sor1";
 267                         reg = <0x0 0x54580000 0x0 0x00040000>;
 268                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&tegra_car TEGRA210_CLK_SOR1>,
 270                                  <&tegra_car TEGRA210_CLK_SOR1_OUT>,
 271                                  <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
 272                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 273                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 274                         clock-names = "sor", "out", "parent", "dp", "safe";
 275                         resets = <&tegra_car 183>;
 276                         reset-names = "sor";
 277                         pinctrl-0 = <&state_dpaux1_aux>;
 278                         pinctrl-1 = <&state_dpaux1_i2c>;
 279                         pinctrl-2 = <&state_dpaux1_off>;
 280                         pinctrl-names = "aux", "i2c", "off";
 281                         power-domains = <&pd_sor>;
 282                         status = "disabled";
 283                 };
 284
 285                 dpaux: dpaux@545c0000 {
 286                         compatible = "nvidia,tegra124-dpaux";
 287                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 288                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 289                         clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
 290                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 291                         clock-names = "dpaux", "parent";
 292                         resets = <&tegra_car 181>;
 293                         reset-names = "dpaux";
 294                         power-domains = <&pd_sor>;
 295                         status = "disabled";
 296
 297                         state_dpaux_aux: pinmux-aux {
 298                                 groups = "dpaux-io";
 299                                 function = "aux";
 300                         };
 301
 302                         state_dpaux_i2c: pinmux-i2c {
 303                                 groups = "dpaux-io";
 304                                 function = "i2c";
 305                         };
 306
 307                         state_dpaux_off: pinmux-off {
 308                                 groups = "dpaux-io";
 309                                 function = "off";
 310                         };
 311
 312                         i2c-bus {
 313                                 #address-cells = <1>;
 314                                 #size-cells = <0>;
 315                         };
 316                 };
 317
 318                 isp@54600000 {
 319                         compatible = "nvidia,tegra210-isp";
 320                         reg = <0x0 0x54600000 0x0 0x00040000>;
 321                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 322                         status = "disabled";
 323                 };
 324
 325                 isp@54680000 {
 326                         compatible = "nvidia,tegra210-isp";
 327                         reg = <0x0 0x54680000 0x0 0x00040000>;
 328                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 329                         status = "disabled";
 330                 };
 331
 332                 i2c@546c0000 {
 333                         compatible = "nvidia,tegra210-i2c-vi";
 334                         reg = <0x0 0x546c0000 0x0 0x00040000>;
 335                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 336                         status = "disabled";
 337                 };
 338         };
 339
 340         gic: interrupt-controller@50041000 {
 341                 compatible = "arm,gic-400";
 342                 #interrupt-cells = <3>;
 343                 interrupt-controller;
 344                 reg = <0x0 0x50041000 0x0 0x1000>,
 345                       <0x0 0x50042000 0x0 0x2000>,
 346                       <0x0 0x50044000 0x0 0x2000>,
 347                       <0x0 0x50046000 0x0 0x2000>;
 348                 interrupts = <GIC_PPI 9
 349                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 350                 interrupt-parent = <&gic>;
 351         };
 352
 353         gpu@57000000 {
 354                 compatible = "nvidia,gm20b";
 355                 reg = <0x0 0x57000000 0x0 0x01000000>,
 356                       <0x0 0x58000000 0x0 0x01000000>;
 357                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 358                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 359                 interrupt-names = "stall", "nonstall";
 360                 clocks = <&tegra_car TEGRA210_CLK_GPU>,
 361                          <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
 362                          <&tegra_car TEGRA210_CLK_PLL_G_REF>;
 363                 clock-names = "gpu", "pwr", "ref";
 364                 resets = <&tegra_car 184>;
 365                 reset-names = "gpu";
 366
 367                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 368
 369                 status = "disabled";
 370         };
 371
 372         lic: interrupt-controller@60004000 {
 373                 compatible = "nvidia,tegra210-ictlr";
 374                 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
 375                       <0x0 0x60004100 0x0 0x40>, /* secondary controller */
 376                       <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
 377                       <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
 378                       <0x0 0x60004400 0x0 0x40>, /* quinary controller */
 379                       <0x0 0x60004500 0x0 0x40>; /* senary controller */
 380                 interrupt-controller;
 381                 #interrupt-cells = <3>;
 382                 interrupt-parent = <&gic>;
 383         };
 384
 385         timer@60005000 {
 386                 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
 387                 reg = <0x0 0x60005000 0x0 0x400>;
 388                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 389                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 393                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
 395                 clock-names = "timer";
 396         };
 397
 398         tegra_car: clock@60006000 {
 399                 compatible = "nvidia,tegra210-car";
 400                 reg = <0x0 0x60006000 0x0 0x1000>;
 401                 #clock-cells = <1>;
 402                 #reset-cells = <1>;
 403         };
 404
 405         flow-controller@60007000 {
 406                 compatible = "nvidia,tegra210-flowctrl";
 407                 reg = <0x0 0x60007000 0x0 0x1000>;
 408         };
 409
 410         gpio: gpio@6000d000 {
 411                 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
 412                 reg = <0x0 0x6000d000 0x0 0x1000>;
 413                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 414                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 415                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 416                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 417                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 418                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 419                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 420                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 421                 #gpio-cells = <2>;
 422                 gpio-controller;
 423                 #interrupt-cells = <2>;
 424                 interrupt-controller;
 425         };
 426
 427         apbdma: dma@60020000 {
 428                 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
 429                 reg = <0x0 0x60020000 0x0 0x1400>;
 430                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 431                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 432                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 433                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 435                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 436                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 437                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 438                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 439                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 440                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 441                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 442                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 443                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 444                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 445                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 446                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 447                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 448                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 449                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 450                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 451                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 452                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 453                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 454                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 455                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 456                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 457                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 458                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 459                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 460                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 461                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
 463                 clock-names = "dma";
 464                 resets = <&tegra_car 34>;
 465                 reset-names = "dma";
 466                 #dma-cells = <1>;
 467         };
 468
 469         apbmisc@70000800 {
 470                 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
 471                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 472                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 473         };
 474
 475         pinmux: pinmux@700008d4 {
 476                 compatible = "nvidia,tegra210-pinmux";
 477                 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
 478                       <0x0 0x70003000 0x0 0x294>; /* Mux registers */
 479         };
 480
 481         /*
 482          * There are two serial driver i.e. 8250 based simple serial
 483          * driver and APB DMA based serial driver for higher baudrate
 484          * and performance. To enable the 8250 based driver, the compatible
 485          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 486          * the APB DMA based serial driver, the compatible is
 487          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 488          */
 489         uarta: serial@70006000 {
 490                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 491                 reg = <0x0 0x70006000 0x0 0x40>;
 492                 reg-shift = <2>;
 493                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 494                 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
 495                 clock-names = "serial";
 496                 resets = <&tegra_car 6>;
 497                 reset-names = "serial";
 498                 dmas = <&apbdma 8>, <&apbdma 8>;
 499                 dma-names = "rx", "tx";
 500                 status = "disabled";
 501         };
 502
 503         uartb: serial@70006040 {
 504                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 505                 reg = <0x0 0x70006040 0x0 0x40>;
 506                 reg-shift = <2>;
 507                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
 509                 clock-names = "serial";
 510                 resets = <&tegra_car 7>;
 511                 reset-names = "serial";
 512                 dmas = <&apbdma 9>, <&apbdma 9>;
 513                 dma-names = "rx", "tx";
 514                 status = "disabled";
 515         };
 516
 517         uartc: serial@70006200 {
 518                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 519                 reg = <0x0 0x70006200 0x0 0x40>;
 520                 reg-shift = <2>;
 521                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 522                 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
 523                 clock-names = "serial";
 524                 resets = <&tegra_car 55>;
 525                 reset-names = "serial";
 526                 dmas = <&apbdma 10>, <&apbdma 10>;
 527                 dma-names = "rx", "tx";
 528                 status = "disabled";
 529         };
 530
 531         uartd: serial@70006300 {
 532                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 533                 reg = <0x0 0x70006300 0x0 0x40>;
 534                 reg-shift = <2>;
 535                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
 537                 clock-names = "serial";
 538                 resets = <&tegra_car 65>;
 539                 reset-names = "serial";
 540                 dmas = <&apbdma 19>, <&apbdma 19>;
 541                 dma-names = "rx", "tx";
 542                 status = "disabled";
 543         };
 544
 545         pwm: pwm@7000a000 {
 546                 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
 547                 reg = <0x0 0x7000a000 0x0 0x100>;
 548                 #pwm-cells = <2>;
 549                 clocks = <&tegra_car TEGRA210_CLK_PWM>;
 550                 clock-names = "pwm";
 551                 resets = <&tegra_car 17>;
 552                 reset-names = "pwm";
 553                 status = "disabled";
 554         };
 555
 556         i2c@7000c000 {
 557                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 558                 reg = <0x0 0x7000c000 0x0 0x100>;
 559                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
 563                 clock-names = "div-clk";
 564                 resets = <&tegra_car 12>;
 565                 reset-names = "i2c";
 566                 dmas = <&apbdma 21>, <&apbdma 21>;
 567                 dma-names = "rx", "tx";
 568                 status = "disabled";
 569         };
 570
 571         i2c@7000c400 {
 572                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 573                 reg = <0x0 0x7000c400 0x0 0x100>;
 574                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
 578                 clock-names = "div-clk";
 579                 resets = <&tegra_car 54>;
 580                 reset-names = "i2c";
 581                 dmas = <&apbdma 22>, <&apbdma 22>;
 582                 dma-names = "rx", "tx";
 583                 status = "disabled";
 584         };
 585
 586         i2c@7000c500 {
 587                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 588                 reg = <0x0 0x7000c500 0x0 0x100>;
 589                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
 593                 clock-names = "div-clk";
 594                 resets = <&tegra_car 67>;
 595                 reset-names = "i2c";
 596                 dmas = <&apbdma 23>, <&apbdma 23>;
 597                 dma-names = "rx", "tx";
 598                 status = "disabled";
 599         };
 600
 601         i2c@7000c700 {
 602                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 603                 reg = <0x0 0x7000c700 0x0 0x100>;
 604                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 605                 #address-cells = <1>;
 606                 #size-cells = <0>;
 607                 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
 608                 clock-names = "div-clk";
 609                 resets = <&tegra_car 103>;
 610                 reset-names = "i2c";
 611                 dmas = <&apbdma 26>, <&apbdma 26>;
 612                 dma-names = "rx", "tx";
 613                 pinctrl-0 = <&state_dpaux1_i2c>;
 614                 pinctrl-1 = <&state_dpaux1_off>;
 615                 pinctrl-names = "default", "idle";
 616                 status = "disabled";
 617         };
 618
 619         i2c@7000d000 {
 620                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 621                 reg = <0x0 0x7000d000 0x0 0x100>;
 622                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
 626                 clock-names = "div-clk";
 627                 resets = <&tegra_car 47>;
 628                 reset-names = "i2c";
 629                 dmas = <&apbdma 24>, <&apbdma 24>;
 630                 dma-names = "rx", "tx";
 631                 status = "disabled";
 632         };
 633
 634         i2c@7000d100 {
 635                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 636                 reg = <0x0 0x7000d100 0x0 0x100>;
 637                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 638                 #address-cells = <1>;
 639                 #size-cells = <0>;
 640                 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
 641                 clock-names = "div-clk";
 642                 resets = <&tegra_car 166>;
 643                 reset-names = "i2c";
 644                 dmas = <&apbdma 30>, <&apbdma 30>;
 645                 dma-names = "rx", "tx";
 646                 pinctrl-0 = <&state_dpaux_i2c>;
 647                 pinctrl-1 = <&state_dpaux_off>;
 648                 pinctrl-names = "default", "idle";
 649                 status = "disabled";
 650         };
 651
 652         spi@7000d400 {
 653                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 654                 reg = <0x0 0x7000d400 0x0 0x200>;
 655                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
 659                 clock-names = "spi";
 660                 resets = <&tegra_car 41>;
 661                 reset-names = "spi";
 662                 dmas = <&apbdma 15>, <&apbdma 15>;
 663                 dma-names = "rx", "tx";
 664                 status = "disabled";
 665         };
 666
 667         spi@7000d600 {
 668                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 669                 reg = <0x0 0x7000d600 0x0 0x200>;
 670                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
 674                 clock-names = "spi";
 675                 resets = <&tegra_car 44>;
 676                 reset-names = "spi";
 677                 dmas = <&apbdma 16>, <&apbdma 16>;
 678                 dma-names = "rx", "tx";
 679                 status = "disabled";
 680         };
 681
 682         spi@7000d800 {
 683                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 684                 reg = <0x0 0x7000d800 0x0 0x200>;
 685                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
 689                 clock-names = "spi";
 690                 resets = <&tegra_car 46>;
 691                 reset-names = "spi";
 692                 dmas = <&apbdma 17>, <&apbdma 17>;
 693                 dma-names = "rx", "tx";
 694                 status = "disabled";
 695         };
 696
 697         spi@7000da00 {
 698                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 699                 reg = <0x0 0x7000da00 0x0 0x200>;
 700                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
 704                 clock-names = "spi";
 705                 resets = <&tegra_car 68>;
 706                 reset-names = "spi";
 707                 dmas = <&apbdma 18>, <&apbdma 18>;
 708                 dma-names = "rx", "tx";
 709                 status = "disabled";
 710         };
 711
 712         rtc@7000e000 {
 713                 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
 714                 reg = <0x0 0x7000e000 0x0 0x100>;
 715                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 716                 clocks = <&tegra_car TEGRA210_CLK_RTC>;
 717                 clock-names = "rtc";
 718         };
 719
 720         pmc: pmc@7000e400 {
 721                 compatible = "nvidia,tegra210-pmc";
 722                 reg = <0x0 0x7000e400 0x0 0x400>;
 723                 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 724                 clock-names = "pclk", "clk32k_in";
 725
 726                 powergates {
 727                         pd_audio: aud {
 728                                 clocks = <&tegra_car TEGRA210_CLK_APE>,
 729                                          <&tegra_car TEGRA210_CLK_APB2APE>;
 730                                 resets = <&tegra_car 198>;
 731                                 #power-domain-cells = <0>;
 732                         };
 733
 734                         pd_sor: sor {
 735                                 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 736                                          <&tegra_car TEGRA210_CLK_SOR1>,
 737                                          <&tegra_car TEGRA210_CLK_CSI>,
 738                                          <&tegra_car TEGRA210_CLK_DSIA>,
 739                                          <&tegra_car TEGRA210_CLK_DSIB>,
 740                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 741                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 742                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 743                                 resets = <&tegra_car TEGRA210_CLK_SOR0>,
 744                                          <&tegra_car TEGRA210_CLK_SOR1>,
 745                                          <&tegra_car TEGRA210_CLK_CSI>,
 746                                          <&tegra_car TEGRA210_CLK_DSIA>,
 747                                          <&tegra_car TEGRA210_CLK_DSIB>,
 748                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 749                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 750                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 751                                 #power-domain-cells = <0>;
 752                         };
 753
 754                         pd_xusbss: xusba {
 755                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 756                                 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 757                                 #power-domain-cells = <0>;
 758                         };
 759
 760                         pd_xusbdev: xusbb {
 761                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
 762                                 resets = <&tegra_car 95>;
 763                                 #power-domain-cells = <0>;
 764                         };
 765
 766                         pd_xusbhost: xusbc {
 767                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 768                                 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 769                                 #power-domain-cells = <0>;
 770                         };
 771
 772                         pd_vic: vic {
 773                                 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 774                                 clock-names = "vic";
 775                                 resets = <&tegra_car 178>;
 776                                 reset-names = "vic";
 777                                 #power-domain-cells = <0>;
 778                         };
 779                 };
 780
 781                 sdmmc1_3v3: sdmmc1-3v3 {
 782                         pins = "sdmmc1";
 783                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 784                 };
 785
 786                 sdmmc1_1v8: sdmmc1-1v8 {
 787                         pins = "sdmmc1";
 788                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 789                 };
 790
 791                 sdmmc3_3v3: sdmmc3-3v3 {
 792                         pins = "sdmmc3";
 793                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 794                 };
 795
 796                 sdmmc3_1v8: sdmmc3-1v8 {
 797                         pins = "sdmmc3";
 798                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 799                 };
 800         };
 801
 802         fuse@7000f800 {
 803                 compatible = "nvidia,tegra210-efuse";
 804                 reg = <0x0 0x7000f800 0x0 0x400>;
 805                 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
 806                 clock-names = "fuse";
 807                 resets = <&tegra_car 39>;
 808                 reset-names = "fuse";
 809         };
 810
 811         mc: memory-controller@70019000 {
 812                 compatible = "nvidia,tegra210-mc";
 813                 reg = <0x0 0x70019000 0x0 0x1000>;
 814                 clocks = <&tegra_car TEGRA210_CLK_MC>;
 815                 clock-names = "mc";
 816
 817                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 818
 819                 #iommu-cells = <1>;
 820         };
 821
 822         sata@70020000 {
 823                 compatible = "nvidia,tegra210-ahci";
 824                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 825                       <0x0 0x70020000 0x0 0x7000>, /* SATA */
 826                       <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
 827                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 828                 clocks = <&tegra_car TEGRA210_CLK_SATA>,
 829                          <&tegra_car TEGRA210_CLK_SATA_OOB>;
 830                 clock-names = "sata", "sata-oob";
 831                 resets = <&tegra_car 124>,
 832                          <&tegra_car 123>,
 833                          <&tegra_car 129>;
 834                 reset-names = "sata", "sata-oob", "sata-cold";
 835                 status = "disabled";
 836         };
 837
 838         hda@70030000 {
 839                 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
 840                 reg = <0x0 0x70030000 0x0 0x10000>;
 841                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 842                 clocks = <&tegra_car TEGRA210_CLK_HDA>,
 843                          <&tegra_car TEGRA210_CLK_HDA2HDMI>,
 844                          <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
 845                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 846                 resets = <&tegra_car 125>, /* hda */
 847                          <&tegra_car 128>, /* hda2hdmi */
 848                          <&tegra_car 111>; /* hda2codec_2x */
 849                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 850                 status = "disabled";
 851         };
 852
 853         usb@70090000 {
 854                 compatible = "nvidia,tegra210-xusb";
 855                 reg = <0x0 0x70090000 0x0 0x8000>,
 856                       <0x0 0x70098000 0x0 0x1000>,
 857                       <0x0 0x70099000 0x0 0x1000>;
 858                 reg-names = "hcd", "fpci", "ipfs";
 859
 860                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 861                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 862
 863                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
 864                          <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
 865                          <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
 866                          <&tegra_car TEGRA210_CLK_XUSB_SS>,
 867                          <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
 868                          <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
 869                          <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
 870                          <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
 871                          <&tegra_car TEGRA210_CLK_PLL_U_480M>,
 872                          <&tegra_car TEGRA210_CLK_CLK_M>,
 873                          <&tegra_car TEGRA210_CLK_PLL_E>;
 874                 clock-names = "xusb_host", "xusb_host_src",
 875                               "xusb_falcon_src", "xusb_ss",
 876                               "xusb_ss_div2", "xusb_ss_src",
 877                               "xusb_hs_src", "xusb_fs_src",
 878                               "pll_u_480m", "clk_m", "pll_e";
 879                 resets = <&tegra_car 89>, <&tegra_car 156>,
 880                          <&tegra_car 143>;
 881                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 882
 883                 nvidia,xusb-padctl = <&padctl>;
 884
 885                 status = "disabled";
 886         };
 887
 888         padctl: padctl@7009f000 {
 889                 compatible = "nvidia,tegra210-xusb-padctl";
 890                 reg = <0x0 0x7009f000 0x0 0x1000>;
 891                 resets = <&tegra_car 142>;
 892                 reset-names = "padctl";
 893
 894                 status = "disabled";
 895
 896                 pads {
 897                         usb2 {
 898                                 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
 899                                 clock-names = "trk";
 900                                 status = "disabled";
 901
 902                                 lanes {
 903                                         usb2-0 {
 904                                                 status = "disabled";
 905                                                 #phy-cells = <0>;
 906                                         };
 907
 908                                         usb2-1 {
 909                                                 status = "disabled";
 910                                                 #phy-cells = <0>;
 911                                         };
 912
 913                                         usb2-2 {
 914                                                 status = "disabled";
 915                                                 #phy-cells = <0>;
 916                                         };
 917
 918                                         usb2-3 {
 919                                                 status = "disabled";
 920                                                 #phy-cells = <0>;
 921                                         };
 922                                 };
 923                         };
 924
 925                         hsic {
 926                                 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
 927                                 clock-names = "trk";
 928                                 status = "disabled";
 929
 930                                 lanes {
 931                                         hsic-0 {
 932                                                 status = "disabled";
 933                                                 #phy-cells = <0>;
 934                                         };
 935
 936                                         hsic-1 {
 937                                                 status = "disabled";
 938                                                 #phy-cells = <0>;
 939                                         };
 940                                 };
 941                         };
 942
 943                         pcie {
 944                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 945                                 clock-names = "pll";
 946                                 resets = <&tegra_car 205>;
 947                                 reset-names = "phy";
 948                                 status = "disabled";
 949
 950                                 lanes {
 951                                         pcie-0 {
 952                                                 status = "disabled";
 953                                                 #phy-cells = <0>;
 954                                         };
 955
 956                                         pcie-1 {
 957                                                 status = "disabled";
 958                                                 #phy-cells = <0>;
 959                                         };
 960
 961                                         pcie-2 {
 962                                                 status = "disabled";
 963                                                 #phy-cells = <0>;
 964                                         };
 965
 966                                         pcie-3 {
 967                                                 status = "disabled";
 968                                                 #phy-cells = <0>;
 969                                         };
 970
 971                                         pcie-4 {
 972                                                 status = "disabled";
 973                                                 #phy-cells = <0>;
 974                                         };
 975
 976                                         pcie-5 {
 977                                                 status = "disabled";
 978                                                 #phy-cells = <0>;
 979                                         };
 980
 981                                         pcie-6 {
 982                                                 status = "disabled";
 983                                                 #phy-cells = <0>;
 984                                         };
 985                                 };
 986                         };
 987
 988                         sata {
 989                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 990                                 clock-names = "pll";
 991                                 resets = <&tegra_car 204>;
 992                                 reset-names = "phy";
 993                                 status = "disabled";
 994
 995                                 lanes {
 996                                         sata-0 {
 997                                                 status = "disabled";
 998                                                 #phy-cells = <0>;
 999                                         };
1000                                 };
1001                         };
1002                 };
1003
1004                 ports {
1005                         usb2-0 {
1006                                 status = "disabled";
1007                         };
1008
1009                         usb2-1 {
1010                                 status = "disabled";
1011                         };
1012
1013                         usb2-2 {
1014                                 status = "disabled";
1015                         };
1016
1017                         usb2-3 {
1018                                 status = "disabled";
1019                         };
1020
1021                         hsic-0 {
1022                                 status = "disabled";
1023                         };
1024
1025                         usb3-0 {
1026                                 status = "disabled";
1027                         };
1028
1029                         usb3-1 {
1030                                 status = "disabled";
1031                         };
1032
1033                         usb3-2 {
1034                                 status = "disabled";
1035                         };
1036
1037                         usb3-3 {
1038                                 status = "disabled";
1039                         };
1040                 };
1041         };
1042
1043         sdhci@700b0000 {
1044                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1045                 reg = <0x0 0x700b0000 0x0 0x200>;
1046                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1047                 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1048                 clock-names = "sdhci";
1049                 resets = <&tegra_car 14>;
1050                 reset-names = "sdhci";
1051                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1052                 pinctrl-0 = <&sdmmc1_3v3>;
1053                 pinctrl-1 = <&sdmmc1_1v8>;
1054                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1055                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1056                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1057                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1058                 nvidia,default-tap = <0x2>;
1059                 nvidia,default-trim = <0x4>;
1060                 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1061                                   <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1062                                   <&tegra_car TEGRA210_CLK_PLL_C4>;
1063                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1064                 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1065                 status = "disabled";
1066         };
1067
1068         sdhci@700b0200 {
1069                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1070                 reg = <0x0 0x700b0200 0x0 0x200>;
1071                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1072                 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1073                 clock-names = "sdhci";
1074                 resets = <&tegra_car 9>;
1075                 reset-names = "sdhci";
1076                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1077                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1078                 nvidia,default-tap = <0x8>;
1079                 nvidia,default-trim = <0x0>;
1080                 status = "disabled";
1081         };
1082
1083         sdhci@700b0400 {
1084                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1085                 reg = <0x0 0x700b0400 0x0 0x200>;
1086                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1087                 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1088                 clock-names = "sdhci";
1089                 resets = <&tegra_car 69>;
1090                 reset-names = "sdhci";
1091                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1092                 pinctrl-0 = <&sdmmc3_3v3>;
1093                 pinctrl-1 = <&sdmmc3_1v8>;
1094                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1095                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1096                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1097                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1098                 nvidia,default-tap = <0x3>;
1099                 nvidia,default-trim = <0x3>;
1100                 status = "disabled";
1101         };
1102
1103         sdhci@700b0600 {
1104                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1105                 reg = <0x0 0x700b0600 0x0 0x200>;
1106                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1107                 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1108                 clock-names = "sdhci";
1109                 resets = <&tegra_car 15>;
1110                 reset-names = "sdhci";
1111                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1112                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1113                 nvidia,default-tap = <0x8>;
1114                 nvidia,default-trim = <0x0>;
1115                 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1116                                   <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1117                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1118                 nvidia,dqs-trim = <40>;
1119                 mmc-hs400-1_8v;
1120                 status = "disabled";
1121         };
1122
1123         mipi: mipi@700e3000 {
1124                 compatible = "nvidia,tegra210-mipi";
1125                 reg = <0x0 0x700e3000 0x0 0x100>;
1126                 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1127                 clock-names = "mipi-cal";
1128                 power-domains = <&pd_sor>;
1129                 #nvidia,mipi-calibrate-cells = <1>;
1130         };
1131
1132         aconnect@702c0000 {
1133                 compatible = "nvidia,tegra210-aconnect";
1134                 clocks = <&tegra_car TEGRA210_CLK_APE>,
1135                          <&tegra_car TEGRA210_CLK_APB2APE>;
1136                 clock-names = "ape", "apb2ape";
1137                 power-domains = <&pd_audio>;
1138                 #address-cells = <1>;
1139                 #size-cells = <1>;
1140                 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1141                 status = "disabled";
1142
1143                 adma: dma@702e2000 {
1144                         compatible = "nvidia,tegra210-adma";
1145                         reg = <0x702e2000 0x2000>;
1146                         interrupt-parent = <&agic>;
1147                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1148                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1149                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1150                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1151                                      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1152                                      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1153                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1154                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1155                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1156                                      <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1157                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1158                                      <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1159                                      <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1160                                      <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1161                                      <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1162                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1163                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1164                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1165                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1166                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1167                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1168                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1169                         #dma-cells = <1>;
1170                         clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1171                         clock-names = "d_audio";
1172                         status = "disabled";
1173                 };
1174
1175                 agic: agic@702f9000 {
1176                         compatible = "nvidia,tegra210-agic";
1177                         #interrupt-cells = <3>;
1178                         interrupt-controller;
1179                         reg = <0x702f9000 0x2000>,
1180                               <0x702fa000 0x2000>;
1181                         interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1182                         clocks = <&tegra_car TEGRA210_CLK_APE>;
1183                         clock-names = "clk";
1184                         status = "disabled";
1185                 };
1186         };
1187
1188         spi@70410000 {
1189                 compatible = "nvidia,tegra210-qspi";
1190                 reg = <0x0 0x70410000 0x0 0x1000>;
1191                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1192                 #address-cells = <1>;
1193                 #size-cells = <0>;
1194                 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1195                 clock-names = "qspi";
1196                 resets = <&tegra_car 211>;
1197                 reset-names = "qspi";
1198                 dmas = <&apbdma 5>, <&apbdma 5>;
1199                 dma-names = "rx", "tx";
1200                 status = "disabled";
1201         };
1202
1203         usb@7d000000 {
1204                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1205                 reg = <0x0 0x7d000000 0x0 0x4000>;
1206                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1207                 phy_type = "utmi";
1208                 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1209                 clock-names = "usb";
1210                 resets = <&tegra_car 22>;
1211                 reset-names = "usb";
1212                 nvidia,phy = <&phy1>;
1213                 status = "disabled";
1214         };
1215
1216         phy1: usb-phy@7d000000 {
1217                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1218                 reg = <0x0 0x7d000000 0x0 0x4000>,
1219                       <0x0 0x7d000000 0x0 0x4000>;
1220                 phy_type = "utmi";
1221                 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1222                          <&tegra_car TEGRA210_CLK_PLL_U>,
1223                          <&tegra_car TEGRA210_CLK_USBD>;
1224                 clock-names = "reg", "pll_u", "utmi-pads";
1225                 resets = <&tegra_car 22>, <&tegra_car 22>;
1226                 reset-names = "usb", "utmi-pads";
1227                 nvidia,hssync-start-delay = <0>;
1228                 nvidia,idle-wait-delay = <17>;
1229                 nvidia,elastic-limit = <16>;
1230                 nvidia,term-range-adj = <6>;
1231                 nvidia,xcvr-setup = <9>;
1232                 nvidia,xcvr-lsfslew = <0>;
1233                 nvidia,xcvr-lsrslew = <3>;
1234                 nvidia,hssquelch-level = <2>;
1235                 nvidia,hsdiscon-level = <5>;
1236                 nvidia,xcvr-hsslew = <12>;
1237                 nvidia,has-utmi-pad-registers;
1238                 status = "disabled";
1239         };
1240
1241         usb@7d004000 {
1242                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1243                 reg = <0x0 0x7d004000 0x0 0x4000>;
1244                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1245                 phy_type = "utmi";
1246                 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1247                 clock-names = "usb";
1248                 resets = <&tegra_car 58>;
1249                 reset-names = "usb";
1250                 nvidia,phy = <&phy2>;
1251                 status = "disabled";
1252         };
1253
1254         phy2: usb-phy@7d004000 {
1255                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1256                 reg = <0x0 0x7d004000 0x0 0x4000>,
1257                       <0x0 0x7d000000 0x0 0x4000>;
1258                 phy_type = "utmi";
1259                 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1260                          <&tegra_car TEGRA210_CLK_PLL_U>,
1261                          <&tegra_car TEGRA210_CLK_USBD>;
1262                 clock-names = "reg", "pll_u", "utmi-pads";
1263                 resets = <&tegra_car 58>, <&tegra_car 22>;
1264                 reset-names = "usb", "utmi-pads";
1265                 nvidia,hssync-start-delay = <0>;
1266                 nvidia,idle-wait-delay = <17>;
1267                 nvidia,elastic-limit = <16>;
1268                 nvidia,term-range-adj = <6>;
1269                 nvidia,xcvr-setup = <9>;
1270                 nvidia,xcvr-lsfslew = <0>;
1271                 nvidia,xcvr-lsrslew = <3>;
1272                 nvidia,hssquelch-level = <2>;
1273                 nvidia,hsdiscon-level = <5>;
1274                 nvidia,xcvr-hsslew = <12>;
1275                 status = "disabled";
1276         };
1277
1278         cpus {
1279                 #address-cells = <1>;
1280                 #size-cells = <0>;
1281
1282                 cpu@0 {
1283                         device_type = "cpu";
1284                         compatible = "arm,cortex-a57";
1285                         reg = <0>;
1286                 };
1287
1288                 cpu@1 {
1289                         device_type = "cpu";
1290                         compatible = "arm,cortex-a57";
1291                         reg = <1>;
1292                 };
1293
1294                 cpu@2 {
1295                         device_type = "cpu";
1296                         compatible = "arm,cortex-a57";
1297                         reg = <2>;
1298                 };
1299
1300                 cpu@3 {
1301                         device_type = "cpu";
1302                         compatible = "arm,cortex-a57";
1303                         reg = <3>;
1304                 };
1305         };
1306
1307         timer {
1308                 compatible = "arm,armv8-timer";
1309                 interrupts = <GIC_PPI 13
1310                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1311                              <GIC_PPI 14
1312                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1313                              <GIC_PPI 11
1314                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1315                              <GIC_PPI 10
1316                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1317                 interrupt-parent = <&gic>;
1318         };
1319
1320         soctherm: thermal-sensor@700e2000 {
1321                 compatible = "nvidia,tegra210-soctherm";
1322                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1323                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1324                 reg-names = "soctherm-reg", "car-reg";
1325                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1326                 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1327                         <&tegra_car TEGRA210_CLK_SOC_THERM>;
1328                 clock-names = "tsensor", "soctherm";
1329                 resets = <&tegra_car 78>;
1330                 reset-names = "soctherm";
1331                 #thermal-sensor-cells = <1>;
1332
1333                 throttle-cfgs {
1334                         throttle_heavy: heavy {
1335                                 nvidia,priority = <100>;
1336                                 nvidia,cpu-throt-percent = <85>;
1337
1338                                 #cooling-cells = <2>;
1339                         };
1340                 };
1341         };
1342
1343         thermal-zones {
1344                 cpu {
1345                         polling-delay-passive = <1000>;
1346                         polling-delay = <0>;
1347
1348                         thermal-sensors =
1349                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1350
1351                         trips {
1352                                 cpu-shutdown-trip {
1353                                         temperature = <102500>;
1354                                         hysteresis = <0>;
1355                                         type = "critical";
1356                                 };
1357
1358                                 cpu_throttle_trip: throttle-trip {
1359                                         temperature = <98500>;
1360                                         hysteresis = <1000>;
1361                                         type = "hot";
1362                                 };
1363                         };
1364
1365                         cooling-maps {
1366                                 map0 {
1367                                         trip = <&cpu_throttle_trip>;
1368                                         cooling-device = <&throttle_heavy 1 1>;
1369                                 };
1370                         };
1371                 };
1372                 mem {
1373                         polling-delay-passive = <0>;
1374                         polling-delay = <0>;
1375
1376                         thermal-sensors =
1377                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1378
1379                         trips {
1380                                 mem-shutdown-trip {
1381                                         temperature = <103000>;
1382                                         hysteresis = <0>;
1383                                         type = "critical";
1384                                 };
1385                         };
1386
1387                         cooling-maps {
1388                                 /*
1389                                  * There are currently no cooling maps,
1390                                  * because there are no cooling devices.
1391                                  */
1392                         };
1393                 };
1394                 gpu {
1395                         polling-delay-passive = <1000>;
1396                         polling-delay = <0>;
1397
1398                         thermal-sensors =
1399                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1400
1401                         trips {
1402                                 gpu-shutdown-trip {
1403                                         temperature = <103000>;
1404                                         hysteresis = <0>;
1405                                         type = "critical";
1406                                 };
1407
1408                                 gpu_throttle_trip: throttle-trip {
1409                                         temperature = <100000>;
1410                                         hysteresis = <1000>;
1411                                         type = "hot";
1412                                 };
1413                         };
1414
1415                         cooling-maps {
1416                                 map0 {
1417                                         trip = <&gpu_throttle_trip>;
1418                                         cooling-device = <&throttle_heavy 1 1>;
1419                                 };
1420                         };
1421                 };
1422                 pllx {
1423                         polling-delay-passive = <0>;
1424                         polling-delay = <0>;
1425
1426                         thermal-sensors =
1427                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1428
1429                         trips {
1430                                 pllx-shutdown-trip {
1431                                         temperature = <103000>;
1432                                         hysteresis = <0>;
1433                                         type = "critical";
1434                                 };
1435                         };
1436
1437                         cooling-maps {
1438                                 /*
1439                                  * There are currently no cooling maps,
1440                                  * because there are no cooling devices.
1441                                  */
1442                         };
1443                 };
1444         };
1445 };