arch/arm64/boot/dts/nvidia/tegra210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra210-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra210-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/thermal/tegra124-soctherm.h>
   8
   9 / {
  10         compatible = "nvidia,tegra210";
  11         interrupt-parent = <&lic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         pcie@1003000 {
  16                 compatible = "nvidia,tegra210-pcie";
  17                 device_type = "pci";
  18                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  19                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  20                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  21                 reg-names = "pads", "afi", "cs";
  22                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  23                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  24                 interrupt-names = "intr", "msi";
  25
  26                 #interrupt-cells = <1>;
  27                 interrupt-map-mask = <0 0 0 0>;
  28                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  29
  30                 bus-range = <0x00 0xff>;
  31                 #address-cells = <3>;
  32                 #size-cells = <2>;
  33
  34                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  35                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  36                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  37                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  38                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  39
  40                 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
  41                          <&tegra_car TEGRA210_CLK_AFI>,
  42                          <&tegra_car TEGRA210_CLK_PLL_E>,
  43                          <&tegra_car TEGRA210_CLK_CML0>;
  44                 clock-names = "pex", "afi", "pll_e", "cml";
  45                 resets = <&tegra_car 70>,
  46                          <&tegra_car 72>,
  47                          <&tegra_car 74>;
  48                 reset-names = "pex", "afi", "pcie_x";
  49                 status = "disabled";
  50
  51                 pci@1,0 {
  52                         device_type = "pci";
  53                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  54                         reg = <0x000800 0 0 0 0>;
  55                         bus-range = <0x00 0xff>;
  56                         status = "disabled";
  57
  58                         #address-cells = <3>;
  59                         #size-cells = <2>;
  60                         ranges;
  61
  62                         nvidia,num-lanes = <4>;
  63                 };
  64
  65                 pci@2,0 {
  66                         device_type = "pci";
  67                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  68                         reg = <0x001000 0 0 0 0>;
  69                         bus-range = <0x00 0xff>;
  70                         status = "disabled";
  71
  72                         #address-cells = <3>;
  73                         #size-cells = <2>;
  74                         ranges;
  75
  76                         nvidia,num-lanes = <1>;
  77                 };
  78         };
  79
  80         host1x@50000000 {
  81                 compatible = "nvidia,tegra210-host1x", "simple-bus";
  82                 reg = <0x0 0x50000000 0x0 0x00034000>;
  83                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  84                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  85                 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
  86                 clock-names = "host1x";
  87                 resets = <&tegra_car 28>;
  88                 reset-names = "host1x";
  89
  90                 #address-cells = <2>;
  91                 #size-cells = <2>;
  92
  93                 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
  94
  95                 iommus = <&mc TEGRA_SWGROUP_HC>;
  96
  97                 dpaux1: dpaux@54040000 {
  98                         compatible = "nvidia,tegra210-dpaux";
  99                         reg = <0x0 0x54040000 0x0 0x00040000>;
 100                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 101                         clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
 102                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 103                         clock-names = "dpaux", "parent";
 104                         resets = <&tegra_car 207>;
 105                         reset-names = "dpaux";
 106                         power-domains = <&pd_sor>;
 107                         status = "disabled";
 108
 109                         state_dpaux1_aux: pinmux-aux {
 110                                 groups = "dpaux-io";
 111                                 function = "aux";
 112                         };
 113
 114                         state_dpaux1_i2c: pinmux-i2c {
 115                                 groups = "dpaux-io";
 116                                 function = "i2c";
 117                         };
 118
 119                         state_dpaux1_off: pinmux-off {
 120                                 groups = "dpaux-io";
 121                                 function = "off";
 122                         };
 123
 124                         i2c-bus {
 125                                 #address-cells = <1>;
 126                                 #size-cells = <0>;
 127                         };
 128                 };
 129
 130                 vi@54080000 {
 131                         compatible = "nvidia,tegra210-vi";
 132                         reg = <0x0 0x54080000 0x0 0x00040000>;
 133                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 134                         status = "disabled";
 135                 };
 136
 137                 tsec@54100000 {
 138                         compatible = "nvidia,tegra210-tsec";
 139                         reg = <0x0 0x54100000 0x0 0x00040000>;
 140                 };
 141
 142                 dc@54200000 {
 143                         compatible = "nvidia,tegra210-dc";
 144                         reg = <0x0 0x54200000 0x0 0x00040000>;
 145                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 146                         clocks = <&tegra_car TEGRA210_CLK_DISP1>,
 147                                  <&tegra_car TEGRA210_CLK_PLL_P>;
 148                         clock-names = "dc", "parent";
 149                         resets = <&tegra_car 27>;
 150                         reset-names = "dc";
 151
 152                         iommus = <&mc TEGRA_SWGROUP_DC>;
 153
 154                         nvidia,head = <0>;
 155                 };
 156
 157                 dc@54240000 {
 158                         compatible = "nvidia,tegra210-dc";
 159                         reg = <0x0 0x54240000 0x0 0x00040000>;
 160                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 161                         clocks = <&tegra_car TEGRA210_CLK_DISP2>,
 162                                  <&tegra_car TEGRA210_CLK_PLL_P>;
 163                         clock-names = "dc", "parent";
 164                         resets = <&tegra_car 26>;
 165                         reset-names = "dc";
 166
 167                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 168
 169                         nvidia,head = <1>;
 170                 };
 171
 172                 dsi@54300000 {
 173                         compatible = "nvidia,tegra210-dsi";
 174                         reg = <0x0 0x54300000 0x0 0x00040000>;
 175                         clocks = <&tegra_car TEGRA210_CLK_DSIA>,
 176                                  <&tegra_car TEGRA210_CLK_DSIALP>,
 177                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 178                         clock-names = "dsi", "lp", "parent";
 179                         resets = <&tegra_car 48>;
 180                         reset-names = "dsi";
 181                         power-domains = <&pd_sor>;
 182                         nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
 183
 184                         status = "disabled";
 185
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                 };
 189
 190                 vic@54340000 {
 191                         compatible = "nvidia,tegra210-vic";
 192                         reg = <0x0 0x54340000 0x0 0x00040000>;
 193                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 195                         clock-names = "vic";
 196                         resets = <&tegra_car 178>;
 197                         reset-names = "vic";
 198
 199                         iommus = <&mc TEGRA_SWGROUP_VIC>;
 200                         power-domains = <&pd_vic>;
 201                 };
 202
 203                 nvjpg@54380000 {
 204                         compatible = "nvidia,tegra210-nvjpg";
 205                         reg = <0x0 0x54380000 0x0 0x00040000>;
 206                         status = "disabled";
 207                 };
 208
 209                 dsi@54400000 {
 210                         compatible = "nvidia,tegra210-dsi";
 211                         reg = <0x0 0x54400000 0x0 0x00040000>;
 212                         clocks = <&tegra_car TEGRA210_CLK_DSIB>,
 213                                  <&tegra_car TEGRA210_CLK_DSIBLP>,
 214                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 215                         clock-names = "dsi", "lp", "parent";
 216                         resets = <&tegra_car 82>;
 217                         reset-names = "dsi";
 218                         power-domains = <&pd_sor>;
 219                         nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
 220
 221                         status = "disabled";
 222
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                 };
 226
 227                 nvdec@54480000 {
 228                         compatible = "nvidia,tegra210-nvdec";
 229                         reg = <0x0 0x54480000 0x0 0x00040000>;
 230                         status = "disabled";
 231                 };
 232
 233                 nvenc@544c0000 {
 234                         compatible = "nvidia,tegra210-nvenc";
 235                         reg = <0x0 0x544c0000 0x0 0x00040000>;
 236                         status = "disabled";
 237                 };
 238
 239                 tsec@54500000 {
 240                         compatible = "nvidia,tegra210-tsec";
 241                         reg = <0x0 0x54500000 0x0 0x00040000>;
 242                         status = "disabled";
 243                 };
 244
 245                 sor@54540000 {
 246                         compatible = "nvidia,tegra210-sor";
 247                         reg = <0x0 0x54540000 0x0 0x00040000>;
 248                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 249                         clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 250                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
 251                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 252                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 253                         clock-names = "sor", "parent", "dp", "safe";
 254                         resets = <&tegra_car 182>;
 255                         reset-names = "sor";
 256                         pinctrl-0 = <&state_dpaux_aux>;
 257                         pinctrl-1 = <&state_dpaux_i2c>;
 258                         pinctrl-2 = <&state_dpaux_off>;
 259                         pinctrl-names = "aux", "i2c", "off";
 260                         power-domains = <&pd_sor>;
 261                         status = "disabled";
 262                 };
 263
 264                 sor@54580000 {
 265                         compatible = "nvidia,tegra210-sor1";
 266                         reg = <0x0 0x54580000 0x0 0x00040000>;
 267                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&tegra_car TEGRA210_CLK_SOR1>,
 269                                  <&tegra_car TEGRA210_CLK_SOR1_SRC>,
 270                                  <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
 271                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 272                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 273                         clock-names = "sor", "source", "parent", "dp", "safe";
 274                         resets = <&tegra_car 183>;
 275                         reset-names = "sor";
 276                         pinctrl-0 = <&state_dpaux1_aux>;
 277                         pinctrl-1 = <&state_dpaux1_i2c>;
 278                         pinctrl-2 = <&state_dpaux1_off>;
 279                         pinctrl-names = "aux", "i2c", "off";
 280                         power-domains = <&pd_sor>;
 281                         status = "disabled";
 282                 };
 283
 284                 dpaux: dpaux@545c0000 {
 285                         compatible = "nvidia,tegra124-dpaux";
 286                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 287                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
 289                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 290                         clock-names = "dpaux", "parent";
 291                         resets = <&tegra_car 181>;
 292                         reset-names = "dpaux";
 293                         power-domains = <&pd_sor>;
 294                         status = "disabled";
 295
 296                         state_dpaux_aux: pinmux-aux {
 297                                 groups = "dpaux-io";
 298                                 function = "aux";
 299                         };
 300
 301                         state_dpaux_i2c: pinmux-i2c {
 302                                 groups = "dpaux-io";
 303                                 function = "i2c";
 304                         };
 305
 306                         state_dpaux_off: pinmux-off {
 307                                 groups = "dpaux-io";
 308                                 function = "off";
 309                         };
 310
 311                         i2c-bus {
 312                                 #address-cells = <1>;
 313                                 #size-cells = <0>;
 314                         };
 315                 };
 316
 317                 isp@54600000 {
 318                         compatible = "nvidia,tegra210-isp";
 319                         reg = <0x0 0x54600000 0x0 0x00040000>;
 320                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 321                         status = "disabled";
 322                 };
 323
 324                 isp@54680000 {
 325                         compatible = "nvidia,tegra210-isp";
 326                         reg = <0x0 0x54680000 0x0 0x00040000>;
 327                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 328                         status = "disabled";
 329                 };
 330
 331                 i2c@546c0000 {
 332                         compatible = "nvidia,tegra210-i2c-vi";
 333                         reg = <0x0 0x546c0000 0x0 0x00040000>;
 334                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 335                         status = "disabled";
 336                 };
 337         };
 338
 339         gic: interrupt-controller@50041000 {
 340                 compatible = "arm,gic-400";
 341                 #interrupt-cells = <3>;
 342                 interrupt-controller;
 343                 reg = <0x0 0x50041000 0x0 0x1000>,
 344                       <0x0 0x50042000 0x0 0x2000>,
 345                       <0x0 0x50044000 0x0 0x2000>,
 346                       <0x0 0x50046000 0x0 0x2000>;
 347                 interrupts = <GIC_PPI 9
 348                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 349                 interrupt-parent = <&gic>;
 350         };
 351
 352         gpu@57000000 {
 353                 compatible = "nvidia,gm20b";
 354                 reg = <0x0 0x57000000 0x0 0x01000000>,
 355                       <0x0 0x58000000 0x0 0x01000000>;
 356                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 357                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 358                 interrupt-names = "stall", "nonstall";
 359                 clocks = <&tegra_car TEGRA210_CLK_GPU>,
 360                          <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
 361                          <&tegra_car TEGRA210_CLK_PLL_G_REF>;
 362                 clock-names = "gpu", "pwr", "ref";
 363                 resets = <&tegra_car 184>;
 364                 reset-names = "gpu";
 365
 366                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 367
 368                 status = "disabled";
 369         };
 370
 371         lic: interrupt-controller@60004000 {
 372                 compatible = "nvidia,tegra210-ictlr";
 373                 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
 374                       <0x0 0x60004100 0x0 0x40>, /* secondary controller */
 375                       <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
 376                       <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
 377                       <0x0 0x60004400 0x0 0x40>, /* quinary controller */
 378                       <0x0 0x60004500 0x0 0x40>; /* senary controller */
 379                 interrupt-controller;
 380                 #interrupt-cells = <3>;
 381                 interrupt-parent = <&gic>;
 382         };
 383
 384         timer@60005000 {
 385                 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
 386                 reg = <0x0 0x60005000 0x0 0x400>;
 387                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 388                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 389                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
 394                 clock-names = "timer";
 395         };
 396
 397         tegra_car: clock@60006000 {
 398                 compatible = "nvidia,tegra210-car";
 399                 reg = <0x0 0x60006000 0x0 0x1000>;
 400                 #clock-cells = <1>;
 401                 #reset-cells = <1>;
 402         };
 403
 404         flow-controller@60007000 {
 405                 compatible = "nvidia,tegra210-flowctrl";
 406                 reg = <0x0 0x60007000 0x0 0x1000>;
 407         };
 408
 409         gpio: gpio@6000d000 {
 410                 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
 411                 reg = <0x0 0x6000d000 0x0 0x1000>;
 412                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 413                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 414                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 415                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 416                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 417                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 418                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 419                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 420                 #gpio-cells = <2>;
 421                 gpio-controller;
 422                 #interrupt-cells = <2>;
 423                 interrupt-controller;
 424         };
 425
 426         apbdma: dma@60020000 {
 427                 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
 428                 reg = <0x0 0x60020000 0x0 0x1400>;
 429                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 430                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 431                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 432                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 433                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 435                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 436                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 437                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 438                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 439                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 440                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 441                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 442                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 443                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 444                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 445                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 446                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 447                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 448                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 449                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 450                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 451                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 452                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 453                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 454                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 455                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 456                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 457                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 458                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 459                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 460                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
 462                 clock-names = "dma";
 463                 resets = <&tegra_car 34>;
 464                 reset-names = "dma";
 465                 #dma-cells = <1>;
 466         };
 467
 468         apbmisc@70000800 {
 469                 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
 470                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 471                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 472         };
 473
 474         pinmux: pinmux@700008d4 {
 475                 compatible = "nvidia,tegra210-pinmux";
 476                 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
 477                       <0x0 0x70003000 0x0 0x294>; /* Mux registers */
 478         };
 479
 480         /*
 481          * There are two serial driver i.e. 8250 based simple serial
 482          * driver and APB DMA based serial driver for higher baudrate
 483          * and performance. To enable the 8250 based driver, the compatible
 484          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 485          * the APB DMA based serial driver, the compatible is
 486          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 487          */
 488         uarta: serial@70006000 {
 489                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 490                 reg = <0x0 0x70006000 0x0 0x40>;
 491                 reg-shift = <2>;
 492                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 493                 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
 494                 clock-names = "serial";
 495                 resets = <&tegra_car 6>;
 496                 reset-names = "serial";
 497                 dmas = <&apbdma 8>, <&apbdma 8>;
 498                 dma-names = "rx", "tx";
 499                 status = "disabled";
 500         };
 501
 502         uartb: serial@70006040 {
 503                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 504                 reg = <0x0 0x70006040 0x0 0x40>;
 505                 reg-shift = <2>;
 506                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
 508                 clock-names = "serial";
 509                 resets = <&tegra_car 7>;
 510                 reset-names = "serial";
 511                 dmas = <&apbdma 9>, <&apbdma 9>;
 512                 dma-names = "rx", "tx";
 513                 status = "disabled";
 514         };
 515
 516         uartc: serial@70006200 {
 517                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 518                 reg = <0x0 0x70006200 0x0 0x40>;
 519                 reg-shift = <2>;
 520                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 521                 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
 522                 clock-names = "serial";
 523                 resets = <&tegra_car 55>;
 524                 reset-names = "serial";
 525                 dmas = <&apbdma 10>, <&apbdma 10>;
 526                 dma-names = "rx", "tx";
 527                 status = "disabled";
 528         };
 529
 530         uartd: serial@70006300 {
 531                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 532                 reg = <0x0 0x70006300 0x0 0x40>;
 533                 reg-shift = <2>;
 534                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 535                 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
 536                 clock-names = "serial";
 537                 resets = <&tegra_car 65>;
 538                 reset-names = "serial";
 539                 dmas = <&apbdma 19>, <&apbdma 19>;
 540                 dma-names = "rx", "tx";
 541                 status = "disabled";
 542         };
 543
 544         pwm: pwm@7000a000 {
 545                 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
 546                 reg = <0x0 0x7000a000 0x0 0x100>;
 547                 #pwm-cells = <2>;
 548                 clocks = <&tegra_car TEGRA210_CLK_PWM>;
 549                 clock-names = "pwm";
 550                 resets = <&tegra_car 17>;
 551                 reset-names = "pwm";
 552                 status = "disabled";
 553         };
 554
 555         i2c@7000c000 {
 556                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 557                 reg = <0x0 0x7000c000 0x0 0x100>;
 558                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
 562                 clock-names = "div-clk";
 563                 resets = <&tegra_car 12>;
 564                 reset-names = "i2c";
 565                 dmas = <&apbdma 21>, <&apbdma 21>;
 566                 dma-names = "rx", "tx";
 567                 status = "disabled";
 568         };
 569
 570         i2c@7000c400 {
 571                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 572                 reg = <0x0 0x7000c400 0x0 0x100>;
 573                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
 577                 clock-names = "div-clk";
 578                 resets = <&tegra_car 54>;
 579                 reset-names = "i2c";
 580                 dmas = <&apbdma 22>, <&apbdma 22>;
 581                 dma-names = "rx", "tx";
 582                 status = "disabled";
 583         };
 584
 585         i2c@7000c500 {
 586                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 587                 reg = <0x0 0x7000c500 0x0 0x100>;
 588                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
 592                 clock-names = "div-clk";
 593                 resets = <&tegra_car 67>;
 594                 reset-names = "i2c";
 595                 dmas = <&apbdma 23>, <&apbdma 23>;
 596                 dma-names = "rx", "tx";
 597                 status = "disabled";
 598         };
 599
 600         i2c@7000c700 {
 601                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 602                 reg = <0x0 0x7000c700 0x0 0x100>;
 603                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
 607                 clock-names = "div-clk";
 608                 resets = <&tegra_car 103>;
 609                 reset-names = "i2c";
 610                 dmas = <&apbdma 26>, <&apbdma 26>;
 611                 dma-names = "rx", "tx";
 612                 pinctrl-0 = <&state_dpaux1_i2c>;
 613                 pinctrl-1 = <&state_dpaux1_off>;
 614                 pinctrl-names = "default", "idle";
 615                 status = "disabled";
 616         };
 617
 618         i2c@7000d000 {
 619                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 620                 reg = <0x0 0x7000d000 0x0 0x100>;
 621                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
 625                 clock-names = "div-clk";
 626                 resets = <&tegra_car 47>;
 627                 reset-names = "i2c";
 628                 dmas = <&apbdma 24>, <&apbdma 24>;
 629                 dma-names = "rx", "tx";
 630                 status = "disabled";
 631         };
 632
 633         i2c@7000d100 {
 634                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
 635                 reg = <0x0 0x7000d100 0x0 0x100>;
 636                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 637                 #address-cells = <1>;
 638                 #size-cells = <0>;
 639                 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
 640                 clock-names = "div-clk";
 641                 resets = <&tegra_car 166>;
 642                 reset-names = "i2c";
 643                 dmas = <&apbdma 30>, <&apbdma 30>;
 644                 dma-names = "rx", "tx";
 645                 pinctrl-0 = <&state_dpaux_i2c>;
 646                 pinctrl-1 = <&state_dpaux_off>;
 647                 pinctrl-names = "default", "idle";
 648                 status = "disabled";
 649         };
 650
 651         spi@7000d400 {
 652                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 653                 reg = <0x0 0x7000d400 0x0 0x200>;
 654                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
 658                 clock-names = "spi";
 659                 resets = <&tegra_car 41>;
 660                 reset-names = "spi";
 661                 dmas = <&apbdma 15>, <&apbdma 15>;
 662                 dma-names = "rx", "tx";
 663                 status = "disabled";
 664         };
 665
 666         spi@7000d600 {
 667                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 668                 reg = <0x0 0x7000d600 0x0 0x200>;
 669                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
 673                 clock-names = "spi";
 674                 resets = <&tegra_car 44>;
 675                 reset-names = "spi";
 676                 dmas = <&apbdma 16>, <&apbdma 16>;
 677                 dma-names = "rx", "tx";
 678                 status = "disabled";
 679         };
 680
 681         spi@7000d800 {
 682                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 683                 reg = <0x0 0x7000d800 0x0 0x200>;
 684                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 685                 #address-cells = <1>;
 686                 #size-cells = <0>;
 687                 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
 688                 clock-names = "spi";
 689                 resets = <&tegra_car 46>;
 690                 reset-names = "spi";
 691                 dmas = <&apbdma 17>, <&apbdma 17>;
 692                 dma-names = "rx", "tx";
 693                 status = "disabled";
 694         };
 695
 696         spi@7000da00 {
 697                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 698                 reg = <0x0 0x7000da00 0x0 0x200>;
 699                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
 703                 clock-names = "spi";
 704                 resets = <&tegra_car 68>;
 705                 reset-names = "spi";
 706                 dmas = <&apbdma 18>, <&apbdma 18>;
 707                 dma-names = "rx", "tx";
 708                 status = "disabled";
 709         };
 710
 711         rtc@7000e000 {
 712                 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
 713                 reg = <0x0 0x7000e000 0x0 0x100>;
 714                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 715                 clocks = <&tegra_car TEGRA210_CLK_RTC>;
 716                 clock-names = "rtc";
 717         };
 718
 719         pmc: pmc@7000e400 {
 720                 compatible = "nvidia,tegra210-pmc";
 721                 reg = <0x0 0x7000e400 0x0 0x400>;
 722                 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 723                 clock-names = "pclk", "clk32k_in";
 724
 725                 powergates {
 726                         pd_audio: aud {
 727                                 clocks = <&tegra_car TEGRA210_CLK_APE>,
 728                                          <&tegra_car TEGRA210_CLK_APB2APE>;
 729                                 resets = <&tegra_car 198>;
 730                                 #power-domain-cells = <0>;
 731                         };
 732
 733                         pd_sor: sor {
 734                                 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 735                                          <&tegra_car TEGRA210_CLK_SOR1>,
 736                                          <&tegra_car TEGRA210_CLK_CSI>,
 737                                          <&tegra_car TEGRA210_CLK_DSIA>,
 738                                          <&tegra_car TEGRA210_CLK_DSIB>,
 739                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 740                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 741                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 742                                 resets = <&tegra_car TEGRA210_CLK_SOR0>,
 743                                          <&tegra_car TEGRA210_CLK_SOR1>,
 744                                          <&tegra_car TEGRA210_CLK_CSI>,
 745                                          <&tegra_car TEGRA210_CLK_DSIA>,
 746                                          <&tegra_car TEGRA210_CLK_DSIB>,
 747                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 748                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 749                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 750                                 #power-domain-cells = <0>;
 751                         };
 752
 753                         pd_xusbss: xusba {
 754                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 755                                 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 756                                 #power-domain-cells = <0>;
 757                         };
 758
 759                         pd_xusbdev: xusbb {
 760                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
 761                                 resets = <&tegra_car 95>;
 762                                 #power-domain-cells = <0>;
 763                         };
 764
 765                         pd_xusbhost: xusbc {
 766                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 767                                 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 768                                 #power-domain-cells = <0>;
 769                         };
 770
 771                         pd_vic: vic {
 772                                 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 773                                 clock-names = "vic";
 774                                 resets = <&tegra_car 178>;
 775                                 reset-names = "vic";
 776                                 #power-domain-cells = <0>;
 777                         };
 778                 };
 779         };
 780
 781         fuse@7000f800 {
 782                 compatible = "nvidia,tegra210-efuse";
 783                 reg = <0x0 0x7000f800 0x0 0x400>;
 784                 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
 785                 clock-names = "fuse";
 786                 resets = <&tegra_car 39>;
 787                 reset-names = "fuse";
 788         };
 789
 790         mc: memory-controller@70019000 {
 791                 compatible = "nvidia,tegra210-mc";
 792                 reg = <0x0 0x70019000 0x0 0x1000>;
 793                 clocks = <&tegra_car TEGRA210_CLK_MC>;
 794                 clock-names = "mc";
 795
 796                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 797
 798                 #iommu-cells = <1>;
 799         };
 800
 801         hda@70030000 {
 802                 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
 803                 reg = <0x0 0x70030000 0x0 0x10000>;
 804                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 805                 clocks = <&tegra_car TEGRA210_CLK_HDA>,
 806                          <&tegra_car TEGRA210_CLK_HDA2HDMI>,
 807                          <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
 808                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 809                 resets = <&tegra_car 125>, /* hda */
 810                          <&tegra_car 128>, /* hda2hdmi */
 811                          <&tegra_car 111>; /* hda2codec_2x */
 812                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 813                 status = "disabled";
 814         };
 815
 816         usb@70090000 {
 817                 compatible = "nvidia,tegra210-xusb";
 818                 reg = <0x0 0x70090000 0x0 0x8000>,
 819                       <0x0 0x70098000 0x0 0x1000>,
 820                       <0x0 0x70099000 0x0 0x1000>;
 821                 reg-names = "hcd", "fpci", "ipfs";
 822
 823                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 824                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 825
 826                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
 827                          <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
 828                          <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
 829                          <&tegra_car TEGRA210_CLK_XUSB_SS>,
 830                          <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
 831                          <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
 832                          <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
 833                          <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
 834                          <&tegra_car TEGRA210_CLK_PLL_U_480M>,
 835                          <&tegra_car TEGRA210_CLK_CLK_M>,
 836                          <&tegra_car TEGRA210_CLK_PLL_E>;
 837                 clock-names = "xusb_host", "xusb_host_src",
 838                               "xusb_falcon_src", "xusb_ss",
 839                               "xusb_ss_div2", "xusb_ss_src",
 840                               "xusb_hs_src", "xusb_fs_src",
 841                               "pll_u_480m", "clk_m", "pll_e";
 842                 resets = <&tegra_car 89>, <&tegra_car 156>,
 843                          <&tegra_car 143>;
 844                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 845
 846                 nvidia,xusb-padctl = <&padctl>;
 847
 848                 status = "disabled";
 849         };
 850
 851         padctl: padctl@7009f000 {
 852                 compatible = "nvidia,tegra210-xusb-padctl";
 853                 reg = <0x0 0x7009f000 0x0 0x1000>;
 854                 resets = <&tegra_car 142>;
 855                 reset-names = "padctl";
 856
 857                 status = "disabled";
 858
 859                 pads {
 860                         usb2 {
 861                                 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
 862                                 clock-names = "trk";
 863                                 status = "disabled";
 864
 865                                 lanes {
 866                                         usb2-0 {
 867                                                 status = "disabled";
 868                                                 #phy-cells = <0>;
 869                                         };
 870
 871                                         usb2-1 {
 872                                                 status = "disabled";
 873                                                 #phy-cells = <0>;
 874                                         };
 875
 876                                         usb2-2 {
 877                                                 status = "disabled";
 878                                                 #phy-cells = <0>;
 879                                         };
 880
 881                                         usb2-3 {
 882                                                 status = "disabled";
 883                                                 #phy-cells = <0>;
 884                                         };
 885                                 };
 886                         };
 887
 888                         hsic {
 889                                 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
 890                                 clock-names = "trk";
 891                                 status = "disabled";
 892
 893                                 lanes {
 894                                         hsic-0 {
 895                                                 status = "disabled";
 896                                                 #phy-cells = <0>;
 897                                         };
 898
 899                                         hsic-1 {
 900                                                 status = "disabled";
 901                                                 #phy-cells = <0>;
 902                                         };
 903                                 };
 904                         };
 905
 906                         pcie {
 907                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 908                                 clock-names = "pll";
 909                                 resets = <&tegra_car 205>;
 910                                 reset-names = "phy";
 911                                 status = "disabled";
 912
 913                                 lanes {
 914                                         pcie-0 {
 915                                                 status = "disabled";
 916                                                 #phy-cells = <0>;
 917                                         };
 918
 919                                         pcie-1 {
 920                                                 status = "disabled";
 921                                                 #phy-cells = <0>;
 922                                         };
 923
 924                                         pcie-2 {
 925                                                 status = "disabled";
 926                                                 #phy-cells = <0>;
 927                                         };
 928
 929                                         pcie-3 {
 930                                                 status = "disabled";
 931                                                 #phy-cells = <0>;
 932                                         };
 933
 934                                         pcie-4 {
 935                                                 status = "disabled";
 936                                                 #phy-cells = <0>;
 937                                         };
 938
 939                                         pcie-5 {
 940                                                 status = "disabled";
 941                                                 #phy-cells = <0>;
 942                                         };
 943
 944                                         pcie-6 {
 945                                                 status = "disabled";
 946                                                 #phy-cells = <0>;
 947                                         };
 948                                 };
 949                         };
 950
 951                         sata {
 952                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 953                                 clock-names = "pll";
 954                                 resets = <&tegra_car 204>;
 955                                 reset-names = "phy";
 956                                 status = "disabled";
 957
 958                                 lanes {
 959                                         sata-0 {
 960                                                 status = "disabled";
 961                                                 #phy-cells = <0>;
 962                                         };
 963                                 };
 964                         };
 965                 };
 966
 967                 ports {
 968                         usb2-0 {
 969                                 status = "disabled";
 970                         };
 971
 972                         usb2-1 {
 973                                 status = "disabled";
 974                         };
 975
 976                         usb2-2 {
 977                                 status = "disabled";
 978                         };
 979
 980                         usb2-3 {
 981                                 status = "disabled";
 982                         };
 983
 984                         hsic-0 {
 985                                 status = "disabled";
 986                         };
 987
 988                         usb3-0 {
 989                                 status = "disabled";
 990                         };
 991
 992                         usb3-1 {
 993                                 status = "disabled";
 994                         };
 995
 996                         usb3-2 {
 997                                 status = "disabled";
 998                         };
 999
1000                         usb3-3 {
1001                                 status = "disabled";
1002                         };
1003                 };
1004         };
1005
1006         sdhci@700b0000 {
1007                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1008                 reg = <0x0 0x700b0000 0x0 0x200>;
1009                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1010                 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1011                 clock-names = "sdhci";
1012                 resets = <&tegra_car 14>;
1013                 reset-names = "sdhci";
1014                 status = "disabled";
1015         };
1016
1017         sdhci@700b0200 {
1018                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1019                 reg = <0x0 0x700b0200 0x0 0x200>;
1020                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1021                 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1022                 clock-names = "sdhci";
1023                 resets = <&tegra_car 9>;
1024                 reset-names = "sdhci";
1025                 status = "disabled";
1026         };
1027
1028         sdhci@700b0400 {
1029                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1030                 reg = <0x0 0x700b0400 0x0 0x200>;
1031                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1032                 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1033                 clock-names = "sdhci";
1034                 resets = <&tegra_car 69>;
1035                 reset-names = "sdhci";
1036                 status = "disabled";
1037         };
1038
1039         sdhci@700b0600 {
1040                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1041                 reg = <0x0 0x700b0600 0x0 0x200>;
1042                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1043                 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1044                 clock-names = "sdhci";
1045                 resets = <&tegra_car 15>;
1046                 reset-names = "sdhci";
1047                 status = "disabled";
1048         };
1049
1050         mipi: mipi@700e3000 {
1051                 compatible = "nvidia,tegra210-mipi";
1052                 reg = <0x0 0x700e3000 0x0 0x100>;
1053                 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1054                 clock-names = "mipi-cal";
1055                 power-domains = <&pd_sor>;
1056                 #nvidia,mipi-calibrate-cells = <1>;
1057         };
1058
1059         aconnect@702c0000 {
1060                 compatible = "nvidia,tegra210-aconnect";
1061                 clocks = <&tegra_car TEGRA210_CLK_APE>,
1062                          <&tegra_car TEGRA210_CLK_APB2APE>;
1063                 clock-names = "ape", "apb2ape";
1064                 power-domains = <&pd_audio>;
1065                 #address-cells = <1>;
1066                 #size-cells = <1>;
1067                 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1068                 status = "disabled";
1069
1070                 adma: dma@702e2000 {
1071                         compatible = "nvidia,tegra210-adma";
1072                         reg = <0x702e2000 0x2000>;
1073                         interrupt-parent = <&agic>;
1074                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1075                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1076                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1077                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1078                                      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1079                                      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1080                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1081                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1082                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1083                                      <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1084                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1085                                      <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1086                                      <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1087                                      <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1088                                      <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1089                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1090                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1091                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1092                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1093                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1094                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1095                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1096                         #dma-cells = <1>;
1097                         clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1098                         clock-names = "d_audio";
1099                         status = "disabled";
1100                 };
1101
1102                 agic: agic@702f9000 {
1103                         compatible = "nvidia,tegra210-agic";
1104                         #interrupt-cells = <3>;
1105                         interrupt-controller;
1106                         reg = <0x702f9000 0x2000>,
1107                               <0x702fa000 0x2000>;
1108                         interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1109                         clocks = <&tegra_car TEGRA210_CLK_APE>;
1110                         clock-names = "clk";
1111                         status = "disabled";
1112                 };
1113         };
1114
1115         spi@70410000 {
1116                 compatible = "nvidia,tegra210-qspi";
1117                 reg = <0x0 0x70410000 0x0 0x1000>;
1118                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1119                 #address-cells = <1>;
1120                 #size-cells = <0>;
1121                 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1122                 clock-names = "qspi";
1123                 resets = <&tegra_car 211>;
1124                 reset-names = "qspi";
1125                 dmas = <&apbdma 5>, <&apbdma 5>;
1126                 dma-names = "rx", "tx";
1127                 status = "disabled";
1128         };
1129
1130         usb@7d000000 {
1131                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1132                 reg = <0x0 0x7d000000 0x0 0x4000>;
1133                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1134                 phy_type = "utmi";
1135                 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1136                 clock-names = "usb";
1137                 resets = <&tegra_car 22>;
1138                 reset-names = "usb";
1139                 nvidia,phy = <&phy1>;
1140                 status = "disabled";
1141         };
1142
1143         phy1: usb-phy@7d000000 {
1144                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1145                 reg = <0x0 0x7d000000 0x0 0x4000>,
1146                       <0x0 0x7d000000 0x0 0x4000>;
1147                 phy_type = "utmi";
1148                 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1149                          <&tegra_car TEGRA210_CLK_PLL_U>,
1150                          <&tegra_car TEGRA210_CLK_USBD>;
1151                 clock-names = "reg", "pll_u", "utmi-pads";
1152                 resets = <&tegra_car 22>, <&tegra_car 22>;
1153                 reset-names = "usb", "utmi-pads";
1154                 nvidia,hssync-start-delay = <0>;
1155                 nvidia,idle-wait-delay = <17>;
1156                 nvidia,elastic-limit = <16>;
1157                 nvidia,term-range-adj = <6>;
1158                 nvidia,xcvr-setup = <9>;
1159                 nvidia,xcvr-lsfslew = <0>;
1160                 nvidia,xcvr-lsrslew = <3>;
1161                 nvidia,hssquelch-level = <2>;
1162                 nvidia,hsdiscon-level = <5>;
1163                 nvidia,xcvr-hsslew = <12>;
1164                 nvidia,has-utmi-pad-registers;
1165                 status = "disabled";
1166         };
1167
1168         usb@7d004000 {
1169                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1170                 reg = <0x0 0x7d004000 0x0 0x4000>;
1171                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1172                 phy_type = "utmi";
1173                 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1174                 clock-names = "usb";
1175                 resets = <&tegra_car 58>;
1176                 reset-names = "usb";
1177                 nvidia,phy = <&phy2>;
1178                 status = "disabled";
1179         };
1180
1181         phy2: usb-phy@7d004000 {
1182                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1183                 reg = <0x0 0x7d004000 0x0 0x4000>,
1184                       <0x0 0x7d000000 0x0 0x4000>;
1185                 phy_type = "utmi";
1186                 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1187                          <&tegra_car TEGRA210_CLK_PLL_U>,
1188                          <&tegra_car TEGRA210_CLK_USBD>;
1189                 clock-names = "reg", "pll_u", "utmi-pads";
1190                 resets = <&tegra_car 58>, <&tegra_car 22>;
1191                 reset-names = "usb", "utmi-pads";
1192                 nvidia,hssync-start-delay = <0>;
1193                 nvidia,idle-wait-delay = <17>;
1194                 nvidia,elastic-limit = <16>;
1195                 nvidia,term-range-adj = <6>;
1196                 nvidia,xcvr-setup = <9>;
1197                 nvidia,xcvr-lsfslew = <0>;
1198                 nvidia,xcvr-lsrslew = <3>;
1199                 nvidia,hssquelch-level = <2>;
1200                 nvidia,hsdiscon-level = <5>;
1201                 nvidia,xcvr-hsslew = <12>;
1202                 status = "disabled";
1203         };
1204
1205         cpus {
1206                 #address-cells = <1>;
1207                 #size-cells = <0>;
1208
1209                 cpu@0 {
1210                         device_type = "cpu";
1211                         compatible = "arm,cortex-a57";
1212                         reg = <0>;
1213                 };
1214
1215                 cpu@1 {
1216                         device_type = "cpu";
1217                         compatible = "arm,cortex-a57";
1218                         reg = <1>;
1219                 };
1220
1221                 cpu@2 {
1222                         device_type = "cpu";
1223                         compatible = "arm,cortex-a57";
1224                         reg = <2>;
1225                 };
1226
1227                 cpu@3 {
1228                         device_type = "cpu";
1229                         compatible = "arm,cortex-a57";
1230                         reg = <3>;
1231                 };
1232         };
1233
1234         timer {
1235                 compatible = "arm,armv8-timer";
1236                 interrupts = <GIC_PPI 13
1237                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1238                              <GIC_PPI 14
1239                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1240                              <GIC_PPI 11
1241                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1242                              <GIC_PPI 10
1243                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1244                 interrupt-parent = <&gic>;
1245         };
1246
1247         soctherm: thermal-sensor@700e2000 {
1248                 compatible = "nvidia,tegra210-soctherm";
1249                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1250                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1251                 reg-names = "soctherm-reg", "car-reg";
1252                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1253                 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1254                         <&tegra_car TEGRA210_CLK_SOC_THERM>;
1255                 clock-names = "tsensor", "soctherm";
1256                 resets = <&tegra_car 78>;
1257                 reset-names = "soctherm";
1258                 #thermal-sensor-cells = <1>;
1259
1260                 throttle-cfgs {
1261                         throttle_heavy: heavy {
1262                                 nvidia,priority = <100>;
1263                                 nvidia,cpu-throt-percent = <85>;
1264
1265                                 #cooling-cells = <2>;
1266                         };
1267                 };
1268         };
1269
1270         thermal-zones {
1271                 cpu {
1272                         polling-delay-passive = <1000>;
1273                         polling-delay = <0>;
1274
1275                         thermal-sensors =
1276                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1277
1278                         trips {
1279                                 cpu-shutdown-trip {
1280                                         temperature = <102500>;
1281                                         hysteresis = <0>;
1282                                         type = "critical";
1283                                 };
1284
1285                                 cpu_throttle_trip: throttle-trip {
1286                                         temperature = <98500>;
1287                                         hysteresis = <1000>;
1288                                         type = "hot";
1289                                 };
1290                         };
1291
1292                         cooling-maps {
1293                                 map0 {
1294                                         trip = <&cpu_throttle_trip>;
1295                                         cooling-device = <&throttle_heavy 1 1>;
1296                                 };
1297                         };
1298                 };
1299                 mem {
1300                         polling-delay-passive = <0>;
1301                         polling-delay = <0>;
1302
1303                         thermal-sensors =
1304                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1305
1306                         trips {
1307                                 mem-shutdown-trip {
1308                                         temperature = <103000>;
1309                                         hysteresis = <0>;
1310                                         type = "critical";
1311                                 };
1312                         };
1313
1314                         cooling-maps {
1315                                 /*
1316                                  * There are currently no cooling maps,
1317                                  * because there are no cooling devices.
1318                                  */
1319                         };
1320                 };
1321                 gpu {
1322                         polling-delay-passive = <1000>;
1323                         polling-delay = <0>;
1324
1325                         thermal-sensors =
1326                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1327
1328                         trips {
1329                                 gpu-shutdown-trip {
1330                                         temperature = <103000>;
1331                                         hysteresis = <0>;
1332                                         type = "critical";
1333                                 };
1334
1335                                 gpu_throttle_trip: throttle-trip {
1336                                         temperature = <100000>;
1337                                         hysteresis = <1000>;
1338                                         type = "hot";
1339                                 };
1340                         };
1341
1342                         cooling-maps {
1343                                 map0 {
1344                                         trip = <&gpu_throttle_trip>;
1345                                         cooling-device = <&throttle_heavy 1 1>;
1346                                 };
1347                         };
1348                 };
1349                 pllx {
1350                         polling-delay-passive = <0>;
1351                         polling-delay = <0>;
1352
1353                         thermal-sensors =
1354                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1355
1356                         trips {
1357                                 pllx-shutdown-trip {
1358                                         temperature = <103000>;
1359                                         hysteresis = <0>;
1360                                         type = "critical";
1361                                 };
1362                         };
1363
1364                         cooling-maps {
1365                                 /*
1366                                  * There are currently no cooling maps,
1367                                  * because there are no cooling devices.
1368                                  */
1369                         };
1370                 };
1371         };
1372 };