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1 /*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
17 #include <dt-bindings/clock/qcom,rpmcc.h>
18 #include <dt-bindings/thermal/thermal.h>
19
20 / {
21 interrupt-parent = <&intc>;
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
28 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
29 };
30
31 chosen { };
32
33 memory {
34 device_type = "memory";
35 /* We expect the bootloader to fill in the reg */
36 reg = <0 0 0 0>;
37 };
38
39 reserved-memory {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 ranges;
43
44 tz-apps@86000000 {
45 reg = <0x0 0x86000000 0x0 0x300000>;
46 no-map;
47 };
48
49 smem_mem: smem_region@86300000 {
50 reg = <0x0 0x86300000 0x0 0x100000>;
51 no-map;
52 };
53
54 hypervisor@86400000 {
55 reg = <0x0 0x86400000 0x0 0x100000>;
56 no-map;
57 };
58
59 tz@86500000 {
60 reg = <0x0 0x86500000 0x0 0x180000>;
61 no-map;
62 };
63
64 reserved@8668000 {
65 reg = <0x0 0x86680000 0x0 0x80000>;
66 no-map;
67 };
68
69 rmtfs@86700000 {
70 compatible = "qcom,rmtfs-mem";
71 reg = <0x0 0x86700000 0x0 0xe0000>;
72 no-map;
73
74 qcom,client-id = <1>;
75 };
76
77 rfsa@867e00000 {
78 reg = <0x0 0x867e0000 0x0 0x20000>;
79 no-map;
80 };
81
82 mpss_mem: mpss@86800000 {
83 reg = <0x0 0x86800000 0x0 0x2b00000>;
84 no-map;
85 };
86
87 wcnss_mem: wcnss@89300000 {
88 reg = <0x0 0x89300000 0x0 0x600000>;
89 no-map;
90 };
91
92 venus_mem: venus@89900000 {
93 reg = <0x0 0x89900000 0x0 0x600000>;
94 no-map;
95 };
96
97 mba_mem: mba@8ea00000 {
98 no-map;
99 reg = <0 0x8ea00000 0 0x100000>;
100 };
101 };
102
103 cpus {
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 CPU0: cpu@0 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a53";
110 reg = <0x0>;
111 next-level-cache = <&L2_0>;
112 enable-method = "psci";
113 cpu-idle-states = <&CPU_SPC>;
114 clocks = <&apcs>;
115 operating-points-v2 = <&cpu_opp_table>;
116 #cooling-cells = <2>;
117 };
118
119 CPU1: cpu@1 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a53";
122 reg = <0x1>;
123 next-level-cache = <&L2_0>;
124 enable-method = "psci";
125 cpu-idle-states = <&CPU_SPC>;
126 clocks = <&apcs>;
127 operating-points-v2 = <&cpu_opp_table>;
128 #cooling-cells = <2>;
129 };
130
131 CPU2: cpu@2 {
132 device_type = "cpu";
133 compatible = "arm,cortex-a53";
134 reg = <0x2>;
135 next-level-cache = <&L2_0>;
136 enable-method = "psci";
137 cpu-idle-states = <&CPU_SPC>;
138 clocks = <&apcs>;
139 operating-points-v2 = <&cpu_opp_table>;
140 #cooling-cells = <2>;
141 };
142
143 CPU3: cpu@3 {
144 device_type = "cpu";
145 compatible = "arm,cortex-a53";
146 reg = <0x3>;
147 next-level-cache = <&L2_0>;
148 enable-method = "psci";
149 cpu-idle-states = <&CPU_SPC>;
150 clocks = <&apcs>;
151 operating-points-v2 = <&cpu_opp_table>;
152 #cooling-cells = <2>;
153 };
154
155 L2_0: l2-cache {
156 compatible = "cache";
157 cache-level = <2>;
158 };
159
160 idle-states {
161 CPU_SPC: spc {
162 compatible = "arm,idle-state";
163 arm,psci-suspend-param = <0x40000002>;
164 entry-latency-us = <130>;
165 exit-latency-us = <150>;
166 min-residency-us = <2000>;
167 local-timer-stop;
168 };
169 };
170 };
171
172 psci {
173 compatible = "arm,psci-1.0";
174 method = "smc";
175 };
176
177 pmu {
178 compatible = "arm,cortex-a53-pmu";
179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
180 };
181
182 thermal-zones {
183 cpu0_1-thermal {
184 polling-delay-passive = <250>;
185 polling-delay = <1000>;
186
187 thermal-sensors = <&tsens 4>;
188
189 trips {
190 cpu0_1_alert0: trip-point@0 {
191 temperature = <75000>;
192 hysteresis = <2000>;
193 type = "passive";
194 };
195 cpu0_1_crit: cpu_crit {
196 temperature = <110000>;
197 hysteresis = <2000>;
198 type = "critical";
199 };
200 };
201
202 cooling-maps {
203 map0 {
204 trip = <&cpu0_1_alert0>;
205 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
209 };
210 };
211 };
212
213 cpu2_3-thermal {
214 polling-delay-passive = <250>;
215 polling-delay = <1000>;
216
217 thermal-sensors = <&tsens 3>;
218
219 trips {
220 cpu2_3_alert0: trip-point@0 {
221 temperature = <75000>;
222 hysteresis = <2000>;
223 type = "passive";
224 };
225 cpu2_3_crit: cpu_crit {
226 temperature = <110000>;
227 hysteresis = <2000>;
228 type = "critical";
229 };
230 };
231
232 cooling-maps {
233 map0 {
234 trip = <&cpu2_3_alert0>;
235 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
237 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
239 };
240 };
241 };
242
243 gpu-thermal {
244 polling-delay-passive = <250>;
245 polling-delay = <1000>;
246
247 thermal-sensors = <&tsens 2>;
248
249 trips {
250 gpu_alert0: trip-point@0 {
251 temperature = <75000>;
252 hysteresis = <2000>;
253 type = "passive";
254 };
255 gpu_crit: gpu_crit {
256 temperature = <95000>;
257 hysteresis = <2000>;
258 type = "critical";
259 };
260 };
261 };
262
263 camera-thermal {
264 polling-delay-passive = <250>;
265 polling-delay = <1000>;
266
267 thermal-sensors = <&tsens 1>;
268
269 trips {
270 cam_alert0: trip-point@0 {
271 temperature = <75000>;
272 hysteresis = <2000>;
273 type = "hot";
274 };
275 };
276 };
277
278 modem-thermal {
279 polling-delay-passive = <250>;
280 polling-delay = <1000>;
281
282 thermal-sensors = <&tsens 0>;
283
284 trips {
285 modem_alert0: trip-point@0 {
286 temperature = <85000>;
287 hysteresis = <2000>;
288 type = "hot";
289 };
290 };
291 };
292
293 };
294
295 cpu_opp_table: cpu_opp_table {
296 compatible = "operating-points-v2";
297 opp-shared;
298
299 opp-200000000 {
300 opp-hz = /bits/ 64 <200000000>;
301 };
302 opp-400000000 {
303 opp-hz = /bits/ 64 <400000000>;
304 };
305 opp-800000000 {
306 opp-hz = /bits/ 64 <800000000>;
307 };
308 opp-998400000 {
309 opp-hz = /bits/ 64 <998400000>;
310 };
311 };
312
313 gpu_opp_table: opp_table {
314 compatible = "operating-points-v2";
315
316 opp-400000000 {
317 opp-hz = /bits/ 64 <400000000>;
318 };
319 opp-19200000 {
320 opp-hz = /bits/ 64 <19200000>;
321 };
322 };
323
324 timer {
325 compatible = "arm,armv8-timer";
326 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
327 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
328 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
329 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
330 };
331
332 clocks {
333 xo_board: xo_board {
334 compatible = "fixed-clock";
335 #clock-cells = <0>;
336 clock-frequency = <19200000>;
337 };
338
339 sleep_clk: sleep_clk {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <32768>;
343 };
344 };
345
346 smem {
347 compatible = "qcom,smem";
348
349 memory-region = <&smem_mem>;
350 qcom,rpm-msg-ram = <&rpm_msg_ram>;
351
352 hwlocks = <&tcsr_mutex 3>;
353 };
354
355 firmware {
356 scm: scm {
357 compatible = "qcom,scm";
358 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
359 clock-names = "core", "bus", "iface";
360 #reset-cells = <1>;
361
362 qcom,dload-mode = <&tcsr 0x6100>;
363 };
364 };
365
366 soc: soc {
367 #address-cells = <1>;
368 #size-cells = <1>;
369 ranges = <0 0 0 0xffffffff>;
370 compatible = "simple-bus";
371
372 restart@4ab000 {
373 compatible = "qcom,pshold";
374 reg = <0x4ab000 0x4>;
375 };
376
377 msmgpio: pinctrl@1000000 {
378 compatible = "qcom,msm8916-pinctrl";
379 reg = <0x1000000 0x300000>;
380 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
381 gpio-controller;
382 #gpio-cells = <2>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
385 };
386
387 gcc: clock-controller@1800000 {
388 compatible = "qcom,gcc-msm8916";
389 #clock-cells = <1>;
390 #reset-cells = <1>;
391 #power-domain-cells = <1>;
392 reg = <0x1800000 0x80000>;
393 };
394
395 tcsr_mutex_regs: syscon@1905000 {
396 compatible = "syscon";
397 reg = <0x1905000 0x20000>;
398 };
399
400 tcsr: syscon@1937000 {
401 compatible = "qcom,tcsr-msm8916", "syscon";
402 reg = <0x1937000 0x30000>;
403 };
404
405 tcsr_mutex: hwlock {
406 compatible = "qcom,tcsr-mutex";
407 syscon = <&tcsr_mutex_regs 0 0x1000>;
408 #hwlock-cells = <1>;
409 };
410
411 rpm_msg_ram: memory@60000 {
412 compatible = "qcom,rpm-msg-ram";
413 reg = <0x60000 0x8000>;
414 };
415
416 blsp1_uart1: serial@78af000 {
417 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
418 reg = <0x78af000 0x200>;
419 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
421 clock-names = "core", "iface";
422 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
423 dma-names = "rx", "tx";
424 status = "disabled";
425 };
426
427 a53pll: clock@b016000 {
428 compatible = "qcom,msm8916-a53pll";
429 reg = <0xb016000 0x40>;
430 #clock-cells = <0>;
431 };
432
433 apcs: mailbox@b011000 {
434 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
435 reg = <0xb011000 0x1000>;
436 #mbox-cells = <1>;
437 clocks = <&a53pll>;
438 #clock-cells = <0>;
439 };
440
441 blsp1_uart2: serial@78b0000 {
442 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
443 reg = <0x78b0000 0x200>;
444 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", "iface";
447 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
448 dma-names = "rx", "tx";
449 status = "disabled";
450 };
451
452 blsp_dma: dma@7884000 {
453 compatible = "qcom,bam-v1.7.0";
454 reg = <0x07884000 0x23000>;
455 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
457 clock-names = "bam_clk";
458 #dma-cells = <1>;
459 qcom,ee = <0>;
460 status = "disabled";
461 };
462
463 blsp_spi1: spi@78b5000 {
464 compatible = "qcom,spi-qup-v2.2.1";
465 reg = <0x078b5000 0x500>;
466 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
468 <&gcc GCC_BLSP1_AHB_CLK>;
469 clock-names = "core", "iface";
470 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
471 dma-names = "rx", "tx";
472 pinctrl-names = "default", "sleep";
473 pinctrl-0 = <&spi1_default>;
474 pinctrl-1 = <&spi1_sleep>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 status = "disabled";
478 };
479
480 blsp_spi2: spi@78b6000 {
481 compatible = "qcom,spi-qup-v2.2.1";
482 reg = <0x078b6000 0x500>;
483 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
485 <&gcc GCC_BLSP1_AHB_CLK>;
486 clock-names = "core", "iface";
487 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
488 dma-names = "rx", "tx";
489 pinctrl-names = "default", "sleep";
490 pinctrl-0 = <&spi2_default>;
491 pinctrl-1 = <&spi2_sleep>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 status = "disabled";
495 };
496
497 blsp_spi3: spi@78b7000 {
498 compatible = "qcom,spi-qup-v2.2.1";
499 reg = <0x078b7000 0x500>;
500 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
502 <&gcc GCC_BLSP1_AHB_CLK>;
503 clock-names = "core", "iface";
504 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
505 dma-names = "rx", "tx";
506 pinctrl-names = "default", "sleep";
507 pinctrl-0 = <&spi3_default>;
508 pinctrl-1 = <&spi3_sleep>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 status = "disabled";
512 };
513
514 blsp_spi4: spi@78b8000 {
515 compatible = "qcom,spi-qup-v2.2.1";
516 reg = <0x078b8000 0x500>;
517 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
519 <&gcc GCC_BLSP1_AHB_CLK>;
520 clock-names = "core", "iface";
521 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
522 dma-names = "rx", "tx";
523 pinctrl-names = "default", "sleep";
524 pinctrl-0 = <&spi4_default>;
525 pinctrl-1 = <&spi4_sleep>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 status = "disabled";
529 };
530
531 blsp_spi5: spi@78b9000 {
532 compatible = "qcom,spi-qup-v2.2.1";
533 reg = <0x078b9000 0x500>;
534 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
536 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", "iface";
538 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
539 dma-names = "rx", "tx";
540 pinctrl-names = "default", "sleep";
541 pinctrl-0 = <&spi5_default>;
542 pinctrl-1 = <&spi5_sleep>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 status = "disabled";
546 };
547
548 blsp_spi6: spi@78ba000 {
549 compatible = "qcom,spi-qup-v2.2.1";
550 reg = <0x078ba000 0x500>;
551 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
553 <&gcc GCC_BLSP1_AHB_CLK>;
554 clock-names = "core", "iface";
555 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
556 dma-names = "rx", "tx";
557 pinctrl-names = "default", "sleep";
558 pinctrl-0 = <&spi6_default>;
559 pinctrl-1 = <&spi6_sleep>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 status = "disabled";
563 };
564
565 blsp_i2c2: i2c@78b6000 {
566 compatible = "qcom,i2c-qup-v2.2.1";
567 reg = <0x078b6000 0x500>;
568 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
570 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
571 clock-names = "iface", "core";
572 pinctrl-names = "default", "sleep";
573 pinctrl-0 = <&i2c2_default>;
574 pinctrl-1 = <&i2c2_sleep>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 status = "disabled";
578 };
579
580 blsp_i2c4: i2c@78b8000 {
581 compatible = "qcom,i2c-qup-v2.2.1";
582 reg = <0x078b8000 0x500>;
583 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
585 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
586 clock-names = "iface", "core";
587 pinctrl-names = "default", "sleep";
588 pinctrl-0 = <&i2c4_default>;
589 pinctrl-1 = <&i2c4_sleep>;
590 #address-cells = <1>;
591 #size-cells = <0>;
592 status = "disabled";
593 };
594
595 blsp_i2c6: i2c@78ba000 {
596 compatible = "qcom,i2c-qup-v2.2.1";
597 reg = <0x078ba000 0x500>;
598 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
600 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
601 clock-names = "iface", "core";
602 pinctrl-names = "default", "sleep";
603 pinctrl-0 = <&i2c6_default>;
604 pinctrl-1 = <&i2c6_sleep>;
605 #address-cells = <1>;
606 #size-cells = <0>;
607 status = "disabled";
608 };
609
610 lpass: lpass@7708000 {
611 status = "disabled";
612 compatible = "qcom,lpass-cpu-apq8016";
613 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
614 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
615 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
616 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
617 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
618 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
619 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
620
621 clock-names = "ahbix-clk",
622 "pcnoc-mport-clk",
623 "pcnoc-sway-clk",
624 "mi2s-bit-clk0",
625 "mi2s-bit-clk1",
626 "mi2s-bit-clk2",
627 "mi2s-bit-clk3";
628 #sound-dai-cells = <1>;
629
630 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
631 interrupt-names = "lpass-irq-lpaif";
632 reg = <0x07708000 0x10000>;
633 reg-names = "lpass-lpaif";
634 };
635
636 lpass_codec: codec{
637 compatible = "qcom,msm8916-wcd-digital-codec";
638 reg = <0x0771c000 0x400>;
639 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
640 <&gcc GCC_CODEC_DIGCODEC_CLK>;
641 clock-names = "ahbix-clk", "mclk";
642 #sound-dai-cells = <1>;
643 };
644
645 sdhc_1: sdhci@7824000 {
646 compatible = "qcom,sdhci-msm-v4";
647 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
648 reg-names = "hc_mem", "core_mem";
649
650 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-names = "hc_irq", "pwr_irq";
652 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
653 <&gcc GCC_SDCC1_AHB_CLK>,
654 <&xo_board>;
655 clock-names = "core", "iface", "xo";
656 mmc-ddr-1_8v;
657 bus-width = <8>;
658 non-removable;
659 status = "disabled";
660 };
661
662 sdhc_2: sdhci@7864000 {
663 compatible = "qcom,sdhci-msm-v4";
664 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
665 reg-names = "hc_mem", "core_mem";
666
667 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
668 interrupt-names = "hc_irq", "pwr_irq";
669 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
670 <&gcc GCC_SDCC2_AHB_CLK>,
671 <&xo_board>;
672 clock-names = "core", "iface", "xo";
673 bus-width = <4>;
674 status = "disabled";
675 };
676
677 otg: usb@78d9000 {
678 compatible = "qcom,ci-hdrc";
679 reg = <0x78d9000 0x200>,
680 <0x78d9200 0x200>;
681 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
684 <&gcc GCC_USB_HS_SYSTEM_CLK>;
685 clock-names = "iface", "core";
686 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
687 assigned-clock-rates = <80000000>;
688 resets = <&gcc GCC_USB_HS_BCR>;
689 reset-names = "core";
690 phy_type = "ulpi";
691 dr_mode = "otg";
692 ahb-burst-config = <0>;
693 phy-names = "usb-phy";
694 phys = <&usb_hs_phy>;
695 status = "disabled";
696 #reset-cells = <1>;
697
698 ulpi {
699 usb_hs_phy: phy {
700 compatible = "qcom,usb-hs-phy-msm8916",
701 "qcom,usb-hs-phy";
702 #phy-cells = <0>;
703 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
704 clock-names = "ref", "sleep";
705 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
706 reset-names = "phy", "por";
707 qcom,init-seq = /bits/ 8 <0x0 0x44
708 0x1 0x6b 0x2 0x24 0x3 0x13>;
709 };
710 };
711 };
712
713 intc: interrupt-controller@b000000 {
714 compatible = "qcom,msm-qgic2";
715 interrupt-controller;
716 #interrupt-cells = <3>;
717 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
718 };
719
720 timer@b020000 {
721 #address-cells = <1>;
722 #size-cells = <1>;
723 ranges;
724 compatible = "arm,armv7-timer-mem";
725 reg = <0xb020000 0x1000>;
726 clock-frequency = <19200000>;
727
728 frame@b021000 {
729 frame-number = <0>;
730 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
732 reg = <0xb021000 0x1000>,
733 <0xb022000 0x1000>;
734 };
735
736 frame@b023000 {
737 frame-number = <1>;
738 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
739 reg = <0xb023000 0x1000>;
740 status = "disabled";
741 };
742
743 frame@b024000 {
744 frame-number = <2>;
745 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
746 reg = <0xb024000 0x1000>;
747 status = "disabled";
748 };
749
750 frame@b025000 {
751 frame-number = <3>;
752 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
753 reg = <0xb025000 0x1000>;
754 status = "disabled";
755 };
756
757 frame@b026000 {
758 frame-number = <4>;
759 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
760 reg = <0xb026000 0x1000>;
761 status = "disabled";
762 };
763
764 frame@b027000 {
765 frame-number = <5>;
766 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
767 reg = <0xb027000 0x1000>;
768 status = "disabled";
769 };
770
771 frame@b028000 {
772 frame-number = <6>;
773 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
774 reg = <0xb028000 0x1000>;
775 status = "disabled";
776 };
777 };
778
779 spmi_bus: spmi@200f000 {
780 compatible = "qcom,spmi-pmic-arb";
781 reg = <0x200f000 0x001000>,
782 <0x2400000 0x400000>,
783 <0x2c00000 0x400000>,
784 <0x3800000 0x200000>,
785 <0x200a000 0x002100>;
786 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
787 interrupt-names = "periph_irq";
788 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
789 qcom,ee = <0>;
790 qcom,channel = <0>;
791 #address-cells = <2>;
792 #size-cells = <0>;
793 interrupt-controller;
794 #interrupt-cells = <4>;
795 };
796
797 rng@22000 {
798 compatible = "qcom,prng";
799 reg = <0x00022000 0x200>;
800 clocks = <&gcc GCC_PRNG_AHB_CLK>;
801 clock-names = "core";
802 };
803
804 qfprom: qfprom@5c000 {
805 compatible = "qcom,qfprom";
806 reg = <0x5c000 0x1000>;
807 #address-cells = <1>;
808 #size-cells = <1>;
809 tsens_caldata: caldata@d0 {
810 reg = <0xd0 0x8>;
811 };
812 tsens_calsel: calsel@ec {
813 reg = <0xec 0x4>;
814 };
815 };
816
817 tsens: thermal-sensor@4a9000 {
818 compatible = "qcom,msm8916-tsens";
819 reg = <0x4a9000 0x1000>, /* TM */
820 <0x4a8000 0x1000>; /* SROT */
821 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
822 nvmem-cell-names = "calib", "calib_sel";
823 #qcom,sensors = <5>;
824 #thermal-sensor-cells = <1>;
825 };
826
827 apps_iommu: iommu@1ef0000 {
828 #address-cells = <1>;
829 #size-cells = <1>;
830 #iommu-cells = <1>;
831 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
832 ranges = <0 0x1e20000 0x40000>;
833 reg = <0x1ef0000 0x3000>;
834 clocks = <&gcc GCC_SMMU_CFG_CLK>,
835 <&gcc GCC_APSS_TCU_CLK>;
836 clock-names = "iface", "bus";
837 qcom,iommu-secure-id = <17>;
838
839 // vfe:
840 iommu-ctx@3000 {
841 compatible = "qcom,msm-iommu-v1-sec";
842 reg = <0x3000 0x1000>;
843 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
844 };
845
846 // mdp_0:
847 iommu-ctx@4000 {
848 compatible = "qcom,msm-iommu-v1-ns";
849 reg = <0x4000 0x1000>;
850 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
851 };
852
853 // venus_ns:
854 iommu-ctx@5000 {
855 compatible = "qcom,msm-iommu-v1-sec";
856 reg = <0x5000 0x1000>;
857 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
858 };
859 };
860
861 gpu_iommu: iommu@1f08000 {
862 #address-cells = <1>;
863 #size-cells = <1>;
864 #iommu-cells = <1>;
865 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
866 ranges = <0 0x1f08000 0x10000>;
867 clocks = <&gcc GCC_SMMU_CFG_CLK>,
868 <&gcc GCC_GFX_TCU_CLK>;
869 clock-names = "iface", "bus";
870 qcom,iommu-secure-id = <18>;
871
872 // gfx3d_user:
873 iommu-ctx@1000 {
874 compatible = "qcom,msm-iommu-v1-ns";
875 reg = <0x1000 0x1000>;
876 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
877 };
878
879 // gfx3d_priv:
880 iommu-ctx@2000 {
881 compatible = "qcom,msm-iommu-v1-ns";
882 reg = <0x2000 0x1000>;
883 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
884 };
885 };
886
887 gpu@1c00000 {
888 compatible = "qcom,adreno-306.0", "qcom,adreno";
889 reg = <0x01c00000 0x20000>;
890 reg-names = "kgsl_3d0_reg_memory";
891 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "kgsl_3d0_irq";
893 clock-names =
894 "core",
895 "iface",
896 "mem",
897 "mem_iface",
898 "alt_mem_iface",
899 "gfx3d";
900 clocks =
901 <&gcc GCC_OXILI_GFX3D_CLK>,
902 <&gcc GCC_OXILI_AHB_CLK>,
903 <&gcc GCC_OXILI_GMEM_CLK>,
904 <&gcc GCC_BIMC_GFX_CLK>,
905 <&gcc GCC_BIMC_GPU_CLK>,
906 <&gcc GFX3D_CLK_SRC>;
907 power-domains = <&gcc OXILI_GDSC>;
908 operating-points-v2 = <&gpu_opp_table>;
909 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
910 };
911
912 mdss: mdss@1a00000 {
913 compatible = "qcom,mdss";
914 reg = <0x1a00000 0x1000>,
915 <0x1ac8000 0x3000>;
916 reg-names = "mdss_phys", "vbif_phys";
917
918 power-domains = <&gcc MDSS_GDSC>;
919
920 clocks = <&gcc GCC_MDSS_AHB_CLK>,
921 <&gcc GCC_MDSS_AXI_CLK>,
922 <&gcc GCC_MDSS_VSYNC_CLK>;
923 clock-names = "iface",
924 "bus",
925 "vsync";
926
927 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
928
929 interrupt-controller;
930 #interrupt-cells = <1>;
931
932 #address-cells = <1>;
933 #size-cells = <1>;
934 ranges;
935
936 mdp: mdp@1a01000 {
937 compatible = "qcom,mdp5";
938 reg = <0x1a01000 0x89000>;
939 reg-names = "mdp_phys";
940
941 interrupt-parent = <&mdss>;
942 interrupts = <0 0>;
943
944 clocks = <&gcc GCC_MDSS_AHB_CLK>,
945 <&gcc GCC_MDSS_AXI_CLK>,
946 <&gcc GCC_MDSS_MDP_CLK>,
947 <&gcc GCC_MDSS_VSYNC_CLK>;
948 clock-names = "iface",
949 "bus",
950 "core",
951 "vsync";
952
953 iommus = <&apps_iommu 4>;
954
955 ports {
956 #address-cells = <1>;
957 #size-cells = <0>;
958
959 port@0 {
960 reg = <0>;
961 mdp5_intf1_out: endpoint {
962 remote-endpoint = <&dsi0_in>;
963 };
964 };
965 };
966 };
967
968 dsi0: dsi@1a98000 {
969 compatible = "qcom,mdss-dsi-ctrl";
970 reg = <0x1a98000 0x25c>;
971 reg-names = "dsi_ctrl";
972
973 interrupt-parent = <&mdss>;
974 interrupts = <4 0>;
975
976 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
977 <&gcc PCLK0_CLK_SRC>;
978 assigned-clock-parents = <&dsi_phy0 0>,
979 <&dsi_phy0 1>;
980
981 clocks = <&gcc GCC_MDSS_MDP_CLK>,
982 <&gcc GCC_MDSS_AHB_CLK>,
983 <&gcc GCC_MDSS_AXI_CLK>,
984 <&gcc GCC_MDSS_BYTE0_CLK>,
985 <&gcc GCC_MDSS_PCLK0_CLK>,
986 <&gcc GCC_MDSS_ESC0_CLK>;
987 clock-names = "mdp_core",
988 "iface",
989 "bus",
990 "byte",
991 "pixel",
992 "core";
993 phys = <&dsi_phy0>;
994 phy-names = "dsi-phy";
995
996 ports {
997 #address-cells = <1>;
998 #size-cells = <0>;
999
1000 port@0 {
1001 reg = <0>;
1002 dsi0_in: endpoint {
1003 remote-endpoint = <&mdp5_intf1_out>;
1004 };
1005 };
1006
1007 port@1 {
1008 reg = <1>;
1009 dsi0_out: endpoint {
1010 };
1011 };
1012 };
1013 };
1014
1015 dsi_phy0: dsi-phy@1a98300 {
1016 compatible = "qcom,dsi-phy-28nm-lp";
1017 reg = <0x1a98300 0xd4>,
1018 <0x1a98500 0x280>,
1019 <0x1a98780 0x30>;
1020 reg-names = "dsi_pll",
1021 "dsi_phy",
1022 "dsi_phy_regulator";
1023
1024 #clock-cells = <1>;
1025 #phy-cells = <0>;
1026
1027 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1028 <&xo_board>;
1029 clock-names = "iface", "ref";
1030 };
1031 };
1032
1033
1034 hexagon@4080000 {
1035 compatible = "qcom,q6v5-pil";
1036 reg = <0x04080000 0x100>,
1037 <0x04020000 0x040>;
1038
1039 reg-names = "qdsp6", "rmb";
1040
1041 interrupts-extended = <&intc 0 24 1>,
1042 <&hexagon_smp2p_in 0 0>,
1043 <&hexagon_smp2p_in 1 0>,
1044 <&hexagon_smp2p_in 2 0>,
1045 <&hexagon_smp2p_in 3 0>;
1046 interrupt-names = "wdog", "fatal", "ready",
1047 "handover", "stop-ack";
1048
1049 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1050 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1051 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1052 <&xo_board>;
1053 clock-names = "iface", "bus", "mem", "xo";
1054
1055 qcom,smem-states = <&hexagon_smp2p_out 0>;
1056 qcom,smem-state-names = "stop";
1057
1058 resets = <&scm 0>;
1059 reset-names = "mss_restart";
1060
1061 cx-supply = <&pm8916_s1>;
1062 mx-supply = <&pm8916_l3>;
1063 pll-supply = <&pm8916_l7>;
1064
1065 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1066
1067 status = "disabled";
1068
1069 mba {
1070 memory-region = <&mba_mem>;
1071 };
1072
1073 mpss {
1074 memory-region = <&mpss_mem>;
1075 };
1076
1077 smd-edge {
1078 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1079
1080 qcom,smd-edge = <0>;
1081 qcom,ipc = <&apcs 8 12>;
1082 qcom,remote-pid = <1>;
1083
1084 label = "hexagon";
1085 };
1086 };
1087
1088 pronto: wcnss@a21b000 {
1089 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1090 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1091 reg-names = "ccu", "dxe", "pmu";
1092
1093 memory-region = <&wcnss_mem>;
1094
1095 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1096 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1097 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1098 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1099 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1100 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1101
1102 vddmx-supply = <&pm8916_l3>;
1103 vddpx-supply = <&pm8916_l7>;
1104
1105 qcom,state = <&wcnss_smp2p_out 0>;
1106 qcom,state-names = "stop";
1107
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&wcnss_pin_a>;
1110
1111 status = "disabled";
1112
1113 iris {
1114 compatible = "qcom,wcn3620";
1115
1116 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1117 clock-names = "xo";
1118
1119 vddxo-supply = <&pm8916_l7>;
1120 vddrfa-supply = <&pm8916_s3>;
1121 vddpa-supply = <&pm8916_l9>;
1122 vdddig-supply = <&pm8916_l5>;
1123 };
1124
1125 smd-edge {
1126 interrupts = <0 142 1>;
1127
1128 qcom,ipc = <&apcs 8 17>;
1129 qcom,smd-edge = <6>;
1130 qcom,remote-pid = <4>;
1131
1132 label = "pronto";
1133
1134 wcnss {
1135 compatible = "qcom,wcnss";
1136 qcom,smd-channels = "WCNSS_CTRL";
1137
1138 qcom,mmio = <&pronto>;
1139
1140 bt {
1141 compatible = "qcom,wcnss-bt";
1142 };
1143
1144 wifi {
1145 compatible = "qcom,wcnss-wlan";
1146
1147 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1148 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1149 interrupt-names = "tx", "rx";
1150
1151 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1152 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1153 };
1154 };
1155 };
1156 };
1157
1158 tpiu@820000 {
1159 compatible = "arm,coresight-tpiu", "arm,primecell";
1160 reg = <0x820000 0x1000>;
1161
1162 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1163 clock-names = "apb_pclk", "atclk";
1164
1165 in-ports {
1166 port {
1167 tpiu_in: endpoint {
1168 remote-endpoint = <&replicator_out1>;
1169 };
1170 };
1171 };
1172 };
1173
1174 funnel@821000 {
1175 compatible = "arm,coresight-funnel", "arm,primecell";
1176 reg = <0x821000 0x1000>;
1177
1178 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1179 clock-names = "apb_pclk", "atclk";
1180
1181 in-ports {
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1184
1185 /*
1186 * Not described input ports:
1187 * 0 - connected to Resource and Power Manger CPU ETM
1188 * 1 - not-connected
1189 * 2 - connected to Modem CPU ETM
1190 * 3 - not-connected
1191 * 5 - not-connected
1192 * 6 - connected trought funnel to Wireless CPU ETM
1193 * 7 - connected to STM component
1194 */
1195
1196 port@4 {
1197 reg = <4>;
1198 funnel0_in4: endpoint {
1199 remote-endpoint = <&funnel1_out>;
1200 };
1201 };
1202 };
1203
1204 out-ports {
1205 port {
1206 funnel0_out: endpoint {
1207 remote-endpoint = <&etf_in>;
1208 };
1209 };
1210 };
1211 };
1212
1213 replicator@824000 {
1214 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1215 reg = <0x824000 0x1000>;
1216
1217 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1218 clock-names = "apb_pclk", "atclk";
1219
1220 out-ports {
1221 #address-cells = <1>;
1222 #size-cells = <0>;
1223
1224 port@0 {
1225 reg = <0>;
1226 replicator_out0: endpoint {
1227 remote-endpoint = <&etr_in>;
1228 };
1229 };
1230 port@1 {
1231 reg = <1>;
1232 replicator_out1: endpoint {
1233 remote-endpoint = <&tpiu_in>;
1234 };
1235 };
1236 };
1237
1238 in-ports {
1239 port {
1240 replicator_in: endpoint {
1241 remote-endpoint = <&etf_out>;
1242 };
1243 };
1244 };
1245 };
1246
1247 etf@825000 {
1248 compatible = "arm,coresight-tmc", "arm,primecell";
1249 reg = <0x825000 0x1000>;
1250
1251 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1252 clock-names = "apb_pclk", "atclk";
1253
1254 in-ports {
1255 port {
1256 etf_in: endpoint {
1257 remote-endpoint = <&funnel0_out>;
1258 };
1259 };
1260 };
1261
1262 out-ports {
1263 port {
1264 etf_out: endpoint {
1265 remote-endpoint = <&replicator_in>;
1266 };
1267 };
1268 };
1269 };
1270
1271 etr@826000 {
1272 compatible = "arm,coresight-tmc", "arm,primecell";
1273 reg = <0x826000 0x1000>;
1274
1275 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1276 clock-names = "apb_pclk", "atclk";
1277
1278 in-ports {
1279 port {
1280 etr_in: endpoint {
1281 remote-endpoint = <&replicator_out0>;
1282 };
1283 };
1284 };
1285 };
1286
1287 funnel@841000 { /* APSS funnel only 4 inputs are used */
1288 compatible = "arm,coresight-funnel", "arm,primecell";
1289 reg = <0x841000 0x1000>;
1290
1291 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1292 clock-names = "apb_pclk", "atclk";
1293
1294 in-ports {
1295 #address-cells = <1>;
1296 #size-cells = <0>;
1297
1298 port@0 {
1299 reg = <0>;
1300 funnel1_in0: endpoint {
1301 remote-endpoint = <&etm0_out>;
1302 };
1303 };
1304 port@1 {
1305 reg = <1>;
1306 funnel1_in1: endpoint {
1307 remote-endpoint = <&etm1_out>;
1308 };
1309 };
1310 port@2 {
1311 reg = <2>;
1312 funnel1_in2: endpoint {
1313 remote-endpoint = <&etm2_out>;
1314 };
1315 };
1316 port@3 {
1317 reg = <3>;
1318 funnel1_in3: endpoint {
1319 remote-endpoint = <&etm3_out>;
1320 };
1321 };
1322 };
1323
1324 out-ports {
1325 port {
1326 funnel1_out: endpoint {
1327 remote-endpoint = <&funnel0_in4>;
1328 };
1329 };
1330 };
1331 };
1332
1333 debug@850000 {
1334 compatible = "arm,coresight-cpu-debug","arm,primecell";
1335 reg = <0x850000 0x1000>;
1336 clocks = <&rpmcc RPM_QDSS_CLK>;
1337 clock-names = "apb_pclk";
1338 cpu = <&CPU0>;
1339 };
1340
1341 debug@852000 {
1342 compatible = "arm,coresight-cpu-debug","arm,primecell";
1343 reg = <0x852000 0x1000>;
1344 clocks = <&rpmcc RPM_QDSS_CLK>;
1345 clock-names = "apb_pclk";
1346 cpu = <&CPU1>;
1347 };
1348
1349 debug@854000 {
1350 compatible = "arm,coresight-cpu-debug","arm,primecell";
1351 reg = <0x854000 0x1000>;
1352 clocks = <&rpmcc RPM_QDSS_CLK>;
1353 clock-names = "apb_pclk";
1354 cpu = <&CPU2>;
1355 };
1356
1357 debug@856000 {
1358 compatible = "arm,coresight-cpu-debug","arm,primecell";
1359 reg = <0x856000 0x1000>;
1360 clocks = <&rpmcc RPM_QDSS_CLK>;
1361 clock-names = "apb_pclk";
1362 cpu = <&CPU3>;
1363 };
1364
1365 etm@85c000 {
1366 compatible = "arm,coresight-etm4x", "arm,primecell";
1367 reg = <0x85c000 0x1000>;
1368
1369 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1370 clock-names = "apb_pclk", "atclk";
1371
1372 cpu = <&CPU0>;
1373
1374 out-ports {
1375 port {
1376 etm0_out: endpoint {
1377 remote-endpoint = <&funnel1_in0>;
1378 };
1379 };
1380 };
1381 };
1382
1383 etm@85d000 {
1384 compatible = "arm,coresight-etm4x", "arm,primecell";
1385 reg = <0x85d000 0x1000>;
1386
1387 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1388 clock-names = "apb_pclk", "atclk";
1389
1390 cpu = <&CPU1>;
1391
1392 out-ports {
1393 port {
1394 etm1_out: endpoint {
1395 remote-endpoint = <&funnel1_in1>;
1396 };
1397 };
1398 };
1399 };
1400
1401 etm@85e000 {
1402 compatible = "arm,coresight-etm4x", "arm,primecell";
1403 reg = <0x85e000 0x1000>;
1404
1405 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1406 clock-names = "apb_pclk", "atclk";
1407
1408 cpu = <&CPU2>;
1409
1410 out-ports {
1411 port {
1412 etm2_out: endpoint {
1413 remote-endpoint = <&funnel1_in2>;
1414 };
1415 };
1416 };
1417 };
1418
1419 etm@85f000 {
1420 compatible = "arm,coresight-etm4x", "arm,primecell";
1421 reg = <0x85f000 0x1000>;
1422
1423 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1424 clock-names = "apb_pclk", "atclk";
1425
1426 cpu = <&CPU3>;
1427
1428 out-ports {
1429 port {
1430 etm3_out: endpoint {
1431 remote-endpoint = <&funnel1_in3>;
1432 };
1433 };
1434 };
1435 };
1436
1437 venus: video-codec@1d00000 {
1438 compatible = "qcom,msm8916-venus";
1439 reg = <0x01d00000 0xff000>;
1440 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1441 power-domains = <&gcc VENUS_GDSC>;
1442 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1443 <&gcc GCC_VENUS0_AHB_CLK>,
1444 <&gcc GCC_VENUS0_AXI_CLK>;
1445 clock-names = "core", "iface", "bus";
1446 iommus = <&apps_iommu 5>;
1447 memory-region = <&venus_mem>;
1448 status = "okay";
1449
1450 video-decoder {
1451 compatible = "venus-decoder";
1452 };
1453
1454 video-encoder {
1455 compatible = "venus-encoder";
1456 };
1457 };
1458
1459 camss: camss@1b00000 {
1460 compatible = "qcom,msm8916-camss";
1461 reg = <0x1b0ac00 0x200>,
1462 <0x1b00030 0x4>,
1463 <0x1b0b000 0x200>,
1464 <0x1b00038 0x4>,
1465 <0x1b08000 0x100>,
1466 <0x1b08400 0x100>,
1467 <0x1b0a000 0x500>,
1468 <0x1b00020 0x10>,
1469 <0x1b10000 0x1000>;
1470 reg-names = "csiphy0",
1471 "csiphy0_clk_mux",
1472 "csiphy1",
1473 "csiphy1_clk_mux",
1474 "csid0",
1475 "csid1",
1476 "ispif",
1477 "csi_clk_mux",
1478 "vfe0";
1479 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1480 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1481 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1482 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1483 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1484 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1485 interrupt-names = "csiphy0",
1486 "csiphy1",
1487 "csid0",
1488 "csid1",
1489 "ispif",
1490 "vfe0";
1491 power-domains = <&gcc VFE_GDSC>;
1492 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1493 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1494 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1495 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1496 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1497 <&gcc GCC_CAMSS_CSI0_CLK>,
1498 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1499 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1500 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1501 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1502 <&gcc GCC_CAMSS_CSI1_CLK>,
1503 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1504 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1505 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1506 <&gcc GCC_CAMSS_AHB_CLK>,
1507 <&gcc GCC_CAMSS_VFE0_CLK>,
1508 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1509 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1510 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1511 clock-names = "top_ahb",
1512 "ispif_ahb",
1513 "csiphy0_timer",
1514 "csiphy1_timer",
1515 "csi0_ahb",
1516 "csi0",
1517 "csi0_phy",
1518 "csi0_pix",
1519 "csi0_rdi",
1520 "csi1_ahb",
1521 "csi1",
1522 "csi1_phy",
1523 "csi1_pix",
1524 "csi1_rdi",
1525 "ahb",
1526 "vfe0",
1527 "csi_vfe0",
1528 "vfe_ahb",
1529 "vfe_axi";
1530 vdda-supply = <&pm8916_l2>;
1531 iommus = <&apps_iommu 3>;
1532 status = "disabled";
1533 ports {
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1536 };
1537 };
1538 };
1539
1540 smd {
1541 compatible = "qcom,smd";
1542
1543 rpm {
1544 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1545 qcom,ipc = <&apcs 8 0>;
1546 qcom,smd-edge = <15>;
1547
1548 rpm_requests {
1549 compatible = "qcom,rpm-msm8916";
1550 qcom,smd-channels = "rpm_requests";
1551
1552 rpmcc: qcom,rpmcc {
1553 compatible = "qcom,rpmcc-msm8916";
1554 #clock-cells = <1>;
1555 };
1556
1557 smd_rpm_regulators: pm8916-regulators {
1558 compatible = "qcom,rpm-pm8916-regulators";
1559
1560 pm8916_s1: s1 {};
1561 pm8916_s3: s3 {};
1562 pm8916_s4: s4 {};
1563
1564 pm8916_l1: l1 {};
1565 pm8916_l2: l2 {};
1566 pm8916_l3: l3 {};
1567 pm8916_l4: l4 {};
1568 pm8916_l5: l5 {};
1569 pm8916_l6: l6 {};
1570 pm8916_l7: l7 {};
1571 pm8916_l8: l8 {};
1572 pm8916_l9: l9 {};
1573 pm8916_l10: l10 {};
1574 pm8916_l11: l11 {};
1575 pm8916_l12: l12 {};
1576 pm8916_l13: l13 {};
1577 pm8916_l14: l14 {};
1578 pm8916_l15: l15 {};
1579 pm8916_l16: l16 {};
1580 pm8916_l17: l17 {};
1581 pm8916_l18: l18 {};
1582 };
1583 };
1584 };
1585 };
1586
1587 hexagon-smp2p {
1588 compatible = "qcom,smp2p";
1589 qcom,smem = <435>, <428>;
1590
1591 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1592
1593 qcom,ipc = <&apcs 8 14>;
1594
1595 qcom,local-pid = <0>;
1596 qcom,remote-pid = <1>;
1597
1598 hexagon_smp2p_out: master-kernel {
1599 qcom,entry-name = "master-kernel";
1600
1601 #qcom,smem-state-cells = <1>;
1602 };
1603
1604 hexagon_smp2p_in: slave-kernel {
1605 qcom,entry-name = "slave-kernel";
1606
1607 interrupt-controller;
1608 #interrupt-cells = <2>;
1609 };
1610 };
1611
1612 wcnss-smp2p {
1613 compatible = "qcom,smp2p";
1614 qcom,smem = <451>, <431>;
1615
1616 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1617
1618 qcom,ipc = <&apcs 8 18>;
1619
1620 qcom,local-pid = <0>;
1621 qcom,remote-pid = <4>;
1622
1623 wcnss_smp2p_out: master-kernel {
1624 qcom,entry-name = "master-kernel";
1625
1626 #qcom,smem-state-cells = <1>;
1627 };
1628
1629 wcnss_smp2p_in: slave-kernel {
1630 qcom,entry-name = "slave-kernel";
1631
1632 interrupt-controller;
1633 #interrupt-cells = <2>;
1634 };
1635 };
1636
1637 smsm {
1638 compatible = "qcom,smsm";
1639
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642
1643 qcom,ipc-1 = <&apcs 8 13>;
1644 qcom,ipc-3 = <&apcs 8 19>;
1645
1646 apps_smsm: apps@0 {
1647 reg = <0>;
1648
1649 #qcom,smem-state-cells = <1>;
1650 };
1651
1652 hexagon_smsm: hexagon@1 {
1653 reg = <1>;
1654 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1655
1656 interrupt-controller;
1657 #interrupt-cells = <2>;
1658 };
1659
1660 wcnss_smsm: wcnss@6 {
1661 reg = <6>;
1662 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1663
1664 interrupt-controller;
1665 #interrupt-cells = <2>;
1666 };
1667 };
1668 };
1669
1670 #include "msm8916-pins.dtsi"
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