arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16
  17 / {
  18         model = "Qualcomm Technologies, Inc. MSM8996";
  19
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /* We expect the bootloader to fill in the reg */
  30                 reg = <0 0 0 0>;
  31         };
  32
  33         reserved-memory {
  34                 #address-cells = <2>;
  35                 #size-cells = <2>;
  36                 ranges;
  37
  38                 mba_region: mba@91500000 {
  39                         reg = <0x0 0x91500000 0x0 0x200000>;
  40                         no-map;
  41                 };
  42
  43                 slpi_region: slpi@90b00000 {
  44                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  45                         no-map;
  46                 };
  47
  48                 venus_region: venus@90400000 {
  49                         reg = <0x0 0x90400000 0x0 0x700000>;
  50                         no-map;
  51                 };
  52
  53                 adsp_region: adsp@8ea00000 {
  54                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  55                         no-map;
  56                 };
  57
  58                 mpss_region: mpss@88800000 {
  59                         reg = <0x0 0x88800000 0x0 0x6200000>;
  60                         no-map;
  61                 };
  62
  63                 smem_mem: smem-mem@86000000 {
  64                         reg = <0x0 0x86000000 0x0 0x200000>;
  65                         no-map;
  66                 };
  67
  68                 memory@85800000 {
  69                         reg = <0x0 0x85800000 0x0 0x800000>;
  70                         no-map;
  71                 };
  72
  73                 memory@86200000 {
  74                         reg = <0x0 0x86200000 0x0 0x2600000>;
  75                         no-map;
  76                 };
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 CPU0: cpu@0 {
  84                         device_type = "cpu";
  85                         compatible = "qcom,kryo";
  86                         reg = <0x0 0x0>;
  87                         enable-method = "psci";
  88                         next-level-cache = <&L2_0>;
  89                         L2_0: l2-cache {
  90                               compatible = "cache";
  91                               cache-level = <2>;
  92                         };
  93                 };
  94
  95                 CPU1: cpu@1 {
  96                         device_type = "cpu";
  97                         compatible = "qcom,kryo";
  98                         reg = <0x0 0x1>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&L2_0>;
 101                 };
 102
 103                 CPU2: cpu@100 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo";
 106                         reg = <0x0 0x100>;
 107                         enable-method = "psci";
 108                         next-level-cache = <&L2_1>;
 109                         L2_1: l2-cache {
 110                               compatible = "cache";
 111                               cache-level = <2>;
 112                         };
 113                 };
 114
 115                 CPU3: cpu@101 {
 116                         device_type = "cpu";
 117                         compatible = "qcom,kryo";
 118                         reg = <0x0 0x101>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&L2_1>;
 121                 };
 122
 123                 cpu-map {
 124                         cluster0 {
 125                                 core0 {
 126                                         cpu = <&CPU0>;
 127                                 };
 128
 129                                 core1 {
 130                                         cpu = <&CPU1>;
 131                                 };
 132                         };
 133
 134                         cluster1 {
 135                                 core0 {
 136                                         cpu = <&CPU2>;
 137                                 };
 138
 139                                 core1 {
 140                                         cpu = <&CPU3>;
 141                                 };
 142                         };
 143                 };
 144         };
 145
 146         thermal-zones {
 147                 cpu-thermal0 {
 148                         polling-delay-passive = <250>;
 149                         polling-delay = <1000>;
 150
 151                         thermal-sensors = <&tsens0 3>;
 152
 153                         trips {
 154                                 cpu_alert0: trip0 {
 155                                         temperature = <75000>;
 156                                         hysteresis = <2000>;
 157                                         type = "passive";
 158                                 };
 159
 160                                 cpu_crit0: trip1 {
 161                                         temperature = <110000>;
 162                                         hysteresis = <2000>;
 163                                         type = "critical";
 164                                 };
 165                         };
 166                 };
 167
 168                 cpu-thermal1 {
 169                         polling-delay-passive = <250>;
 170                         polling-delay = <1000>;
 171
 172                         thermal-sensors = <&tsens0 5>;
 173
 174                         trips {
 175                                 cpu_alert1: trip0 {
 176                                         temperature = <75000>;
 177                                         hysteresis = <2000>;
 178                                         type = "passive";
 179                                 };
 180
 181                                 cpu_crit1: trip1 {
 182                                         temperature = <110000>;
 183                                         hysteresis = <2000>;
 184                                         type = "critical";
 185                                 };
 186                         };
 187                 };
 188
 189                 cpu-thermal2 {
 190                         polling-delay-passive = <250>;
 191                         polling-delay = <1000>;
 192
 193                         thermal-sensors = <&tsens0 8>;
 194
 195                         trips {
 196                                 cpu_alert2: trip0 {
 197                                         temperature = <75000>;
 198                                         hysteresis = <2000>;
 199                                         type = "passive";
 200                                 };
 201
 202                                 cpu_crit2: trip1 {
 203                                         temperature = <110000>;
 204                                         hysteresis = <2000>;
 205                                         type = "critical";
 206                                 };
 207                         };
 208                 };
 209
 210                 cpu-thermal3 {
 211                         polling-delay-passive = <250>;
 212                         polling-delay = <1000>;
 213
 214                         thermal-sensors = <&tsens0 10>;
 215
 216                         trips {
 217                                 cpu_alert3: trip0 {
 218                                         temperature = <75000>;
 219                                         hysteresis = <2000>;
 220                                         type = "passive";
 221                                 };
 222
 223                                 cpu_crit3: trip1 {
 224                                         temperature = <110000>;
 225                                         hysteresis = <2000>;
 226                                         type = "critical";
 227                                 };
 228                         };
 229                 };
 230         };
 231
 232         timer {
 233                 compatible = "arm,armv8-timer";
 234                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 235                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 236                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 237                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 238         };
 239
 240         clocks {
 241                 xo_board: xo_board {
 242                         compatible = "fixed-clock";
 243                         #clock-cells = <0>;
 244                         clock-frequency = <19200000>;
 245                         clock-output-names = "xo_board";
 246                 };
 247
 248                 sleep_clk: sleep_clk {
 249                         compatible = "fixed-clock";
 250                         #clock-cells = <0>;
 251                         clock-frequency = <32764>;
 252                         clock-output-names = "sleep_clk";
 253                 };
 254         };
 255
 256         psci {
 257                 compatible = "arm,psci-1.0";
 258                 method = "smc";
 259         };
 260
 261         tcsr_mutex: hwlock {
 262                 compatible = "qcom,tcsr-mutex";
 263                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 264                 #hwlock-cells = <1>;
 265         };
 266
 267         smem {
 268                 compatible = "qcom,smem";
 269                 memory-region = <&smem_mem>;
 270                 hwlocks = <&tcsr_mutex 3>;
 271         };
 272
 273         soc: soc {
 274                 #address-cells = <1>;
 275                 #size-cells = <1>;
 276                 ranges = <0 0 0 0xffffffff>;
 277                 compatible = "simple-bus";
 278
 279                 tcsr_mutex_regs: syscon@740000 {
 280                         compatible = "syscon";
 281                         reg = <0x740000 0x20000>;
 282                 };
 283
 284                 intc: interrupt-controller@9bc0000 {
 285                         compatible = "arm,gic-v3";
 286                         #interrupt-cells = <3>;
 287                         interrupt-controller;
 288                         #redistributor-regions = <1>;
 289                         redistributor-stride = <0x0 0x40000>;
 290                         reg = <0x09bc0000 0x10000>,
 291                               <0x09c00000 0x100000>;
 292                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 293                 };
 294
 295                 apcs: syscon@9820000 {
 296                         compatible = "syscon";
 297                         reg = <0x9820000 0x1000>;
 298                 };
 299
 300                 gcc: clock-controller@300000 {
 301                         compatible = "qcom,gcc-msm8996";
 302                         #clock-cells = <1>;
 303                         #reset-cells = <1>;
 304                         #power-domain-cells = <1>;
 305                         reg = <0x300000 0x90000>;
 306                 };
 307
 308                 blsp1_spi0: spi@07575000 {
 309                         compatible = "qcom,spi-qup-v2.2.1";
 310                         reg = <0x07575000 0x600>;
 311                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 313                                  <&gcc GCC_BLSP1_AHB_CLK>;
 314                         clock-names = "core", "iface";
 315                         pinctrl-names = "default", "sleep";
 316                         pinctrl-0 = <&blsp1_spi0_default>;
 317                         pinctrl-1 = <&blsp1_spi0_sleep>;
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                         status = "disabled";
 321                 };
 322
 323                 blsp2_i2c0: i2c@075b5000 {
 324                         compatible = "qcom,i2c-qup-v2.2.1";
 325                         reg = <0x075b5000 0x1000>;
 326                         interrupts = <GIC_SPI 101 0>;
 327                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 328                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 329                         clock-names = "iface", "core";
 330                         pinctrl-names = "default", "sleep";
 331                         pinctrl-0 = <&blsp2_i2c0_default>;
 332                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         status = "disabled";
 336                 };
 337
 338                 tsens0: thermal-sensor@4a8000 {
 339                         compatible = "qcom,msm8996-tsens";
 340                         reg = <0x4a8000 0x2000>;
 341                         #thermal-sensor-cells = <1>;
 342                 };
 343
 344                 blsp2_uart1: serial@75b0000 {
 345                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 346                         reg = <0x75b0000 0x1000>;
 347                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 348                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 349                                  <&gcc GCC_BLSP2_AHB_CLK>;
 350                         clock-names = "core", "iface";
 351                         status = "disabled";
 352                 };
 353
 354                 blsp2_i2c1: i2c@075b6000 {
 355                         compatible = "qcom,i2c-qup-v2.2.1";
 356                         reg = <0x075b6000 0x1000>;
 357                         interrupts = <GIC_SPI 102 0>;
 358                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 359                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 360                         clock-names = "iface", "core";
 361                         pinctrl-names = "default", "sleep";
 362                         pinctrl-0 = <&blsp2_i2c1_default>;
 363                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         status = "disabled";
 367                 };
 368
 369                 blsp2_uart2: serial@75b1000 {
 370                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 371                         reg = <0x075b1000 0x1000>;
 372                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 373                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 374                                  <&gcc GCC_BLSP2_AHB_CLK>;
 375                         clock-names = "core", "iface";
 376                         status = "disabled";
 377                 };
 378
 379                 blsp1_i2c2: i2c@07577000 {
 380                         compatible = "qcom,i2c-qup-v2.2.1";
 381                         reg = <0x07577000 0x1000>;
 382                         interrupts = <GIC_SPI 97 0>;
 383                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 384                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 385                         clock-names = "iface", "core";
 386                         pinctrl-names = "default", "sleep";
 387                         pinctrl-0 = <&blsp1_i2c2_default>;
 388                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         status = "disabled";
 392                 };
 393
 394                 blsp2_spi5: spi@075ba000{
 395                         compatible = "qcom,spi-qup-v2.2.1";
 396                         reg = <0x075ba000 0x600>;
 397                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
 399                                  <&gcc GCC_BLSP2_AHB_CLK>;
 400                         clock-names = "core", "iface";
 401                         pinctrl-names = "default", "sleep";
 402                         pinctrl-0 = <&blsp2_spi5_default>;
 403                         pinctrl-1 = <&blsp2_spi5_sleep>;
 404                         #address-cells = <1>;
 405                         #size-cells = <0>;
 406                         status = "disabled";
 407                 };
 408
 409                 sdhc2: sdhci@74a4900 {
 410                          status = "disabled";
 411                          compatible = "qcom,sdhci-msm-v4";
 412                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 413                          reg-names = "hc_mem", "core_mem";
 414
 415                          interrupts = <0 125 0>, <0 221 0>;
 416                          interrupt-names = "hc_irq", "pwr_irq";
 417
 418                          clock-names = "iface", "core", "xo";
 419                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 420                          <&gcc GCC_SDCC2_APPS_CLK>,
 421                          <&xo_board>;
 422                          bus-width = <4>;
 423                  };
 424
 425                 msmgpio: pinctrl@1010000 {
 426                         compatible = "qcom,msm8996-pinctrl";
 427                         reg = <0x01010000 0x300000>;
 428                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 429                         gpio-controller;
 430                         #gpio-cells = <2>;
 431                         interrupt-controller;
 432                         #interrupt-cells = <2>;
 433                 };
 434
 435                 timer@09840000 {
 436                         #address-cells = <1>;
 437                         #size-cells = <1>;
 438                         ranges;
 439                         compatible = "arm,armv7-timer-mem";
 440                         reg = <0x09840000 0x1000>;
 441                         clock-frequency = <19200000>;
 442
 443                         frame@9850000 {
 444                                 frame-number = <0>;
 445                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 446                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 447                                 reg = <0x09850000 0x1000>,
 448                                       <0x09860000 0x1000>;
 449                         };
 450
 451                         frame@9870000 {
 452                                 frame-number = <1>;
 453                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 454                                 reg = <0x09870000 0x1000>;
 455                                 status = "disabled";
 456                         };
 457
 458                         frame@9880000 {
 459                                 frame-number = <2>;
 460                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 461                                 reg = <0x09880000 0x1000>;
 462                                 status = "disabled";
 463                         };
 464
 465                         frame@9890000 {
 466                                 frame-number = <3>;
 467                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 468                                 reg = <0x09890000 0x1000>;
 469                                 status = "disabled";
 470                         };
 471
 472                         frame@98a0000 {
 473                                 frame-number = <4>;
 474                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 475                                 reg = <0x098a0000 0x1000>;
 476                                 status = "disabled";
 477                         };
 478
 479                         frame@98b0000 {
 480                                 frame-number = <5>;
 481                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 482                                 reg = <0x098b0000 0x1000>;
 483                                 status = "disabled";
 484                         };
 485
 486                         frame@98c0000 {
 487                                 frame-number = <6>;
 488                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 489                                 reg = <0x098c0000 0x1000>;
 490                                 status = "disabled";
 491                         };
 492                 };
 493
 494                 spmi_bus: qcom,spmi@400f000 {
 495                         compatible = "qcom,spmi-pmic-arb";
 496                         reg = <0x400f000 0x1000>,
 497                               <0x4400000 0x800000>,
 498                               <0x4c00000 0x800000>,
 499                               <0x5800000 0x200000>,
 500                               <0x400a000 0x002100>;
 501                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 502                         interrupt-names = "periph_irq";
 503                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 504                         qcom,ee = <0>;
 505                         qcom,channel = <0>;
 506                         #address-cells = <2>;
 507                         #size-cells = <0>;
 508                         interrupt-controller;
 509                         #interrupt-cells = <4>;
 510                 };
 511
 512                 mmcc: clock-controller@8c0000 {
 513                         compatible = "qcom,mmcc-msm8996";
 514                         #clock-cells = <1>;
 515                         #reset-cells = <1>;
 516                         #power-domain-cells = <1>;
 517                         reg = <0x8c0000 0x40000>;
 518                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 519                                           <&mmcc MMPLL1_PLL>,
 520                                           <&mmcc MMPLL3_PLL>,
 521                                           <&mmcc MMPLL4_PLL>,
 522                                           <&mmcc MMPLL5_PLL>;
 523                         assigned-clock-rates = <624000000>,
 524                                                <810000000>,
 525                                                <980000000>,
 526                                                <960000000>,
 527                                                <825000000>;
 528                 };
 529         };
 530
 531         adsp-smp2p {
 532                 compatible = "qcom,smp2p";
 533                 qcom,smem = <443>, <429>;
 534
 535                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 536
 537                 qcom,ipc = <&apcs 16 10>;
 538
 539                 qcom,local-pid = <0>;
 540                 qcom,remote-pid = <2>;
 541
 542                 adsp_smp2p_out: master-kernel {
 543                         qcom,entry-name = "master-kernel";
 544                         #qcom,state-cells = <1>;
 545                 };
 546
 547                 adsp_smp2p_in: slave-kernel {
 548                         qcom,entry-name = "slave-kernel";
 549
 550                         interrupt-controller;
 551                         #interrupt-cells = <2>;
 552                 };
 553         };
 554 };
 555 #include "msm8996-pins.dtsi"