arch/arm64/boot/dts/renesas/r8a77995.dtsi

   1 /*
   2  * Device Tree Source for the r8a77995 SoC
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Glider bvba
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/r8a77995-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a77995";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         psci {
  22                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  23                 method = "smc";
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 a53_0: cpu@0 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         reg = <0x0>;
  33                         device_type = "cpu";
  34                         power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
  35                         next-level-cache = <&L2_CA53>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 L2_CA53: cache-controller-1 {
  40                         compatible = "cache";
  41                         power-domains = <&sysc R8A77995_PD_CA53_SCU>;
  42                         cache-unified;
  43                         cache-level = <2>;
  44                 };
  45         };
  46
  47         extal_clk: extal {
  48                 compatible = "fixed-clock";
  49                 #clock-cells = <0>;
  50                 /* This value must be overridden by the board */
  51                 clock-frequency = <0>;
  52         };
  53
  54         scif_clk: scif {
  55                 compatible = "fixed-clock";
  56                 #clock-cells = <0>;
  57                 clock-frequency = <0>;
  58         };
  59
  60         soc {
  61                 compatible = "simple-bus";
  62                 interrupt-parent = <&gic>;
  63                 #address-cells = <2>;
  64                 #size-cells = <2>;
  65                 ranges;
  66
  67                 gic: interrupt-controller@f1010000 {
  68                         compatible = "arm,gic-400";
  69                         #interrupt-cells = <3>;
  70                         #address-cells = <0>;
  71                         interrupt-controller;
  72                         reg = <0x0 0xf1010000 0 0x1000>,
  73                               <0x0 0xf1020000 0 0x20000>,
  74                               <0x0 0xf1040000 0 0x20000>,
  75                               <0x0 0xf1060000 0 0x20000>;
  76                         interrupts = <GIC_PPI 9
  77                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  78                         clocks = <&cpg CPG_MOD 408>;
  79                         clock-names = "clk";
  80                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
  81                         resets = <&cpg 408>;
  82                 };
  83
  84                 timer {
  85                         compatible = "arm,armv8-timer";
  86                         interrupts = <GIC_PPI 13
  87                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  88                                      <GIC_PPI 14
  89                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  90                                      <GIC_PPI 11
  91                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  92                                      <GIC_PPI 10
  93                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  94                 };
  95
  96                 rwdt: watchdog@e6020000 {
  97                         compatible = "renesas,r8a77995-wdt",
  98                                      "renesas,rcar-gen3-wdt";
  99                         reg = <0 0xe6020000 0 0x0c>;
 100                         clocks = <&cpg CPG_MOD 402>;
 101                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 102                         resets = <&cpg 402>;
 103                         status = "disabled";
 104                 };
 105
 106                 pmu_a53 {
 107                         compatible = "arm,cortex-a53-pmu";
 108                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 109                 };
 110
 111                 cpg: clock-controller@e6150000 {
 112                         compatible = "renesas,r8a77995-cpg-mssr";
 113                         reg = <0 0xe6150000 0 0x1000>;
 114                         clocks = <&extal_clk>;
 115                         clock-names = "extal";
 116                         #clock-cells = <2>;
 117                         #power-domain-cells = <0>;
 118                         #reset-cells = <1>;
 119                 };
 120
 121                 rst: reset-controller@e6160000 {
 122                         compatible = "renesas,r8a77995-rst";
 123                         reg = <0 0xe6160000 0 0x0200>;
 124                 };
 125
 126                 pfc: pin-controller@e6060000 {
 127                         compatible = "renesas,pfc-r8a77995";
 128                         reg = <0 0xe6060000 0 0x508>;
 129                 };
 130
 131                 prr: chipid@fff00044 {
 132                         compatible = "renesas,prr";
 133                         reg = <0 0xfff00044 0 4>;
 134                 };
 135
 136                 sysc: system-controller@e6180000 {
 137                         compatible = "renesas,r8a77995-sysc";
 138                         reg = <0 0xe6180000 0 0x0400>;
 139                         #power-domain-cells = <1>;
 140                 };
 141
 142                 gpio0: gpio@e6050000 {
 143                         compatible = "renesas,gpio-r8a77995",
 144                                      "renesas,rcar-gen3-gpio",
 145                                      "renesas,gpio-rcar";
 146                         reg = <0 0xe6050000 0 0x50>;
 147                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 148                         #gpio-cells = <2>;
 149                         gpio-controller;
 150                         gpio-ranges = <&pfc 0 0 9>;
 151                         #interrupt-cells = <2>;
 152                         interrupt-controller;
 153                         clocks = <&cpg CPG_MOD 912>;
 154                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 155                         resets = <&cpg 912>;
 156                 };
 157
 158                 gpio1: gpio@e6051000 {
 159                         compatible = "renesas,gpio-r8a77995",
 160                                      "renesas,rcar-gen3-gpio",
 161                                      "renesas,gpio-rcar";
 162                         reg = <0 0xe6051000 0 0x50>;
 163                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 164                         #gpio-cells = <2>;
 165                         gpio-controller;
 166                         gpio-ranges = <&pfc 0 32 32>;
 167                         #interrupt-cells = <2>;
 168                         interrupt-controller;
 169                         clocks = <&cpg CPG_MOD 911>;
 170                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 171                         resets = <&cpg 911>;
 172                 };
 173
 174                 gpio2: gpio@e6052000 {
 175                         compatible = "renesas,gpio-r8a77995",
 176                                      "renesas,rcar-gen3-gpio",
 177                                      "renesas,gpio-rcar";
 178                         reg = <0 0xe6052000 0 0x50>;
 179                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 180                         #gpio-cells = <2>;
 181                         gpio-controller;
 182                         gpio-ranges = <&pfc 0 64 32>;
 183                         #interrupt-cells = <2>;
 184                         interrupt-controller;
 185                         clocks = <&cpg CPG_MOD 910>;
 186                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 187                         resets = <&cpg 910>;
 188                 };
 189
 190                 gpio3: gpio@e6053000 {
 191                         compatible = "renesas,gpio-r8a77995",
 192                                      "renesas,rcar-gen3-gpio",
 193                                      "renesas,gpio-rcar";
 194                         reg = <0 0xe6053000 0 0x50>;
 195                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 196                         #gpio-cells = <2>;
 197                         gpio-controller;
 198                         gpio-ranges = <&pfc 0 96 10>;
 199                         #interrupt-cells = <2>;
 200                         interrupt-controller;
 201                         clocks = <&cpg CPG_MOD 909>;
 202                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 203                         resets = <&cpg 909>;
 204                 };
 205
 206                 gpio4: gpio@e6054000 {
 207                         compatible = "renesas,gpio-r8a77995",
 208                                      "renesas,rcar-gen3-gpio",
 209                                      "renesas,gpio-rcar";
 210                         reg = <0 0xe6054000 0 0x50>;
 211                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 212                         #gpio-cells = <2>;
 213                         gpio-controller;
 214                         gpio-ranges = <&pfc 0 128 32>;
 215                         #interrupt-cells = <2>;
 216                         interrupt-controller;
 217                         clocks = <&cpg CPG_MOD 908>;
 218                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 219                         resets = <&cpg 908>;
 220                 };
 221
 222                 gpio5: gpio@e6055000 {
 223                         compatible = "renesas,gpio-r8a77995",
 224                                      "renesas,rcar-gen3-gpio",
 225                                      "renesas,gpio-rcar";
 226                         reg = <0 0xe6055000 0 0x50>;
 227                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 228                         #gpio-cells = <2>;
 229                         gpio-controller;
 230                         gpio-ranges = <&pfc 0 160 21>;
 231                         #interrupt-cells = <2>;
 232                         interrupt-controller;
 233                         clocks = <&cpg CPG_MOD 907>;
 234                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 235                         resets = <&cpg 907>;
 236                 };
 237
 238                 gpio6: gpio@e6055400 {
 239                         compatible = "renesas,gpio-r8a77995",
 240                                      "renesas,rcar-gen3-gpio",
 241                                      "renesas,gpio-rcar";
 242                         reg = <0 0xe6055400 0 0x50>;
 243                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 244                         #gpio-cells = <2>;
 245                         gpio-controller;
 246                         gpio-ranges = <&pfc 0 192 14>;
 247                         #interrupt-cells = <2>;
 248                         interrupt-controller;
 249                         clocks = <&cpg CPG_MOD 906>;
 250                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 251                         resets = <&cpg 906>;
 252                 };
 253
 254                 avb: ethernet@e6800000 {
 255                         compatible = "renesas,etheravb-r8a77995",
 256                                      "renesas,etheravb-rcar-gen3";
 257                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 258                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 259                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 260                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 261                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 262                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 263                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 264                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 265                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 266                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 268                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 269                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 270                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 271                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 283                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 284                                           "ch4", "ch5", "ch6", "ch7",
 285                                           "ch8", "ch9", "ch10", "ch11",
 286                                           "ch12", "ch13", "ch14", "ch15",
 287                                           "ch16", "ch17", "ch18", "ch19",
 288                                           "ch20", "ch21", "ch22", "ch23",
 289                                           "ch24";
 290                         clocks = <&cpg CPG_MOD 812>;
 291                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 292                         resets = <&cpg 812>;
 293                         phy-mode = "rgmii-txid";
 294                         #address-cells = <1>;
 295                         #size-cells = <0>;
 296                         status = "disabled";
 297                 };
 298
 299                 scif2: serial@e6e88000 {
 300                         compatible = "renesas,scif-r8a77995",
 301                                      "renesas,rcar-gen3-scif", "renesas,scif";
 302                         reg = <0 0xe6e88000 0 64>;
 303                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&cpg CPG_MOD 310>,
 305                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 306                                  <&scif_clk>;
 307                         clock-names = "fck", "brg_int", "scif_clk";
 308                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 309                         resets = <&cpg 310>;
 310                         status = "disabled";
 311                 };
 312
 313                 ehci0: usb@ee080100 {
 314                         compatible = "generic-ehci";
 315                         reg = <0 0xee080100 0 0x100>;
 316                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&cpg CPG_MOD 703>;
 318                         phys = <&usb2_phy0>;
 319                         phy-names = "usb";
 320                         companion = <&ohci0>;
 321                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 322                         resets = <&cpg 703>;
 323                         status = "disabled";
 324                 };
 325
 326                 ohci0: usb@ee080000 {
 327                         compatible = "generic-ohci";
 328                         reg = <0 0xee080000 0 0x100>;
 329                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 330                         clocks = <&cpg CPG_MOD 703>;
 331                         phys = <&usb2_phy0>;
 332                         phy-names = "usb";
 333                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 334                         resets = <&cpg 703>;
 335                         status = "disabled";
 336                 };
 337
 338                 usb2_phy0: usb-phy@ee080200 {
 339                         compatible = "renesas,usb2-phy-r8a77995",
 340                                      "renesas,rcar-gen3-usb2-phy";
 341                         reg = <0 0xee080200 0 0x700>;
 342                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 343                         clocks = <&cpg CPG_MOD 703>;
 344                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 345                         resets = <&cpg 703>;
 346                         #phy-cells = <0>;
 347                         status = "disabled";
 348                 };
 349         };
 350 };