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arm64: dts: rockchip: rename nodename for phy-rockchip-inno-usb2
[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / boot / dts / rockchip / px30.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "rockchip,px30";
17
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 ethernet0 = &gmac;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &uart2;
31 serial3 = &uart3;
32 serial4 = &uart4;
33 serial5 = &uart5;
34 spi0 = &spi0;
35 spi1 = &spi1;
36 };
37
38 cpus {
39 #address-cells = <2>;
40 #size-cells = <0>;
41
42 cpu0: cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a35";
45 reg = <0x0 0x0>;
46 enable-method = "psci";
47 clocks = <&cru ARMCLK>;
48 #cooling-cells = <2>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
52 };
53
54 cpu1: cpu@1 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a35";
57 reg = <0x0 0x1>;
58 enable-method = "psci";
59 clocks = <&cru ARMCLK>;
60 #cooling-cells = <2>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
64 };
65
66 cpu2: cpu@2 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a35";
69 reg = <0x0 0x2>;
70 enable-method = "psci";
71 clocks = <&cru ARMCLK>;
72 #cooling-cells = <2>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
76 };
77
78 cpu3: cpu@3 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a35";
81 reg = <0x0 0x3>;
82 enable-method = "psci";
83 clocks = <&cru ARMCLK>;
84 #cooling-cells = <2>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
88 };
89
90 idle-states {
91 entry-method = "psci";
92
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
100 };
101
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
104 local-timer-stop;
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
109 };
110 };
111 };
112
113 cpu0_opp_table: cpu0-opp-table {
114 compatible = "operating-points-v2";
115 opp-shared;
116
117 opp-600000000 {
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
121 opp-suspend;
122 };
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
127 };
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
132 };
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
137 };
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
142 };
143 };
144
145 arm-pmu {
146 compatible = "arm,cortex-a35-pmu";
147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
152 };
153
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
156 ports = <&vopb_out>, <&vopl_out>;
157 status = "disabled";
158 };
159
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
164 #clock-cells = <0>;
165 };
166
167 psci {
168 compatible = "arm,psci-1.0";
169 method = "smc";
170 };
171
172 timer {
173 compatible = "arm,armv8-timer";
174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
178 };
179
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
186
187 trips {
188 threshold: trip-point-0 {
189 temperature = <70000>;
190 hysteresis = <2000>;
191 type = "passive";
192 };
193
194 target: trip-point-1 {
195 temperature = <85000>;
196 hysteresis = <2000>;
197 type = "passive";
198 };
199
200 soc_crit: soc-crit {
201 temperature = <115000>;
202 hysteresis = <2000>;
203 type = "critical";
204 };
205 };
206
207 cooling-maps {
208 map0 {
209 trip = <&target>;
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211 contribution = <4096>;
212 };
213
214 map1 {
215 trip = <&target>;
216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
217 contribution = <4096>;
218 };
219 };
220 };
221
222 gpu_thermal: gpu-thermal {
223 polling-delay-passive = <100>; /* milliseconds */
224 polling-delay = <1000>; /* milliseconds */
225 thermal-sensors = <&tsadc 1>;
226 };
227 };
228
229 xin24m: xin24m {
230 compatible = "fixed-clock";
231 #clock-cells = <0>;
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
234 };
235
236 pmu: power-management@ff000000 {
237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
238 reg = <0x0 0xff000000 0x0 0x1000>;
239
240 power: power-controller {
241 compatible = "rockchip,px30-power-controller";
242 #power-domain-cells = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245
246 /* These power domains are grouped by VD_LOGIC */
247 power-domain@PX30_PD_USB {
248 reg = <PX30_PD_USB>;
249 clocks = <&cru HCLK_HOST>,
250 <&cru HCLK_OTG>,
251 <&cru SCLK_OTG_ADP>;
252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
253 #power-domain-cells = <0>;
254 };
255 power-domain@PX30_PD_SDCARD {
256 reg = <PX30_PD_SDCARD>;
257 clocks = <&cru HCLK_SDMMC>,
258 <&cru SCLK_SDMMC>;
259 pm_qos = <&qos_sdmmc>;
260 #power-domain-cells = <0>;
261 };
262 power-domain@PX30_PD_GMAC {
263 reg = <PX30_PD_GMAC>;
264 clocks = <&cru ACLK_GMAC>,
265 <&cru PCLK_GMAC>,
266 <&cru SCLK_MAC_REF>,
267 <&cru SCLK_GMAC_RX_TX>;
268 pm_qos = <&qos_gmac>;
269 #power-domain-cells = <0>;
270 };
271 power-domain@PX30_PD_MMC_NAND {
272 reg = <PX30_PD_MMC_NAND>;
273 clocks = <&cru HCLK_NANDC>,
274 <&cru HCLK_EMMC>,
275 <&cru HCLK_SDIO>,
276 <&cru HCLK_SFC>,
277 <&cru SCLK_EMMC>,
278 <&cru SCLK_NANDC>,
279 <&cru SCLK_SDIO>,
280 <&cru SCLK_SFC>;
281 pm_qos = <&qos_emmc>, <&qos_nand>,
282 <&qos_sdio>, <&qos_sfc>;
283 #power-domain-cells = <0>;
284 };
285 power-domain@PX30_PD_VPU {
286 reg = <PX30_PD_VPU>;
287 clocks = <&cru ACLK_VPU>,
288 <&cru HCLK_VPU>,
289 <&cru SCLK_CORE_VPU>;
290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
291 #power-domain-cells = <0>;
292 };
293 power-domain@PX30_PD_VO {
294 reg = <PX30_PD_VO>;
295 clocks = <&cru ACLK_RGA>,
296 <&cru ACLK_VOPB>,
297 <&cru ACLK_VOPL>,
298 <&cru DCLK_VOPB>,
299 <&cru DCLK_VOPL>,
300 <&cru HCLK_RGA>,
301 <&cru HCLK_VOPB>,
302 <&cru HCLK_VOPL>,
303 <&cru PCLK_MIPI_DSI>,
304 <&cru SCLK_RGA_CORE>,
305 <&cru SCLK_VOPB_PWM>;
306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
307 <&qos_vop_m0>, <&qos_vop_m1>;
308 #power-domain-cells = <0>;
309 };
310 power-domain@PX30_PD_VI {
311 reg = <PX30_PD_VI>;
312 clocks = <&cru ACLK_CIF>,
313 <&cru ACLK_ISP>,
314 <&cru HCLK_CIF>,
315 <&cru HCLK_ISP>,
316 <&cru SCLK_ISP>;
317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
318 <&qos_isp_wr>, <&qos_isp_m1>,
319 <&qos_vip>;
320 #power-domain-cells = <0>;
321 };
322 power-domain@PX30_PD_GPU {
323 reg = <PX30_PD_GPU>;
324 clocks = <&cru SCLK_GPU>;
325 pm_qos = <&qos_gpu>;
326 #power-domain-cells = <0>;
327 };
328 };
329 };
330
331 pmugrf: syscon@ff010000 {
332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
333 reg = <0x0 0xff010000 0x0 0x1000>;
334 #address-cells = <1>;
335 #size-cells = <1>;
336
337 pmu_io_domains: io-domains {
338 compatible = "rockchip,px30-pmu-io-voltage-domain";
339 status = "disabled";
340 };
341
342 reboot-mode {
343 compatible = "syscon-reboot-mode";
344 offset = <0x200>;
345 mode-bootloader = <BOOT_BL_DOWNLOAD>;
346 mode-fastboot = <BOOT_FASTBOOT>;
347 mode-loader = <BOOT_BL_DOWNLOAD>;
348 mode-normal = <BOOT_NORMAL>;
349 mode-recovery = <BOOT_RECOVERY>;
350 };
351 };
352
353 uart0: serial@ff030000 {
354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
355 reg = <0x0 0xff030000 0x0 0x100>;
356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
358 clock-names = "baudclk", "apb_pclk";
359 dmas = <&dmac 0>, <&dmac 1>;
360 dma-names = "tx", "rx";
361 reg-shift = <2>;
362 reg-io-width = <4>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
365 status = "disabled";
366 };
367
368 i2s1_2ch: i2s@ff070000 {
369 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
370 reg = <0x0 0xff070000 0x0 0x1000>;
371 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
373 clock-names = "i2s_clk", "i2s_hclk";
374 dmas = <&dmac 18>, <&dmac 19>;
375 dma-names = "tx", "rx";
376 pinctrl-names = "default";
377 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
378 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
379 #sound-dai-cells = <0>;
380 status = "disabled";
381 };
382
383 i2s2_2ch: i2s@ff080000 {
384 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
385 reg = <0x0 0xff080000 0x0 0x1000>;
386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
388 clock-names = "i2s_clk", "i2s_hclk";
389 dmas = <&dmac 20>, <&dmac 21>;
390 dma-names = "tx", "rx";
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
393 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
394 #sound-dai-cells = <0>;
395 status = "disabled";
396 };
397
398 gic: interrupt-controller@ff131000 {
399 compatible = "arm,gic-400";
400 #interrupt-cells = <3>;
401 #address-cells = <0>;
402 interrupt-controller;
403 reg = <0x0 0xff131000 0 0x1000>,
404 <0x0 0xff132000 0 0x2000>,
405 <0x0 0xff134000 0 0x2000>,
406 <0x0 0xff136000 0 0x2000>;
407 interrupts = <GIC_PPI 9
408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
409 };
410
411 grf: syscon@ff140000 {
412 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
413 reg = <0x0 0xff140000 0x0 0x1000>;
414 #address-cells = <1>;
415 #size-cells = <1>;
416
417 io_domains: io-domains {
418 compatible = "rockchip,px30-io-voltage-domain";
419 status = "disabled";
420 };
421
422 lvds: lvds {
423 compatible = "rockchip,px30-lvds";
424 phys = <&dsi_dphy>;
425 phy-names = "dphy";
426 rockchip,grf = <&grf>;
427 rockchip,output = "lvds";
428 status = "disabled";
429
430 ports {
431 #address-cells = <1>;
432 #size-cells = <0>;
433
434 port@0 {
435 reg = <0>;
436 #address-cells = <1>;
437 #size-cells = <0>;
438
439 lvds_vopb_in: endpoint@0 {
440 reg = <0>;
441 remote-endpoint = <&vopb_out_lvds>;
442 };
443
444 lvds_vopl_in: endpoint@1 {
445 reg = <1>;
446 remote-endpoint = <&vopl_out_lvds>;
447 };
448 };
449 };
450 };
451 };
452
453 uart1: serial@ff158000 {
454 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
455 reg = <0x0 0xff158000 0x0 0x100>;
456 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
458 clock-names = "baudclk", "apb_pclk";
459 dmas = <&dmac 2>, <&dmac 3>;
460 dma-names = "tx", "rx";
461 reg-shift = <2>;
462 reg-io-width = <4>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
465 status = "disabled";
466 };
467
468 uart2: serial@ff160000 {
469 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
470 reg = <0x0 0xff160000 0x0 0x100>;
471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
473 clock-names = "baudclk", "apb_pclk";
474 dmas = <&dmac 4>, <&dmac 5>;
475 dma-names = "tx", "rx";
476 reg-shift = <2>;
477 reg-io-width = <4>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&uart2m0_xfer>;
480 status = "disabled";
481 };
482
483 uart3: serial@ff168000 {
484 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
485 reg = <0x0 0xff168000 0x0 0x100>;
486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
488 clock-names = "baudclk", "apb_pclk";
489 dmas = <&dmac 6>, <&dmac 7>;
490 dma-names = "tx", "rx";
491 reg-shift = <2>;
492 reg-io-width = <4>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
495 status = "disabled";
496 };
497
498 uart4: serial@ff170000 {
499 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
500 reg = <0x0 0xff170000 0x0 0x100>;
501 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
503 clock-names = "baudclk", "apb_pclk";
504 dmas = <&dmac 8>, <&dmac 9>;
505 dma-names = "tx", "rx";
506 reg-shift = <2>;
507 reg-io-width = <4>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
510 status = "disabled";
511 };
512
513 uart5: serial@ff178000 {
514 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
515 reg = <0x0 0xff178000 0x0 0x100>;
516 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
518 clock-names = "baudclk", "apb_pclk";
519 dmas = <&dmac 10>, <&dmac 11>;
520 dma-names = "tx", "rx";
521 reg-shift = <2>;
522 reg-io-width = <4>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
525 status = "disabled";
526 };
527
528 i2c0: i2c@ff180000 {
529 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
530 reg = <0x0 0xff180000 0x0 0x1000>;
531 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
532 clock-names = "i2c", "pclk";
533 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&i2c0_xfer>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 status = "disabled";
539 };
540
541 i2c1: i2c@ff190000 {
542 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
543 reg = <0x0 0xff190000 0x0 0x1000>;
544 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
545 clock-names = "i2c", "pclk";
546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c1_xfer>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551 status = "disabled";
552 };
553
554 i2c2: i2c@ff1a0000 {
555 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
556 reg = <0x0 0xff1a0000 0x0 0x1000>;
557 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
558 clock-names = "i2c", "pclk";
559 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c2_xfer>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564 status = "disabled";
565 };
566
567 i2c3: i2c@ff1b0000 {
568 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
569 reg = <0x0 0xff1b0000 0x0 0x1000>;
570 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
571 clock-names = "i2c", "pclk";
572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c3_xfer>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 status = "disabled";
578 };
579
580 spi0: spi@ff1d0000 {
581 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
582 reg = <0x0 0xff1d0000 0x0 0x1000>;
583 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
585 clock-names = "spiclk", "apb_pclk";
586 dmas = <&dmac 12>, <&dmac 13>;
587 dma-names = "tx", "rx";
588 pinctrl-names = "default";
589 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
590 #address-cells = <1>;
591 #size-cells = <0>;
592 status = "disabled";
593 };
594
595 spi1: spi@ff1d8000 {
596 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
597 reg = <0x0 0xff1d8000 0x0 0x1000>;
598 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
600 clock-names = "spiclk", "apb_pclk";
601 dmas = <&dmac 14>, <&dmac 15>;
602 dma-names = "tx", "rx";
603 pinctrl-names = "default";
604 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
605 #address-cells = <1>;
606 #size-cells = <0>;
607 status = "disabled";
608 };
609
610 wdt: watchdog@ff1e0000 {
611 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
612 reg = <0x0 0xff1e0000 0x0 0x100>;
613 clocks = <&cru PCLK_WDT_NS>;
614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
615 status = "disabled";
616 };
617
618 pwm0: pwm@ff200000 {
619 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
620 reg = <0x0 0xff200000 0x0 0x10>;
621 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
622 clock-names = "pwm", "pclk";
623 pinctrl-names = "default";
624 pinctrl-0 = <&pwm0_pin>;
625 #pwm-cells = <3>;
626 status = "disabled";
627 };
628
629 pwm1: pwm@ff200010 {
630 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
631 reg = <0x0 0xff200010 0x0 0x10>;
632 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
633 clock-names = "pwm", "pclk";
634 pinctrl-names = "default";
635 pinctrl-0 = <&pwm1_pin>;
636 #pwm-cells = <3>;
637 status = "disabled";
638 };
639
640 pwm2: pwm@ff200020 {
641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
642 reg = <0x0 0xff200020 0x0 0x10>;
643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
644 clock-names = "pwm", "pclk";
645 pinctrl-names = "default";
646 pinctrl-0 = <&pwm2_pin>;
647 #pwm-cells = <3>;
648 status = "disabled";
649 };
650
651 pwm3: pwm@ff200030 {
652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
653 reg = <0x0 0xff200030 0x0 0x10>;
654 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
655 clock-names = "pwm", "pclk";
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm3_pin>;
658 #pwm-cells = <3>;
659 status = "disabled";
660 };
661
662 pwm4: pwm@ff208000 {
663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
664 reg = <0x0 0xff208000 0x0 0x10>;
665 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
666 clock-names = "pwm", "pclk";
667 pinctrl-names = "default";
668 pinctrl-0 = <&pwm4_pin>;
669 #pwm-cells = <3>;
670 status = "disabled";
671 };
672
673 pwm5: pwm@ff208010 {
674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
675 reg = <0x0 0xff208010 0x0 0x10>;
676 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
677 clock-names = "pwm", "pclk";
678 pinctrl-names = "default";
679 pinctrl-0 = <&pwm5_pin>;
680 #pwm-cells = <3>;
681 status = "disabled";
682 };
683
684 pwm6: pwm@ff208020 {
685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
686 reg = <0x0 0xff208020 0x0 0x10>;
687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
688 clock-names = "pwm", "pclk";
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm6_pin>;
691 #pwm-cells = <3>;
692 status = "disabled";
693 };
694
695 pwm7: pwm@ff208030 {
696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
697 reg = <0x0 0xff208030 0x0 0x10>;
698 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
699 clock-names = "pwm", "pclk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&pwm7_pin>;
702 #pwm-cells = <3>;
703 status = "disabled";
704 };
705
706 rktimer: timer@ff210000 {
707 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
708 reg = <0x0 0xff210000 0x0 0x1000>;
709 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
711 clock-names = "pclk", "timer";
712 };
713
714 dmac: dmac@ff240000 {
715 compatible = "arm,pl330", "arm,primecell";
716 reg = <0x0 0xff240000 0x0 0x4000>;
717 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
719 arm,pl330-periph-burst;
720 clocks = <&cru ACLK_DMAC>;
721 clock-names = "apb_pclk";
722 #dma-cells = <1>;
723 };
724
725 tsadc: tsadc@ff280000 {
726 compatible = "rockchip,px30-tsadc";
727 reg = <0x0 0xff280000 0x0 0x100>;
728 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
729 assigned-clocks = <&cru SCLK_TSADC>;
730 assigned-clock-rates = <50000>;
731 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
732 clock-names = "tsadc", "apb_pclk";
733 resets = <&cru SRST_TSADC>;
734 reset-names = "tsadc-apb";
735 rockchip,grf = <&grf>;
736 rockchip,hw-tshut-temp = <120000>;
737 pinctrl-names = "init", "default", "sleep";
738 pinctrl-0 = <&tsadc_otp_pin>;
739 pinctrl-1 = <&tsadc_otp_out>;
740 pinctrl-2 = <&tsadc_otp_pin>;
741 #thermal-sensor-cells = <1>;
742 status = "disabled";
743 };
744
745 saradc: saradc@ff288000 {
746 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
747 reg = <0x0 0xff288000 0x0 0x100>;
748 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
749 #io-channel-cells = <1>;
750 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
751 clock-names = "saradc", "apb_pclk";
752 resets = <&cru SRST_SARADC_P>;
753 reset-names = "saradc-apb";
754 status = "disabled";
755 };
756
757 otp: nvmem@ff290000 {
758 compatible = "rockchip,px30-otp";
759 reg = <0x0 0xff290000 0x0 0x4000>;
760 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
761 <&cru PCLK_OTP_PHY>;
762 clock-names = "otp", "apb_pclk", "phy";
763 resets = <&cru SRST_OTP_PHY>;
764 reset-names = "phy";
765 #address-cells = <1>;
766 #size-cells = <1>;
767
768 /* Data cells */
769 cpu_id: id@7 {
770 reg = <0x07 0x10>;
771 };
772 cpu_leakage: cpu-leakage@17 {
773 reg = <0x17 0x1>;
774 };
775 performance: performance@1e {
776 reg = <0x1e 0x1>;
777 bits = <4 3>;
778 };
779 };
780
781 cru: clock-controller@ff2b0000 {
782 compatible = "rockchip,px30-cru";
783 reg = <0x0 0xff2b0000 0x0 0x1000>;
784 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
785 clock-names = "xin24m", "gpll";
786 rockchip,grf = <&grf>;
787 #clock-cells = <1>;
788 #reset-cells = <1>;
789
790 assigned-clocks = <&cru PLL_NPLL>,
791 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
792 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
793 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
794
795 assigned-clock-rates = <1188000000>,
796 <200000000>, <200000000>,
797 <150000000>, <150000000>,
798 <100000000>, <200000000>;
799 };
800
801 pmucru: clock-controller@ff2bc000 {
802 compatible = "rockchip,px30-pmucru";
803 reg = <0x0 0xff2bc000 0x0 0x1000>;
804 clocks = <&xin24m>;
805 clock-names = "xin24m";
806 rockchip,grf = <&grf>;
807 #clock-cells = <1>;
808 #reset-cells = <1>;
809
810 assigned-clocks =
811 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
812 <&pmucru SCLK_WIFI_PMU>;
813 assigned-clock-rates =
814 <1200000000>, <100000000>,
815 <26000000>;
816 };
817
818 usb2phy_grf: syscon@ff2c0000 {
819 compatible = "rockchip,px30-usb2phy-grf", "syscon",
820 "simple-mfd";
821 reg = <0x0 0xff2c0000 0x0 0x10000>;
822 #address-cells = <1>;
823 #size-cells = <1>;
824
825 u2phy: usb2phy@100 {
826 compatible = "rockchip,px30-usb2phy";
827 reg = <0x100 0x20>;
828 clocks = <&pmucru SCLK_USBPHY_REF>;
829 clock-names = "phyclk";
830 #clock-cells = <0>;
831 assigned-clocks = <&cru USB480M>;
832 assigned-clock-parents = <&u2phy>;
833 clock-output-names = "usb480m_phy";
834 status = "disabled";
835
836 u2phy_host: host-port {
837 #phy-cells = <0>;
838 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
839 interrupt-names = "linestate";
840 status = "disabled";
841 };
842
843 u2phy_otg: otg-port {
844 #phy-cells = <0>;
845 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
848 interrupt-names = "otg-bvalid", "otg-id",
849 "linestate";
850 status = "disabled";
851 };
852 };
853 };
854
855 dsi_dphy: phy@ff2e0000 {
856 compatible = "rockchip,px30-dsi-dphy";
857 reg = <0x0 0xff2e0000 0x0 0x10000>;
858 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
859 clock-names = "ref", "pclk";
860 resets = <&cru SRST_MIPIDSIPHY_P>;
861 reset-names = "apb";
862 #phy-cells = <0>;
863 power-domains = <&power PX30_PD_VO>;
864 status = "disabled";
865 };
866
867 usb20_otg: usb@ff300000 {
868 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
869 "snps,dwc2";
870 reg = <0x0 0xff300000 0x0 0x40000>;
871 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&cru HCLK_OTG>;
873 clock-names = "otg";
874 dr_mode = "otg";
875 g-np-tx-fifo-size = <16>;
876 g-rx-fifo-size = <280>;
877 g-tx-fifo-size = <256 128 128 64 32 16>;
878 phys = <&u2phy_otg>;
879 phy-names = "usb2-phy";
880 power-domains = <&power PX30_PD_USB>;
881 status = "disabled";
882 };
883
884 usb_host0_ehci: usb@ff340000 {
885 compatible = "generic-ehci";
886 reg = <0x0 0xff340000 0x0 0x10000>;
887 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&cru HCLK_HOST>;
889 phys = <&u2phy_host>;
890 phy-names = "usb";
891 power-domains = <&power PX30_PD_USB>;
892 status = "disabled";
893 };
894
895 usb_host0_ohci: usb@ff350000 {
896 compatible = "generic-ohci";
897 reg = <0x0 0xff350000 0x0 0x10000>;
898 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cru HCLK_HOST>;
900 phys = <&u2phy_host>;
901 phy-names = "usb";
902 power-domains = <&power PX30_PD_USB>;
903 status = "disabled";
904 };
905
906 gmac: ethernet@ff360000 {
907 compatible = "rockchip,px30-gmac";
908 reg = <0x0 0xff360000 0x0 0x10000>;
909 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
910 interrupt-names = "macirq";
911 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
912 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
913 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
914 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
915 clock-names = "stmmaceth", "mac_clk_rx",
916 "mac_clk_tx", "clk_mac_ref",
917 "clk_mac_refout", "aclk_mac",
918 "pclk_mac", "clk_mac_speed";
919 rockchip,grf = <&grf>;
920 phy-mode = "rmii";
921 pinctrl-names = "default";
922 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
923 power-domains = <&power PX30_PD_GMAC>;
924 resets = <&cru SRST_GMAC_A>;
925 reset-names = "stmmaceth";
926 status = "disabled";
927 };
928
929 sdmmc: mmc@ff370000 {
930 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
931 reg = <0x0 0xff370000 0x0 0x4000>;
932 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
934 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
935 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
936 bus-width = <4>;
937 fifo-depth = <0x100>;
938 max-frequency = <150000000>;
939 pinctrl-names = "default";
940 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
941 power-domains = <&power PX30_PD_SDCARD>;
942 status = "disabled";
943 };
944
945 sdio: mmc@ff380000 {
946 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
947 reg = <0x0 0xff380000 0x0 0x4000>;
948 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
950 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
951 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
952 bus-width = <4>;
953 fifo-depth = <0x100>;
954 max-frequency = <150000000>;
955 pinctrl-names = "default";
956 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
957 power-domains = <&power PX30_PD_MMC_NAND>;
958 status = "disabled";
959 };
960
961 emmc: mmc@ff390000 {
962 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
963 reg = <0x0 0xff390000 0x0 0x4000>;
964 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
966 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
967 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
968 bus-width = <8>;
969 fifo-depth = <0x100>;
970 max-frequency = <150000000>;
971 pinctrl-names = "default";
972 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
973 power-domains = <&power PX30_PD_MMC_NAND>;
974 status = "disabled";
975 };
976
977 nfc: nand-controller@ff3b0000 {
978 compatible = "rockchip,px30-nfc";
979 reg = <0x0 0xff3b0000 0x0 0x4000>;
980 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
982 clock-names = "ahb", "nfc";
983 assigned-clocks = <&cru SCLK_NANDC>;
984 assigned-clock-rates = <150000000>;
985 pinctrl-names = "default";
986 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
987 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
988 power-domains = <&power PX30_PD_MMC_NAND>;
989 status = "disabled";
990 };
991
992 gpu_opp_table: opp-table2 {
993 compatible = "operating-points-v2";
994
995 opp-200000000 {
996 opp-hz = /bits/ 64 <200000000>;
997 opp-microvolt = <950000>;
998 };
999 opp-300000000 {
1000 opp-hz = /bits/ 64 <300000000>;
1001 opp-microvolt = <975000>;
1002 };
1003 opp-400000000 {
1004 opp-hz = /bits/ 64 <400000000>;
1005 opp-microvolt = <1050000>;
1006 };
1007 opp-480000000 {
1008 opp-hz = /bits/ 64 <480000000>;
1009 opp-microvolt = <1125000>;
1010 };
1011 };
1012
1013 gpu: gpu@ff400000 {
1014 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1015 reg = <0x0 0xff400000 0x0 0x4000>;
1016 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1019 interrupt-names = "job", "mmu", "gpu";
1020 clocks = <&cru SCLK_GPU>;
1021 #cooling-cells = <2>;
1022 power-domains = <&power PX30_PD_GPU>;
1023 operating-points-v2 = <&gpu_opp_table>;
1024 status = "disabled";
1025 };
1026
1027 dsi: dsi@ff450000 {
1028 compatible = "rockchip,px30-mipi-dsi";
1029 reg = <0x0 0xff450000 0x0 0x10000>;
1030 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cru PCLK_MIPI_DSI>;
1032 clock-names = "pclk";
1033 phys = <&dsi_dphy>;
1034 phy-names = "dphy";
1035 power-domains = <&power PX30_PD_VO>;
1036 resets = <&cru SRST_MIPIDSI_HOST_P>;
1037 reset-names = "apb";
1038 rockchip,grf = <&grf>;
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1041 status = "disabled";
1042
1043 ports {
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046
1047 port@0 {
1048 reg = <0>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051
1052 dsi_in_vopb: endpoint@0 {
1053 reg = <0>;
1054 remote-endpoint = <&vopb_out_dsi>;
1055 };
1056
1057 dsi_in_vopl: endpoint@1 {
1058 reg = <1>;
1059 remote-endpoint = <&vopl_out_dsi>;
1060 };
1061 };
1062 };
1063 };
1064
1065 vopb: vop@ff460000 {
1066 compatible = "rockchip,px30-vop-big";
1067 reg = <0x0 0xff460000 0x0 0xefc>;
1068 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1070 <&cru HCLK_VOPB>;
1071 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1072 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1073 reset-names = "axi", "ahb", "dclk";
1074 iommus = <&vopb_mmu>;
1075 power-domains = <&power PX30_PD_VO>;
1076 status = "disabled";
1077
1078 vopb_out: port {
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081
1082 vopb_out_dsi: endpoint@0 {
1083 reg = <0>;
1084 remote-endpoint = <&dsi_in_vopb>;
1085 };
1086
1087 vopb_out_lvds: endpoint@1 {
1088 reg = <1>;
1089 remote-endpoint = <&lvds_vopb_in>;
1090 };
1091 };
1092 };
1093
1094 vopb_mmu: iommu@ff460f00 {
1095 compatible = "rockchip,iommu";
1096 reg = <0x0 0xff460f00 0x0 0x100>;
1097 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1099 clock-names = "aclk", "iface";
1100 power-domains = <&power PX30_PD_VO>;
1101 #iommu-cells = <0>;
1102 status = "disabled";
1103 };
1104
1105 vopl: vop@ff470000 {
1106 compatible = "rockchip,px30-vop-lit";
1107 reg = <0x0 0xff470000 0x0 0xefc>;
1108 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1110 <&cru HCLK_VOPL>;
1111 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1112 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1113 reset-names = "axi", "ahb", "dclk";
1114 iommus = <&vopl_mmu>;
1115 power-domains = <&power PX30_PD_VO>;
1116 status = "disabled";
1117
1118 vopl_out: port {
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121
1122 vopl_out_dsi: endpoint@0 {
1123 reg = <0>;
1124 remote-endpoint = <&dsi_in_vopl>;
1125 };
1126
1127 vopl_out_lvds: endpoint@1 {
1128 reg = <1>;
1129 remote-endpoint = <&lvds_vopl_in>;
1130 };
1131 };
1132 };
1133
1134 vopl_mmu: iommu@ff470f00 {
1135 compatible = "rockchip,iommu";
1136 reg = <0x0 0xff470f00 0x0 0x100>;
1137 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1138 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1139 clock-names = "aclk", "iface";
1140 power-domains = <&power PX30_PD_VO>;
1141 #iommu-cells = <0>;
1142 status = "disabled";
1143 };
1144
1145 qos_gmac: qos@ff518000 {
1146 compatible = "rockchip,px30-qos", "syscon";
1147 reg = <0x0 0xff518000 0x0 0x20>;
1148 };
1149
1150 qos_gpu: qos@ff520000 {
1151 compatible = "rockchip,px30-qos", "syscon";
1152 reg = <0x0 0xff520000 0x0 0x20>;
1153 };
1154
1155 qos_sdmmc: qos@ff52c000 {
1156 compatible = "rockchip,px30-qos", "syscon";
1157 reg = <0x0 0xff52c000 0x0 0x20>;
1158 };
1159
1160 qos_emmc: qos@ff538000 {
1161 compatible = "rockchip,px30-qos", "syscon";
1162 reg = <0x0 0xff538000 0x0 0x20>;
1163 };
1164
1165 qos_nand: qos@ff538080 {
1166 compatible = "rockchip,px30-qos", "syscon";
1167 reg = <0x0 0xff538080 0x0 0x20>;
1168 };
1169
1170 qos_sdio: qos@ff538100 {
1171 compatible = "rockchip,px30-qos", "syscon";
1172 reg = <0x0 0xff538100 0x0 0x20>;
1173 };
1174
1175 qos_sfc: qos@ff538180 {
1176 compatible = "rockchip,px30-qos", "syscon";
1177 reg = <0x0 0xff538180 0x0 0x20>;
1178 };
1179
1180 qos_usb_host: qos@ff540000 {
1181 compatible = "rockchip,px30-qos", "syscon";
1182 reg = <0x0 0xff540000 0x0 0x20>;
1183 };
1184
1185 qos_usb_otg: qos@ff540080 {
1186 compatible = "rockchip,px30-qos", "syscon";
1187 reg = <0x0 0xff540080 0x0 0x20>;
1188 };
1189
1190 qos_isp_128: qos@ff548000 {
1191 compatible = "rockchip,px30-qos", "syscon";
1192 reg = <0x0 0xff548000 0x0 0x20>;
1193 };
1194
1195 qos_isp_rd: qos@ff548080 {
1196 compatible = "rockchip,px30-qos", "syscon";
1197 reg = <0x0 0xff548080 0x0 0x20>;
1198 };
1199
1200 qos_isp_wr: qos@ff548100 {
1201 compatible = "rockchip,px30-qos", "syscon";
1202 reg = <0x0 0xff548100 0x0 0x20>;
1203 };
1204
1205 qos_isp_m1: qos@ff548180 {
1206 compatible = "rockchip,px30-qos", "syscon";
1207 reg = <0x0 0xff548180 0x0 0x20>;
1208 };
1209
1210 qos_vip: qos@ff548200 {
1211 compatible = "rockchip,px30-qos", "syscon";
1212 reg = <0x0 0xff548200 0x0 0x20>;
1213 };
1214
1215 qos_rga_rd: qos@ff550000 {
1216 compatible = "rockchip,px30-qos", "syscon";
1217 reg = <0x0 0xff550000 0x0 0x20>;
1218 };
1219
1220 qos_rga_wr: qos@ff550080 {
1221 compatible = "rockchip,px30-qos", "syscon";
1222 reg = <0x0 0xff550080 0x0 0x20>;
1223 };
1224
1225 qos_vop_m0: qos@ff550100 {
1226 compatible = "rockchip,px30-qos", "syscon";
1227 reg = <0x0 0xff550100 0x0 0x20>;
1228 };
1229
1230 qos_vop_m1: qos@ff550180 {
1231 compatible = "rockchip,px30-qos", "syscon";
1232 reg = <0x0 0xff550180 0x0 0x20>;
1233 };
1234
1235 qos_vpu: qos@ff558000 {
1236 compatible = "rockchip,px30-qos", "syscon";
1237 reg = <0x0 0xff558000 0x0 0x20>;
1238 };
1239
1240 qos_vpu_r128: qos@ff558080 {
1241 compatible = "rockchip,px30-qos", "syscon";
1242 reg = <0x0 0xff558080 0x0 0x20>;
1243 };
1244
1245 pinctrl: pinctrl {
1246 compatible = "rockchip,px30-pinctrl";
1247 rockchip,grf = <&grf>;
1248 rockchip,pmu = <&pmugrf>;
1249 #address-cells = <2>;
1250 #size-cells = <2>;
1251 ranges;
1252
1253 gpio0: gpio0@ff040000 {
1254 compatible = "rockchip,gpio-bank";
1255 reg = <0x0 0xff040000 0x0 0x100>;
1256 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&pmucru PCLK_GPIO0_PMU>;
1258 gpio-controller;
1259 #gpio-cells = <2>;
1260
1261 interrupt-controller;
1262 #interrupt-cells = <2>;
1263 };
1264
1265 gpio1: gpio1@ff250000 {
1266 compatible = "rockchip,gpio-bank";
1267 reg = <0x0 0xff250000 0x0 0x100>;
1268 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&cru PCLK_GPIO1>;
1270 gpio-controller;
1271 #gpio-cells = <2>;
1272
1273 interrupt-controller;
1274 #interrupt-cells = <2>;
1275 };
1276
1277 gpio2: gpio2@ff260000 {
1278 compatible = "rockchip,gpio-bank";
1279 reg = <0x0 0xff260000 0x0 0x100>;
1280 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&cru PCLK_GPIO2>;
1282 gpio-controller;
1283 #gpio-cells = <2>;
1284
1285 interrupt-controller;
1286 #interrupt-cells = <2>;
1287 };
1288
1289 gpio3: gpio3@ff270000 {
1290 compatible = "rockchip,gpio-bank";
1291 reg = <0x0 0xff270000 0x0 0x100>;
1292 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&cru PCLK_GPIO3>;
1294 gpio-controller;
1295 #gpio-cells = <2>;
1296
1297 interrupt-controller;
1298 #interrupt-cells = <2>;
1299 };
1300
1301 pcfg_pull_up: pcfg-pull-up {
1302 bias-pull-up;
1303 };
1304
1305 pcfg_pull_down: pcfg-pull-down {
1306 bias-pull-down;
1307 };
1308
1309 pcfg_pull_none: pcfg-pull-none {
1310 bias-disable;
1311 };
1312
1313 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1314 bias-disable;
1315 drive-strength = <2>;
1316 };
1317
1318 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1319 bias-pull-up;
1320 drive-strength = <2>;
1321 };
1322
1323 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1324 bias-pull-up;
1325 drive-strength = <4>;
1326 };
1327
1328 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1329 bias-disable;
1330 drive-strength = <4>;
1331 };
1332
1333 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1334 bias-pull-down;
1335 drive-strength = <4>;
1336 };
1337
1338 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1339 bias-disable;
1340 drive-strength = <8>;
1341 };
1342
1343 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1344 bias-pull-up;
1345 drive-strength = <8>;
1346 };
1347
1348 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1349 bias-disable;
1350 drive-strength = <12>;
1351 };
1352
1353 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1354 bias-pull-up;
1355 drive-strength = <12>;
1356 };
1357
1358 pcfg_pull_none_smt: pcfg-pull-none-smt {
1359 bias-disable;
1360 input-schmitt-enable;
1361 };
1362
1363 pcfg_output_high: pcfg-output-high {
1364 output-high;
1365 };
1366
1367 pcfg_output_low: pcfg-output-low {
1368 output-low;
1369 };
1370
1371 pcfg_input_high: pcfg-input-high {
1372 bias-pull-up;
1373 input-enable;
1374 };
1375
1376 pcfg_input: pcfg-input {
1377 input-enable;
1378 };
1379
1380 i2c0 {
1381 i2c0_xfer: i2c0-xfer {
1382 rockchip,pins =
1383 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1384 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1385 };
1386 };
1387
1388 i2c1 {
1389 i2c1_xfer: i2c1-xfer {
1390 rockchip,pins =
1391 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1392 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1393 };
1394 };
1395
1396 i2c2 {
1397 i2c2_xfer: i2c2-xfer {
1398 rockchip,pins =
1399 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1400 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1401 };
1402 };
1403
1404 i2c3 {
1405 i2c3_xfer: i2c3-xfer {
1406 rockchip,pins =
1407 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1408 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1409 };
1410 };
1411
1412 tsadc {
1413 tsadc_otp_pin: tsadc-otp-pin {
1414 rockchip,pins =
1415 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1416 };
1417
1418 tsadc_otp_out: tsadc-otp-out {
1419 rockchip,pins =
1420 <0 RK_PA6 1 &pcfg_pull_none>;
1421 };
1422 };
1423
1424 uart0 {
1425 uart0_xfer: uart0-xfer {
1426 rockchip,pins =
1427 <0 RK_PB2 1 &pcfg_pull_up>,
1428 <0 RK_PB3 1 &pcfg_pull_up>;
1429 };
1430
1431 uart0_cts: uart0-cts {
1432 rockchip,pins =
1433 <0 RK_PB4 1 &pcfg_pull_none>;
1434 };
1435
1436 uart0_rts: uart0-rts {
1437 rockchip,pins =
1438 <0 RK_PB5 1 &pcfg_pull_none>;
1439 };
1440 };
1441
1442 uart1 {
1443 uart1_xfer: uart1-xfer {
1444 rockchip,pins =
1445 <1 RK_PC1 1 &pcfg_pull_up>,
1446 <1 RK_PC0 1 &pcfg_pull_up>;
1447 };
1448
1449 uart1_cts: uart1-cts {
1450 rockchip,pins =
1451 <1 RK_PC2 1 &pcfg_pull_none>;
1452 };
1453
1454 uart1_rts: uart1-rts {
1455 rockchip,pins =
1456 <1 RK_PC3 1 &pcfg_pull_none>;
1457 };
1458 };
1459
1460 uart2-m0 {
1461 uart2m0_xfer: uart2m0-xfer {
1462 rockchip,pins =
1463 <1 RK_PD2 2 &pcfg_pull_up>,
1464 <1 RK_PD3 2 &pcfg_pull_up>;
1465 };
1466 };
1467
1468 uart2-m1 {
1469 uart2m1_xfer: uart2m1-xfer {
1470 rockchip,pins =
1471 <2 RK_PB4 2 &pcfg_pull_up>,
1472 <2 RK_PB6 2 &pcfg_pull_up>;
1473 };
1474 };
1475
1476 uart3-m0 {
1477 uart3m0_xfer: uart3m0-xfer {
1478 rockchip,pins =
1479 <0 RK_PC0 2 &pcfg_pull_up>,
1480 <0 RK_PC1 2 &pcfg_pull_up>;
1481 };
1482
1483 uart3m0_cts: uart3m0-cts {
1484 rockchip,pins =
1485 <0 RK_PC2 2 &pcfg_pull_none>;
1486 };
1487
1488 uart3m0_rts: uart3m0-rts {
1489 rockchip,pins =
1490 <0 RK_PC3 2 &pcfg_pull_none>;
1491 };
1492 };
1493
1494 uart3-m1 {
1495 uart3m1_xfer: uart3m1-xfer {
1496 rockchip,pins =
1497 <1 RK_PB6 2 &pcfg_pull_up>,
1498 <1 RK_PB7 2 &pcfg_pull_up>;
1499 };
1500
1501 uart3m1_cts: uart3m1-cts {
1502 rockchip,pins =
1503 <1 RK_PB4 2 &pcfg_pull_none>;
1504 };
1505
1506 uart3m1_rts: uart3m1-rts {
1507 rockchip,pins =
1508 <1 RK_PB5 2 &pcfg_pull_none>;
1509 };
1510 };
1511
1512 uart4 {
1513 uart4_xfer: uart4-xfer {
1514 rockchip,pins =
1515 <1 RK_PD4 2 &pcfg_pull_up>,
1516 <1 RK_PD5 2 &pcfg_pull_up>;
1517 };
1518
1519 uart4_cts: uart4-cts {
1520 rockchip,pins =
1521 <1 RK_PD6 2 &pcfg_pull_none>;
1522 };
1523
1524 uart4_rts: uart4-rts {
1525 rockchip,pins =
1526 <1 RK_PD7 2 &pcfg_pull_none>;
1527 };
1528 };
1529
1530 uart5 {
1531 uart5_xfer: uart5-xfer {
1532 rockchip,pins =
1533 <3 RK_PA2 4 &pcfg_pull_up>,
1534 <3 RK_PA1 4 &pcfg_pull_up>;
1535 };
1536
1537 uart5_cts: uart5-cts {
1538 rockchip,pins =
1539 <3 RK_PA3 4 &pcfg_pull_none>;
1540 };
1541
1542 uart5_rts: uart5-rts {
1543 rockchip,pins =
1544 <3 RK_PA5 4 &pcfg_pull_none>;
1545 };
1546 };
1547
1548 spi0 {
1549 spi0_clk: spi0-clk {
1550 rockchip,pins =
1551 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1552 };
1553
1554 spi0_csn: spi0-csn {
1555 rockchip,pins =
1556 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1557 };
1558
1559 spi0_miso: spi0-miso {
1560 rockchip,pins =
1561 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1562 };
1563
1564 spi0_mosi: spi0-mosi {
1565 rockchip,pins =
1566 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1567 };
1568
1569 spi0_clk_hs: spi0-clk-hs {
1570 rockchip,pins =
1571 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1572 };
1573
1574 spi0_miso_hs: spi0-miso-hs {
1575 rockchip,pins =
1576 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1577 };
1578
1579 spi0_mosi_hs: spi0-mosi-hs {
1580 rockchip,pins =
1581 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1582 };
1583 };
1584
1585 spi1 {
1586 spi1_clk: spi1-clk {
1587 rockchip,pins =
1588 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1589 };
1590
1591 spi1_csn0: spi1-csn0 {
1592 rockchip,pins =
1593 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1594 };
1595
1596 spi1_csn1: spi1-csn1 {
1597 rockchip,pins =
1598 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1599 };
1600
1601 spi1_miso: spi1-miso {
1602 rockchip,pins =
1603 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1604 };
1605
1606 spi1_mosi: spi1-mosi {
1607 rockchip,pins =
1608 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1609 };
1610
1611 spi1_clk_hs: spi1-clk-hs {
1612 rockchip,pins =
1613 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1614 };
1615
1616 spi1_miso_hs: spi1-miso-hs {
1617 rockchip,pins =
1618 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1619 };
1620
1621 spi1_mosi_hs: spi1-mosi-hs {
1622 rockchip,pins =
1623 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1624 };
1625 };
1626
1627 pdm {
1628 pdm_clk0m0: pdm-clk0m0 {
1629 rockchip,pins =
1630 <3 RK_PC6 2 &pcfg_pull_none>;
1631 };
1632
1633 pdm_clk0m1: pdm-clk0m1 {
1634 rockchip,pins =
1635 <2 RK_PC6 1 &pcfg_pull_none>;
1636 };
1637
1638 pdm_clk1: pdm-clk1 {
1639 rockchip,pins =
1640 <3 RK_PC7 2 &pcfg_pull_none>;
1641 };
1642
1643 pdm_sdi0m0: pdm-sdi0m0 {
1644 rockchip,pins =
1645 <3 RK_PD3 2 &pcfg_pull_none>;
1646 };
1647
1648 pdm_sdi0m1: pdm-sdi0m1 {
1649 rockchip,pins =
1650 <2 RK_PC5 2 &pcfg_pull_none>;
1651 };
1652
1653 pdm_sdi1: pdm-sdi1 {
1654 rockchip,pins =
1655 <3 RK_PD0 2 &pcfg_pull_none>;
1656 };
1657
1658 pdm_sdi2: pdm-sdi2 {
1659 rockchip,pins =
1660 <3 RK_PD1 2 &pcfg_pull_none>;
1661 };
1662
1663 pdm_sdi3: pdm-sdi3 {
1664 rockchip,pins =
1665 <3 RK_PD2 2 &pcfg_pull_none>;
1666 };
1667
1668 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1669 rockchip,pins =
1670 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1671 };
1672
1673 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1674 rockchip,pins =
1675 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1676 };
1677
1678 pdm_clk1_sleep: pdm-clk1-sleep {
1679 rockchip,pins =
1680 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1681 };
1682
1683 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1684 rockchip,pins =
1685 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1686 };
1687
1688 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1689 rockchip,pins =
1690 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1691 };
1692
1693 pdm_sdi1_sleep: pdm-sdi1-sleep {
1694 rockchip,pins =
1695 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1696 };
1697
1698 pdm_sdi2_sleep: pdm-sdi2-sleep {
1699 rockchip,pins =
1700 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1701 };
1702
1703 pdm_sdi3_sleep: pdm-sdi3-sleep {
1704 rockchip,pins =
1705 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1706 };
1707 };
1708
1709 i2s0 {
1710 i2s0_8ch_mclk: i2s0-8ch-mclk {
1711 rockchip,pins =
1712 <3 RK_PC1 2 &pcfg_pull_none>;
1713 };
1714
1715 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1716 rockchip,pins =
1717 <3 RK_PC3 2 &pcfg_pull_none>;
1718 };
1719
1720 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1721 rockchip,pins =
1722 <3 RK_PB4 2 &pcfg_pull_none>;
1723 };
1724
1725 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1726 rockchip,pins =
1727 <3 RK_PC2 2 &pcfg_pull_none>;
1728 };
1729
1730 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1731 rockchip,pins =
1732 <3 RK_PB5 2 &pcfg_pull_none>;
1733 };
1734
1735 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1736 rockchip,pins =
1737 <3 RK_PC4 2 &pcfg_pull_none>;
1738 };
1739
1740 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1741 rockchip,pins =
1742 <3 RK_PC0 2 &pcfg_pull_none>;
1743 };
1744
1745 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1746 rockchip,pins =
1747 <3 RK_PB7 2 &pcfg_pull_none>;
1748 };
1749
1750 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1751 rockchip,pins =
1752 <3 RK_PB6 2 &pcfg_pull_none>;
1753 };
1754
1755 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1756 rockchip,pins =
1757 <3 RK_PC5 2 &pcfg_pull_none>;
1758 };
1759
1760 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1761 rockchip,pins =
1762 <3 RK_PB3 2 &pcfg_pull_none>;
1763 };
1764
1765 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1766 rockchip,pins =
1767 <3 RK_PB1 2 &pcfg_pull_none>;
1768 };
1769
1770 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1771 rockchip,pins =
1772 <3 RK_PB0 2 &pcfg_pull_none>;
1773 };
1774 };
1775
1776 i2s1 {
1777 i2s1_2ch_mclk: i2s1-2ch-mclk {
1778 rockchip,pins =
1779 <2 RK_PC3 1 &pcfg_pull_none>;
1780 };
1781
1782 i2s1_2ch_sclk: i2s1-2ch-sclk {
1783 rockchip,pins =
1784 <2 RK_PC2 1 &pcfg_pull_none>;
1785 };
1786
1787 i2s1_2ch_lrck: i2s1-2ch-lrck {
1788 rockchip,pins =
1789 <2 RK_PC1 1 &pcfg_pull_none>;
1790 };
1791
1792 i2s1_2ch_sdi: i2s1-2ch-sdi {
1793 rockchip,pins =
1794 <2 RK_PC5 1 &pcfg_pull_none>;
1795 };
1796
1797 i2s1_2ch_sdo: i2s1-2ch-sdo {
1798 rockchip,pins =
1799 <2 RK_PC4 1 &pcfg_pull_none>;
1800 };
1801 };
1802
1803 i2s2 {
1804 i2s2_2ch_mclk: i2s2-2ch-mclk {
1805 rockchip,pins =
1806 <3 RK_PA1 2 &pcfg_pull_none>;
1807 };
1808
1809 i2s2_2ch_sclk: i2s2-2ch-sclk {
1810 rockchip,pins =
1811 <3 RK_PA2 2 &pcfg_pull_none>;
1812 };
1813
1814 i2s2_2ch_lrck: i2s2-2ch-lrck {
1815 rockchip,pins =
1816 <3 RK_PA3 2 &pcfg_pull_none>;
1817 };
1818
1819 i2s2_2ch_sdi: i2s2-2ch-sdi {
1820 rockchip,pins =
1821 <3 RK_PA5 2 &pcfg_pull_none>;
1822 };
1823
1824 i2s2_2ch_sdo: i2s2-2ch-sdo {
1825 rockchip,pins =
1826 <3 RK_PA7 2 &pcfg_pull_none>;
1827 };
1828 };
1829
1830 sdmmc {
1831 sdmmc_clk: sdmmc-clk {
1832 rockchip,pins =
1833 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1834 };
1835
1836 sdmmc_cmd: sdmmc-cmd {
1837 rockchip,pins =
1838 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1839 };
1840
1841 sdmmc_det: sdmmc-det {
1842 rockchip,pins =
1843 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1844 };
1845
1846 sdmmc_bus1: sdmmc-bus1 {
1847 rockchip,pins =
1848 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1849 };
1850
1851 sdmmc_bus4: sdmmc-bus4 {
1852 rockchip,pins =
1853 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1854 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1855 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1856 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1857 };
1858 };
1859
1860 sdio {
1861 sdio_clk: sdio-clk {
1862 rockchip,pins =
1863 <1 RK_PC5 1 &pcfg_pull_none>;
1864 };
1865
1866 sdio_cmd: sdio-cmd {
1867 rockchip,pins =
1868 <1 RK_PC4 1 &pcfg_pull_up>;
1869 };
1870
1871 sdio_bus4: sdio-bus4 {
1872 rockchip,pins =
1873 <1 RK_PC6 1 &pcfg_pull_up>,
1874 <1 RK_PC7 1 &pcfg_pull_up>,
1875 <1 RK_PD0 1 &pcfg_pull_up>,
1876 <1 RK_PD1 1 &pcfg_pull_up>;
1877 };
1878 };
1879
1880 emmc {
1881 emmc_clk: emmc-clk {
1882 rockchip,pins =
1883 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1884 };
1885
1886 emmc_cmd: emmc-cmd {
1887 rockchip,pins =
1888 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1889 };
1890
1891 emmc_rstnout: emmc-rstnout {
1892 rockchip,pins =
1893 <1 RK_PB3 2 &pcfg_pull_none>;
1894 };
1895
1896 emmc_bus1: emmc-bus1 {
1897 rockchip,pins =
1898 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1899 };
1900
1901 emmc_bus4: emmc-bus4 {
1902 rockchip,pins =
1903 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1904 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1905 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1906 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1907 };
1908
1909 emmc_bus8: emmc-bus8 {
1910 rockchip,pins =
1911 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1912 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1913 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1914 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1915 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1916 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1917 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1918 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1919 };
1920 };
1921
1922 flash {
1923 flash_cs0: flash-cs0 {
1924 rockchip,pins =
1925 <1 RK_PB0 1 &pcfg_pull_none>;
1926 };
1927
1928 flash_rdy: flash-rdy {
1929 rockchip,pins =
1930 <1 RK_PB1 1 &pcfg_pull_none>;
1931 };
1932
1933 flash_dqs: flash-dqs {
1934 rockchip,pins =
1935 <1 RK_PB2 1 &pcfg_pull_none>;
1936 };
1937
1938 flash_ale: flash-ale {
1939 rockchip,pins =
1940 <1 RK_PB3 1 &pcfg_pull_none>;
1941 };
1942
1943 flash_cle: flash-cle {
1944 rockchip,pins =
1945 <1 RK_PB4 1 &pcfg_pull_none>;
1946 };
1947
1948 flash_wrn: flash-wrn {
1949 rockchip,pins =
1950 <1 RK_PB5 1 &pcfg_pull_none>;
1951 };
1952
1953 flash_csl: flash-csl {
1954 rockchip,pins =
1955 <1 RK_PB6 1 &pcfg_pull_none>;
1956 };
1957
1958 flash_rdn: flash-rdn {
1959 rockchip,pins =
1960 <1 RK_PB7 1 &pcfg_pull_none>;
1961 };
1962
1963 flash_bus8: flash-bus8 {
1964 rockchip,pins =
1965 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1966 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1967 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1968 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1969 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1970 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1971 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1972 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1973 };
1974 };
1975
1976 lcdc {
1977 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1978 rockchip,pins =
1979 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1980 };
1981
1982 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1983 rockchip,pins =
1984 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1985 };
1986
1987 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1988 rockchip,pins =
1989 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1990 };
1991
1992 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1993 rockchip,pins =
1994 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1995 };
1996
1997 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1998 rockchip,pins =
1999 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2000 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2001 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2002 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2003 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2004 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2005 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2006 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2007 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2008 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2009 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2010 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2011 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2012 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2013 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2014 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2015 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2016 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2017 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2018 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2019 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2020 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2021 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2022 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2023 };
2024
2025 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2026 rockchip,pins =
2027 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2028 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2029 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2030 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2031 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2032 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2033 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2034 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2035 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2036 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2037 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2038 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2039 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2040 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2041 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2042 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2043 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2044 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2045 };
2046
2047 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2048 rockchip,pins =
2049 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2050 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2051 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2052 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2053 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2054 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2055 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2056 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2057 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2058 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2059 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2060 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2061 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2062 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2063 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2064 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2065 };
2066
2067 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2068 rockchip,pins =
2069 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2070 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2071 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2072 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2073 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2074 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2075 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2076 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2077 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2078 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2079 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2080 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2081 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2082 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2083 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2084 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2085 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2086 };
2087
2088 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2089 rockchip,pins =
2090 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2091 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2092 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2093 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2094 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2095 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2096 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2097 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2098 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2099 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2100 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2101 };
2102
2103 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2104 rockchip,pins =
2105 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2106 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2107 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2108 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2109 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2110 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2111 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2112 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2113 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2114 };
2115 };
2116
2117 pwm0 {
2118 pwm0_pin: pwm0-pin {
2119 rockchip,pins =
2120 <0 RK_PB7 1 &pcfg_pull_none>;
2121 };
2122 };
2123
2124 pwm1 {
2125 pwm1_pin: pwm1-pin {
2126 rockchip,pins =
2127 <0 RK_PC0 1 &pcfg_pull_none>;
2128 };
2129 };
2130
2131 pwm2 {
2132 pwm2_pin: pwm2-pin {
2133 rockchip,pins =
2134 <2 RK_PB5 1 &pcfg_pull_none>;
2135 };
2136 };
2137
2138 pwm3 {
2139 pwm3_pin: pwm3-pin {
2140 rockchip,pins =
2141 <0 RK_PC1 1 &pcfg_pull_none>;
2142 };
2143 };
2144
2145 pwm4 {
2146 pwm4_pin: pwm4-pin {
2147 rockchip,pins =
2148 <3 RK_PC2 3 &pcfg_pull_none>;
2149 };
2150 };
2151
2152 pwm5 {
2153 pwm5_pin: pwm5-pin {
2154 rockchip,pins =
2155 <3 RK_PC3 3 &pcfg_pull_none>;
2156 };
2157 };
2158
2159 pwm6 {
2160 pwm6_pin: pwm6-pin {
2161 rockchip,pins =
2162 <3 RK_PC4 3 &pcfg_pull_none>;
2163 };
2164 };
2165
2166 pwm7 {
2167 pwm7_pin: pwm7-pin {
2168 rockchip,pins =
2169 <3 RK_PC5 3 &pcfg_pull_none>;
2170 };
2171 };
2172
2173 gmac {
2174 rmii_pins: rmii-pins {
2175 rockchip,pins =
2176 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2177 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2178 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2179 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2180 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2181 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2182 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2183 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2184 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2185 };
2186
2187 mac_refclk_12ma: mac-refclk-12ma {
2188 rockchip,pins =
2189 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2190 };
2191
2192 mac_refclk: mac-refclk {
2193 rockchip,pins =
2194 <2 RK_PB2 2 &pcfg_pull_none>;
2195 };
2196 };
2197
2198 cif-m0 {
2199 cif_clkout_m0: cif-clkout-m0 {
2200 rockchip,pins =
2201 <2 RK_PB3 1 &pcfg_pull_none>;
2202 };
2203
2204 dvp_d2d9_m0: dvp-d2d9-m0 {
2205 rockchip,pins =
2206 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2207 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2208 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2209 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2210 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2211 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2212 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2213 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2214 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2215 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2216 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2217 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2218 };
2219
2220 dvp_d0d1_m0: dvp-d0d1-m0 {
2221 rockchip,pins =
2222 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2223 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2224 };
2225
2226 dvp_d10d11_m0:d10-d11-m0 {
2227 rockchip,pins =
2228 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2229 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2230 };
2231 };
2232
2233 cif-m1 {
2234 cif_clkout_m1: cif-clkout-m1 {
2235 rockchip,pins =
2236 <3 RK_PD0 3 &pcfg_pull_none>;
2237 };
2238
2239 dvp_d2d9_m1: dvp-d2d9-m1 {
2240 rockchip,pins =
2241 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2242 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2243 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2244 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2245 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2246 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2247 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2248 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2249 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2250 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2251 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2252 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2253 };
2254
2255 dvp_d0d1_m1: dvp-d0d1-m1 {
2256 rockchip,pins =
2257 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2258 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2259 };
2260
2261 dvp_d10d11_m1:d10-d11-m1 {
2262 rockchip,pins =
2263 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2264 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2265 };
2266 };
2267
2268 isp {
2269 isp_prelight: isp-prelight {
2270 rockchip,pins =
2271 <3 RK_PD1 4 &pcfg_pull_none>;
2272 };
2273 };
2274 };
2275 };
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