]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - arch/arm64/boot/dts/rockchip/rk3328.dtsi
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
arm64: dts: rockchip: fix rk3328 sdmmc0 write errors
[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / boot / dts / rockchip / rk3328.dtsi
1 /*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3328-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51
52 / {
53 compatible = "rockchip,rk3328";
54
55 interrupt-parent = <&gic>;
56 #address-cells = <2>;
57 #size-cells = <2>;
58
59 aliases {
60 serial0 = &uart0;
61 serial1 = &uart1;
62 serial2 = &uart2;
63 i2c0 = &i2c0;
64 i2c1 = &i2c1;
65 i2c2 = &i2c2;
66 i2c3 = &i2c3;
67 ethernet0 = &gmac2io;
68 ethernet1 = &gmac2phy;
69 };
70
71 cpus {
72 #address-cells = <2>;
73 #size-cells = <0>;
74
75 cpu0: cpu@0 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a53", "arm,armv8";
78 reg = <0x0 0x0>;
79 clocks = <&cru ARMCLK>;
80 #cooling-cells = <2>;
81 dynamic-power-coefficient = <120>;
82 enable-method = "psci";
83 next-level-cache = <&l2>;
84 operating-points-v2 = <&cpu0_opp_table>;
85 };
86
87 cpu1: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53", "arm,armv8";
90 reg = <0x0 0x1>;
91 clocks = <&cru ARMCLK>;
92 dynamic-power-coefficient = <120>;
93 enable-method = "psci";
94 next-level-cache = <&l2>;
95 operating-points-v2 = <&cpu0_opp_table>;
96 };
97
98 cpu2: cpu@2 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x2>;
102 clocks = <&cru ARMCLK>;
103 dynamic-power-coefficient = <120>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 operating-points-v2 = <&cpu0_opp_table>;
107 };
108
109 cpu3: cpu@3 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a53", "arm,armv8";
112 reg = <0x0 0x3>;
113 clocks = <&cru ARMCLK>;
114 dynamic-power-coefficient = <120>;
115 enable-method = "psci";
116 next-level-cache = <&l2>;
117 operating-points-v2 = <&cpu0_opp_table>;
118 };
119
120 l2: l2-cache0 {
121 compatible = "cache";
122 };
123 };
124
125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
127 opp-shared;
128
129 opp-408000000 {
130 opp-hz = /bits/ 64 <408000000>;
131 opp-microvolt = <950000>;
132 clock-latency-ns = <40000>;
133 opp-suspend;
134 };
135 opp-600000000 {
136 opp-hz = /bits/ 64 <600000000>;
137 opp-microvolt = <950000>;
138 clock-latency-ns = <40000>;
139 };
140 opp-816000000 {
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
143 clock-latency-ns = <40000>;
144 };
145 opp-1008000000 {
146 opp-hz = /bits/ 64 <1008000000>;
147 opp-microvolt = <1100000>;
148 clock-latency-ns = <40000>;
149 };
150 opp-1200000000 {
151 opp-hz = /bits/ 64 <1200000000>;
152 opp-microvolt = <1225000>;
153 clock-latency-ns = <40000>;
154 };
155 opp-1296000000 {
156 opp-hz = /bits/ 64 <1296000000>;
157 opp-microvolt = <1300000>;
158 clock-latency-ns = <40000>;
159 };
160 };
161
162 amba {
163 compatible = "simple-bus";
164 #address-cells = <2>;
165 #size-cells = <2>;
166 ranges;
167
168 dmac: dmac@ff1f0000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0x0 0xff1f0000 0x0 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru ACLK_DMAC>;
174 clock-names = "apb_pclk";
175 #dma-cells = <1>;
176 };
177 };
178
179 arm-pmu {
180 compatible = "arm,cortex-a53-pmu";
181 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
186 };
187
188 psci {
189 compatible = "arm,psci-1.0", "arm,psci-0.2";
190 method = "smc";
191 };
192
193 timer {
194 compatible = "arm,armv8-timer";
195 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
196 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
197 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
199 };
200
201 xin24m: xin24m {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <24000000>;
205 clock-output-names = "xin24m";
206 };
207
208 i2s0: i2s@ff000000 {
209 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
210 reg = <0x0 0xff000000 0x0 0x1000>;
211 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
213 clock-names = "i2s_clk", "i2s_hclk";
214 dmas = <&dmac 11>, <&dmac 12>;
215 dma-names = "tx", "rx";
216 status = "disabled";
217 };
218
219 i2s1: i2s@ff010000 {
220 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
221 reg = <0x0 0xff010000 0x0 0x1000>;
222 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
224 clock-names = "i2s_clk", "i2s_hclk";
225 dmas = <&dmac 14>, <&dmac 15>;
226 dma-names = "tx", "rx";
227 status = "disabled";
228 };
229
230 i2s2: i2s@ff020000 {
231 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
232 reg = <0x0 0xff020000 0x0 0x1000>;
233 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
235 clock-names = "i2s_clk", "i2s_hclk";
236 dmas = <&dmac 0>, <&dmac 1>;
237 dma-names = "tx", "rx";
238 status = "disabled";
239 };
240
241 spdif: spdif@ff030000 {
242 compatible = "rockchip,rk3328-spdif";
243 reg = <0x0 0xff030000 0x0 0x1000>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
246 clock-names = "mclk", "hclk";
247 dmas = <&dmac 10>;
248 dma-names = "tx";
249 pinctrl-names = "default";
250 pinctrl-0 = <&spdifm2_tx>;
251 status = "disabled";
252 };
253
254 pdm: pdm@ff040000 {
255 compatible = "rockchip,pdm";
256 reg = <0x0 0xff040000 0x0 0x1000>;
257 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
258 clock-names = "pdm_clk", "pdm_hclk";
259 dmas = <&dmac 16>;
260 dma-names = "rx";
261 pinctrl-names = "default", "sleep";
262 pinctrl-0 = <&pdmm0_clk
263 &pdmm0_sdi0
264 &pdmm0_sdi1
265 &pdmm0_sdi2
266 &pdmm0_sdi3>;
267 pinctrl-1 = <&pdmm0_clk_sleep
268 &pdmm0_sdi0_sleep
269 &pdmm0_sdi1_sleep
270 &pdmm0_sdi2_sleep
271 &pdmm0_sdi3_sleep>;
272 status = "disabled";
273 };
274
275 grf: syscon@ff100000 {
276 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
277 reg = <0x0 0xff100000 0x0 0x1000>;
278 #address-cells = <1>;
279 #size-cells = <1>;
280
281 io_domains: io-domains {
282 compatible = "rockchip,rk3328-io-voltage-domain";
283 status = "disabled";
284 };
285
286 power: power-controller {
287 compatible = "rockchip,rk3328-power-controller";
288 #power-domain-cells = <1>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 pd_hevc@RK3328_PD_HEVC {
293 reg = <RK3328_PD_HEVC>;
294 };
295 pd_video@RK3328_PD_VIDEO {
296 reg = <RK3328_PD_VIDEO>;
297 };
298 pd_vpu@RK3328_PD_VPU {
299 reg = <RK3328_PD_VPU>;
300 };
301 };
302
303 reboot-mode {
304 compatible = "syscon-reboot-mode";
305 offset = <0x5c8>;
306 mode-normal = <BOOT_NORMAL>;
307 mode-recovery = <BOOT_RECOVERY>;
308 mode-bootloader = <BOOT_FASTBOOT>;
309 mode-loader = <BOOT_BL_DOWNLOAD>;
310 };
311
312 };
313
314 uart0: serial@ff110000 {
315 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff110000 0x0 0x100>;
317 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
319 clock-names = "baudclk", "apb_pclk";
320 dmas = <&dmac 2>, <&dmac 3>;
321 #dma-cells = <2>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
324 reg-io-width = <4>;
325 reg-shift = <2>;
326 status = "disabled";
327 };
328
329 uart1: serial@ff120000 {
330 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
331 reg = <0x0 0xff120000 0x0 0x100>;
332 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
334 clock-names = "baudclk", "apb_pclk";
335 dmas = <&dmac 4>, <&dmac 5>;
336 #dma-cells = <2>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
339 reg-io-width = <4>;
340 reg-shift = <2>;
341 status = "disabled";
342 };
343
344 uart2: serial@ff130000 {
345 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
346 reg = <0x0 0xff130000 0x0 0x100>;
347 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clock-names = "baudclk", "apb_pclk";
350 dmas = <&dmac 6>, <&dmac 7>;
351 #dma-cells = <2>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart2m1_xfer>;
354 reg-io-width = <4>;
355 reg-shift = <2>;
356 status = "disabled";
357 };
358
359 i2c0: i2c@ff150000 {
360 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
361 reg = <0x0 0xff150000 0x0 0x1000>;
362 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
366 clock-names = "i2c", "pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c0_xfer>;
369 status = "disabled";
370 };
371
372 i2c1: i2c@ff160000 {
373 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
374 reg = <0x0 0xff160000 0x0 0x1000>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
379 clock-names = "i2c", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c1_xfer>;
382 status = "disabled";
383 };
384
385 i2c2: i2c@ff170000 {
386 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
387 reg = <0x0 0xff170000 0x0 0x1000>;
388 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
390 #size-cells = <0>;
391 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
392 clock-names = "i2c", "pclk";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c2_xfer>;
395 status = "disabled";
396 };
397
398 i2c3: i2c@ff180000 {
399 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
400 reg = <0x0 0xff180000 0x0 0x1000>;
401 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
405 clock-names = "i2c", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c3_xfer>;
408 status = "disabled";
409 };
410
411 spi0: spi@ff190000 {
412 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
413 reg = <0x0 0xff190000 0x0 0x1000>;
414 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
416 #size-cells = <0>;
417 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
418 clock-names = "spiclk", "apb_pclk";
419 dmas = <&dmac 8>, <&dmac 9>;
420 dma-names = "tx", "rx";
421 pinctrl-names = "default";
422 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
423 status = "disabled";
424 };
425
426 wdt: watchdog@ff1a0000 {
427 compatible = "snps,dw-wdt";
428 reg = <0x0 0xff1a0000 0x0 0x100>;
429 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
430 };
431
432 pwm0: pwm@ff1b0000 {
433 compatible = "rockchip,rk3328-pwm";
434 reg = <0x0 0xff1b0000 0x0 0x10>;
435 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
436 clock-names = "pwm", "pclk";
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm0_pin>;
439 #pwm-cells = <3>;
440 status = "disabled";
441 };
442
443 pwm1: pwm@ff1b0010 {
444 compatible = "rockchip,rk3328-pwm";
445 reg = <0x0 0xff1b0010 0x0 0x10>;
446 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
447 clock-names = "pwm", "pclk";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pwm1_pin>;
450 #pwm-cells = <3>;
451 status = "disabled";
452 };
453
454 pwm2: pwm@ff1b0020 {
455 compatible = "rockchip,rk3328-pwm";
456 reg = <0x0 0xff1b0020 0x0 0x10>;
457 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
458 clock-names = "pwm", "pclk";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm2_pin>;
461 #pwm-cells = <3>;
462 status = "disabled";
463 };
464
465 pwm3: pwm@ff1b0030 {
466 compatible = "rockchip,rk3328-pwm";
467 reg = <0x0 0xff1b0030 0x0 0x10>;
468 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwmir_pin>;
473 #pwm-cells = <3>;
474 status = "disabled";
475 };
476
477 thermal-zones {
478 soc_thermal: soc-thermal {
479 polling-delay-passive = <20>;
480 polling-delay = <1000>;
481 sustainable-power = <1000>;
482
483 thermal-sensors = <&tsadc 0>;
484
485 trips {
486 threshold: trip-point0 {
487 temperature = <70000>;
488 hysteresis = <2000>;
489 type = "passive";
490 };
491 target: trip-point1 {
492 temperature = <85000>;
493 hysteresis = <2000>;
494 type = "passive";
495 };
496 soc_crit: soc-crit {
497 temperature = <95000>;
498 hysteresis = <2000>;
499 type = "critical";
500 };
501 };
502
503 cooling-maps {
504 map0 {
505 trip = <&target>;
506 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
507 contribution = <4096>;
508 };
509 };
510 };
511
512 };
513
514 tsadc: tsadc@ff250000 {
515 compatible = "rockchip,rk3328-tsadc";
516 reg = <0x0 0xff250000 0x0 0x100>;
517 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
518 assigned-clocks = <&cru SCLK_TSADC>;
519 assigned-clock-rates = <50000>;
520 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
521 clock-names = "tsadc", "apb_pclk";
522 pinctrl-names = "init", "default", "sleep";
523 pinctrl-0 = <&otp_gpio>;
524 pinctrl-1 = <&otp_out>;
525 pinctrl-2 = <&otp_gpio>;
526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 rockchip,grf = <&grf>;
529 rockchip,hw-tshut-temp = <100000>;
530 #thermal-sensor-cells = <1>;
531 status = "disabled";
532 };
533
534 saradc: adc@ff280000 {
535 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
536 reg = <0x0 0xff280000 0x0 0x100>;
537 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
538 #io-channel-cells = <1>;
539 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
540 clock-names = "saradc", "apb_pclk";
541 resets = <&cru SRST_SARADC_P>;
542 reset-names = "saradc-apb";
543 status = "disabled";
544 };
545
546 h265e_mmu: iommu@ff330200 {
547 compatible = "rockchip,iommu";
548 reg = <0x0 0xff330200 0 0x100>;
549 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
550 interrupt-names = "h265e_mmu";
551 #iommu-cells = <0>;
552 status = "disabled";
553 };
554
555 vepu_mmu: iommu@ff340800 {
556 compatible = "rockchip,iommu";
557 reg = <0x0 0xff340800 0x0 0x40>;
558 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-names = "vepu_mmu";
560 #iommu-cells = <0>;
561 status = "disabled";
562 };
563
564 vpu_mmu: iommu@ff350800 {
565 compatible = "rockchip,iommu";
566 reg = <0x0 0xff350800 0x0 0x40>;
567 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
568 interrupt-names = "vpu_mmu";
569 #iommu-cells = <0>;
570 status = "disabled";
571 };
572
573 rkvdec_mmu: iommu@ff360480 {
574 compatible = "rockchip,iommu";
575 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
576 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "rkvdec_mmu";
578 #iommu-cells = <0>;
579 status = "disabled";
580 };
581
582 vop_mmu: iommu@ff373f00 {
583 compatible = "rockchip,iommu";
584 reg = <0x0 0xff373f00 0x0 0x100>;
585 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
586 interrupt-names = "vop_mmu";
587 #iommu-cells = <0>;
588 status = "disabled";
589 };
590
591 cru: clock-controller@ff440000 {
592 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
593 reg = <0x0 0xff440000 0x0 0x1000>;
594 rockchip,grf = <&grf>;
595 #clock-cells = <1>;
596 #reset-cells = <1>;
597 assigned-clocks =
598 /*
599 * CPLL should run at 1200, but that is to high for
600 * the initial dividers of most of its children.
601 * We need set cpll child clk div first,
602 * and then set the cpll frequency.
603 */
604 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
605 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
606 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
607 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
608 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
609 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
610 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
611 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
612 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
613 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
614 <&cru SCLK_WIFI>, <&cru ARMCLK>,
615 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
616 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
617 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
618 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
619 <&cru SCLK_RTC32K>;
620 assigned-clock-parents =
621 <&cru HDMIPHY>, <&cru PLL_APLL>,
622 <&cru PLL_GPLL>, <&xin24m>,
623 <&xin24m>, <&xin24m>;
624 assigned-clock-rates =
625 <0>, <61440000>,
626 <0>, <24000000>,
627 <24000000>, <24000000>,
628 <15000000>, <15000000>,
629 <100000000>, <100000000>,
630 <100000000>, <100000000>,
631 <50000000>, <100000000>,
632 <100000000>, <100000000>,
633 <50000000>, <50000000>,
634 <50000000>, <50000000>,
635 <24000000>, <600000000>,
636 <491520000>, <1200000000>,
637 <150000000>, <75000000>,
638 <75000000>, <150000000>,
639 <75000000>, <75000000>,
640 <32768>;
641 };
642
643 usb2phy_grf: syscon@ff450000 {
644 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
645 "simple-mfd";
646 reg = <0x0 0xff450000 0x0 0x10000>;
647 #address-cells = <1>;
648 #size-cells = <1>;
649
650 u2phy: usb2-phy@100 {
651 compatible = "rockchip,rk3328-usb2phy";
652 reg = <0x100 0x10>;
653 clocks = <&xin24m>;
654 clock-names = "phyclk";
655 clock-output-names = "usb480m_phy";
656 #clock-cells = <0>;
657 assigned-clocks = <&cru USB480M>;
658 assigned-clock-parents = <&u2phy>;
659 status = "disabled";
660
661 u2phy_otg: otg-port {
662 #phy-cells = <0>;
663 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
666 interrupt-names = "otg-bvalid", "otg-id",
667 "linestate";
668 status = "disabled";
669 };
670
671 u2phy_host: host-port {
672 #phy-cells = <0>;
673 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-names = "linestate";
675 status = "disabled";
676 };
677 };
678 };
679
680 sdmmc: dwmmc@ff500000 {
681 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
682 reg = <0x0 0xff500000 0x0 0x4000>;
683 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
685 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
686 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
687 fifo-depth = <0x100>;
688 status = "disabled";
689 };
690
691 sdio: dwmmc@ff510000 {
692 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
693 reg = <0x0 0xff510000 0x0 0x4000>;
694 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
696 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
697 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
698 fifo-depth = <0x100>;
699 status = "disabled";
700 };
701
702 emmc: dwmmc@ff520000 {
703 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
704 reg = <0x0 0xff520000 0x0 0x4000>;
705 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
707 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
708 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
709 fifo-depth = <0x100>;
710 status = "disabled";
711 };
712
713 gmac2io: ethernet@ff540000 {
714 compatible = "rockchip,rk3328-gmac";
715 reg = <0x0 0xff540000 0x0 0x10000>;
716 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
717 interrupt-names = "macirq";
718 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
719 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
720 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
721 <&cru PCLK_MAC2IO>;
722 clock-names = "stmmaceth", "mac_clk_rx",
723 "mac_clk_tx", "clk_mac_ref",
724 "clk_mac_refout", "aclk_mac",
725 "pclk_mac";
726 resets = <&cru SRST_GMAC2IO_A>;
727 reset-names = "stmmaceth";
728 rockchip,grf = <&grf>;
729 status = "disabled";
730 };
731
732 gmac2phy: ethernet@ff550000 {
733 compatible = "rockchip,rk3328-gmac";
734 reg = <0x0 0xff550000 0x0 0x10000>;
735 rockchip,grf = <&grf>;
736 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
737 interrupt-names = "macirq";
738 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
739 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
740 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
741 <&cru SCLK_MAC2PHY_OUT>;
742 clock-names = "stmmaceth", "mac_clk_rx",
743 "mac_clk_tx", "clk_mac_ref",
744 "aclk_mac", "pclk_mac",
745 "clk_macphy";
746 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
747 reset-names = "stmmaceth", "mac-phy";
748 phy-mode = "rmii";
749 phy-handle = <&phy>;
750 status = "disabled";
751
752 mdio {
753 compatible = "snps,dwmac-mdio";
754 #address-cells = <1>;
755 #size-cells = <0>;
756
757 phy: phy@0 {
758 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
759 reg = <0>;
760 clocks = <&cru SCLK_MAC2PHY_OUT>;
761 resets = <&cru SRST_MACPHY>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
764 phy-is-integrated;
765 };
766 };
767 };
768
769 usb20_otg: usb@ff580000 {
770 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
771 "snps,dwc2";
772 reg = <0x0 0xff580000 0x0 0x40000>;
773 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cru HCLK_OTG>;
775 clock-names = "otg";
776 dr_mode = "otg";
777 g-np-tx-fifo-size = <16>;
778 g-rx-fifo-size = <280>;
779 g-tx-fifo-size = <256 128 128 64 32 16>;
780 g-use-dma;
781 phys = <&u2phy_otg>;
782 phy-names = "usb2-phy";
783 status = "disabled";
784 };
785
786 usb_host0_ehci: usb@ff5c0000 {
787 compatible = "generic-ehci";
788 reg = <0x0 0xff5c0000 0x0 0x10000>;
789 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru HCLK_HOST0>, <&u2phy>;
791 clock-names = "usbhost", "utmi";
792 phys = <&u2phy_host>;
793 phy-names = "usb";
794 status = "disabled";
795 };
796
797 usb_host0_ohci: usb@ff5d0000 {
798 compatible = "generic-ohci";
799 reg = <0x0 0xff5d0000 0x0 0x10000>;
800 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cru HCLK_HOST0>, <&u2phy>;
802 clock-names = "usbhost", "utmi";
803 phys = <&u2phy_host>;
804 phy-names = "usb";
805 status = "disabled";
806 };
807
808 gic: interrupt-controller@ff811000 {
809 compatible = "arm,gic-400";
810 #interrupt-cells = <3>;
811 #address-cells = <0>;
812 interrupt-controller;
813 reg = <0x0 0xff811000 0 0x1000>,
814 <0x0 0xff812000 0 0x2000>,
815 <0x0 0xff814000 0 0x2000>,
816 <0x0 0xff816000 0 0x2000>;
817 interrupts = <GIC_PPI 9
818 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
819 };
820
821 pinctrl: pinctrl {
822 compatible = "rockchip,rk3328-pinctrl";
823 rockchip,grf = <&grf>;
824 #address-cells = <2>;
825 #size-cells = <2>;
826 ranges;
827
828 gpio0: gpio0@ff210000 {
829 compatible = "rockchip,gpio-bank";
830 reg = <0x0 0xff210000 0x0 0x100>;
831 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&cru PCLK_GPIO0>;
833
834 gpio-controller;
835 #gpio-cells = <2>;
836
837 interrupt-controller;
838 #interrupt-cells = <2>;
839 };
840
841 gpio1: gpio1@ff220000 {
842 compatible = "rockchip,gpio-bank";
843 reg = <0x0 0xff220000 0x0 0x100>;
844 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cru PCLK_GPIO1>;
846
847 gpio-controller;
848 #gpio-cells = <2>;
849
850 interrupt-controller;
851 #interrupt-cells = <2>;
852 };
853
854 gpio2: gpio2@ff230000 {
855 compatible = "rockchip,gpio-bank";
856 reg = <0x0 0xff230000 0x0 0x100>;
857 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&cru PCLK_GPIO2>;
859
860 gpio-controller;
861 #gpio-cells = <2>;
862
863 interrupt-controller;
864 #interrupt-cells = <2>;
865 };
866
867 gpio3: gpio3@ff240000 {
868 compatible = "rockchip,gpio-bank";
869 reg = <0x0 0xff240000 0x0 0x100>;
870 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru PCLK_GPIO3>;
872
873 gpio-controller;
874 #gpio-cells = <2>;
875
876 interrupt-controller;
877 #interrupt-cells = <2>;
878 };
879
880 pcfg_pull_up: pcfg-pull-up {
881 bias-pull-up;
882 };
883
884 pcfg_pull_down: pcfg-pull-down {
885 bias-pull-down;
886 };
887
888 pcfg_pull_none: pcfg-pull-none {
889 bias-disable;
890 };
891
892 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
893 bias-disable;
894 drive-strength = <2>;
895 };
896
897 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
898 bias-pull-up;
899 drive-strength = <2>;
900 };
901
902 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
903 bias-pull-up;
904 drive-strength = <4>;
905 };
906
907 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
908 bias-disable;
909 drive-strength = <4>;
910 };
911
912 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
913 bias-pull-down;
914 drive-strength = <4>;
915 };
916
917 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
918 bias-disable;
919 drive-strength = <8>;
920 };
921
922 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
923 bias-pull-up;
924 drive-strength = <8>;
925 };
926
927 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
928 bias-disable;
929 drive-strength = <12>;
930 };
931
932 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
933 bias-pull-up;
934 drive-strength = <12>;
935 };
936
937 pcfg_output_high: pcfg-output-high {
938 output-high;
939 };
940
941 pcfg_output_low: pcfg-output-low {
942 output-low;
943 };
944
945 pcfg_input_high: pcfg-input-high {
946 bias-pull-up;
947 input-enable;
948 };
949
950 pcfg_input: pcfg-input {
951 input-enable;
952 };
953
954 i2c0 {
955 i2c0_xfer: i2c0-xfer {
956 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
957 <2 RK_PD1 1 &pcfg_pull_none>;
958 };
959 };
960
961 i2c1 {
962 i2c1_xfer: i2c1-xfer {
963 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
964 <2 RK_PA5 2 &pcfg_pull_none>;
965 };
966 };
967
968 i2c2 {
969 i2c2_xfer: i2c2-xfer {
970 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
971 <2 RK_PB6 1 &pcfg_pull_none>;
972 };
973 };
974
975 i2c3 {
976 i2c3_xfer: i2c3-xfer {
977 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
978 <0 RK_PA6 2 &pcfg_pull_none>;
979 };
980 i2c3_gpio: i2c3-gpio {
981 rockchip,pins =
982 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
983 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
984 };
985 };
986
987 hdmi_i2c {
988 hdmii2c_xfer: hdmii2c-xfer {
989 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
990 <0 RK_PA6 1 &pcfg_pull_none>;
991 };
992 };
993
994 pdm-0 {
995 pdmm0_clk: pdmm0-clk {
996 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
997 };
998
999 pdmm0_fsync: pdmm0-fsync {
1000 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1001 };
1002
1003 pdmm0_sdi0: pdmm0-sdi0 {
1004 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1005 };
1006
1007 pdmm0_sdi1: pdmm0-sdi1 {
1008 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1009 };
1010
1011 pdmm0_sdi2: pdmm0-sdi2 {
1012 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1013 };
1014
1015 pdmm0_sdi3: pdmm0-sdi3 {
1016 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1017 };
1018
1019 pdmm0_clk_sleep: pdmm0-clk-sleep {
1020 rockchip,pins =
1021 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1022 };
1023
1024 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1025 rockchip,pins =
1026 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1027 };
1028
1029 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1030 rockchip,pins =
1031 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1032 };
1033
1034 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1035 rockchip,pins =
1036 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1037 };
1038
1039 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1040 rockchip,pins =
1041 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1042 };
1043
1044 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1045 rockchip,pins =
1046 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1047 };
1048 };
1049
1050 tsadc {
1051 otp_gpio: otp-gpio {
1052 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1053 };
1054
1055 otp_out: otp-out {
1056 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1057 };
1058 };
1059
1060 uart0 {
1061 uart0_xfer: uart0-xfer {
1062 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1063 <1 RK_PB0 1 &pcfg_pull_none>;
1064 };
1065
1066 uart0_cts: uart0-cts {
1067 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1068 };
1069
1070 uart0_rts: uart0-rts {
1071 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1072 };
1073
1074 uart0_rts_gpio: uart0-rts-gpio {
1075 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1076 };
1077 };
1078
1079 uart1 {
1080 uart1_xfer: uart1-xfer {
1081 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1082 <3 RK_PA6 4 &pcfg_pull_none>;
1083 };
1084
1085 uart1_cts: uart1-cts {
1086 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1087 };
1088
1089 uart1_rts: uart1-rts {
1090 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1091 };
1092
1093 uart1_rts_gpio: uart1-rts-gpio {
1094 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1095 };
1096 };
1097
1098 uart2-0 {
1099 uart2m0_xfer: uart2m0-xfer {
1100 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1101 <1 RK_PA1 2 &pcfg_pull_none>;
1102 };
1103 };
1104
1105 uart2-1 {
1106 uart2m1_xfer: uart2m1-xfer {
1107 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1108 <2 RK_PA1 1 &pcfg_pull_none>;
1109 };
1110 };
1111
1112 spi0-0 {
1113 spi0m0_clk: spi0m0-clk {
1114 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1115 };
1116
1117 spi0m0_cs0: spi0m0-cs0 {
1118 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1119 };
1120
1121 spi0m0_tx: spi0m0-tx {
1122 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1123 };
1124
1125 spi0m0_rx: spi0m0-rx {
1126 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1127 };
1128
1129 spi0m0_cs1: spi0m0-cs1 {
1130 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1131 };
1132 };
1133
1134 spi0-1 {
1135 spi0m1_clk: spi0m1-clk {
1136 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1137 };
1138
1139 spi0m1_cs0: spi0m1-cs0 {
1140 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1141 };
1142
1143 spi0m1_tx: spi0m1-tx {
1144 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1145 };
1146
1147 spi0m1_rx: spi0m1-rx {
1148 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1149 };
1150
1151 spi0m1_cs1: spi0m1-cs1 {
1152 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1153 };
1154 };
1155
1156 spi0-2 {
1157 spi0m2_clk: spi0m2-clk {
1158 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1159 };
1160
1161 spi0m2_cs0: spi0m2-cs0 {
1162 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1163 };
1164
1165 spi0m2_tx: spi0m2-tx {
1166 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1167 };
1168
1169 spi0m2_rx: spi0m2-rx {
1170 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1171 };
1172 };
1173
1174 i2s1 {
1175 i2s1_mclk: i2s1-mclk {
1176 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1177 };
1178
1179 i2s1_sclk: i2s1-sclk {
1180 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1181 };
1182
1183 i2s1_lrckrx: i2s1-lrckrx {
1184 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1185 };
1186
1187 i2s1_lrcktx: i2s1-lrcktx {
1188 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1189 };
1190
1191 i2s1_sdi: i2s1-sdi {
1192 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1193 };
1194
1195 i2s1_sdo: i2s1-sdo {
1196 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1197 };
1198
1199 i2s1_sdio1: i2s1-sdio1 {
1200 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1201 };
1202
1203 i2s1_sdio2: i2s1-sdio2 {
1204 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1205 };
1206
1207 i2s1_sdio3: i2s1-sdio3 {
1208 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1209 };
1210
1211 i2s1_sleep: i2s1-sleep {
1212 rockchip,pins =
1213 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1214 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1215 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1216 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1217 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1218 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1219 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1220 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1221 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1222 };
1223 };
1224
1225 i2s2-0 {
1226 i2s2m0_mclk: i2s2m0-mclk {
1227 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1228 };
1229
1230 i2s2m0_sclk: i2s2m0-sclk {
1231 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1232 };
1233
1234 i2s2m0_lrckrx: i2s2m0-lrckrx {
1235 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1236 };
1237
1238 i2s2m0_lrcktx: i2s2m0-lrcktx {
1239 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1240 };
1241
1242 i2s2m0_sdi: i2s2m0-sdi {
1243 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1244 };
1245
1246 i2s2m0_sdo: i2s2m0-sdo {
1247 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1248 };
1249
1250 i2s2m0_sleep: i2s2m0-sleep {
1251 rockchip,pins =
1252 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1253 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1254 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1255 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1256 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1257 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1258 };
1259 };
1260
1261 i2s2-1 {
1262 i2s2m1_mclk: i2s2m1-mclk {
1263 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1264 };
1265
1266 i2s2m1_sclk: i2s2m1-sclk {
1267 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1268 };
1269
1270 i2s2m1_lrckrx: i2sm1-lrckrx {
1271 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1272 };
1273
1274 i2s2m1_lrcktx: i2s2m1-lrcktx {
1275 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1276 };
1277
1278 i2s2m1_sdi: i2s2m1-sdi {
1279 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1280 };
1281
1282 i2s2m1_sdo: i2s2m1-sdo {
1283 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1284 };
1285
1286 i2s2m1_sleep: i2s2m1-sleep {
1287 rockchip,pins =
1288 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1289 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1290 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1291 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1292 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1293 };
1294 };
1295
1296 spdif-0 {
1297 spdifm0_tx: spdifm0-tx {
1298 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1299 };
1300 };
1301
1302 spdif-1 {
1303 spdifm1_tx: spdifm1-tx {
1304 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1305 };
1306 };
1307
1308 spdif-2 {
1309 spdifm2_tx: spdifm2-tx {
1310 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1311 };
1312 };
1313
1314 sdmmc0-0 {
1315 sdmmc0m0_pwren: sdmmc0m0-pwren {
1316 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1317 };
1318
1319 sdmmc0m0_gpio: sdmmc0m0-gpio {
1320 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1321 };
1322 };
1323
1324 sdmmc0-1 {
1325 sdmmc0m1_pwren: sdmmc0m1-pwren {
1326 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1327 };
1328
1329 sdmmc0m1_gpio: sdmmc0m1-gpio {
1330 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1331 };
1332 };
1333
1334 sdmmc0 {
1335 sdmmc0_clk: sdmmc0-clk {
1336 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1337 };
1338
1339 sdmmc0_cmd: sdmmc0-cmd {
1340 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1341 };
1342
1343 sdmmc0_dectn: sdmmc0-dectn {
1344 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1345 };
1346
1347 sdmmc0_wrprt: sdmmc0-wrprt {
1348 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1349 };
1350
1351 sdmmc0_bus1: sdmmc0-bus1 {
1352 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1353 };
1354
1355 sdmmc0_bus4: sdmmc0-bus4 {
1356 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1357 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1358 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1359 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1360 };
1361
1362 sdmmc0_gpio: sdmmc0-gpio {
1363 rockchip,pins =
1364 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1365 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1366 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1367 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1368 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1369 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1370 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1371 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1372 };
1373 };
1374
1375 sdmmc0ext {
1376 sdmmc0ext_clk: sdmmc0ext-clk {
1377 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1378 };
1379
1380 sdmmc0ext_cmd: sdmmc0ext-cmd {
1381 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1382 };
1383
1384 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1385 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1386 };
1387
1388 sdmmc0ext_dectn: sdmmc0ext-dectn {
1389 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1390 };
1391
1392 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1393 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1394 };
1395
1396 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1397 rockchip,pins =
1398 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1399 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1400 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1401 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1402 };
1403
1404 sdmmc0ext_gpio: sdmmc0ext-gpio {
1405 rockchip,pins =
1406 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1407 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1408 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1409 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1410 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1411 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1412 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1413 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1414 };
1415 };
1416
1417 sdmmc1 {
1418 sdmmc1_clk: sdmmc1-clk {
1419 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1420 };
1421
1422 sdmmc1_cmd: sdmmc1-cmd {
1423 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1424 };
1425
1426 sdmmc1_pwren: sdmmc1-pwren {
1427 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1428 };
1429
1430 sdmmc1_wrprt: sdmmc1-wrprt {
1431 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1432 };
1433
1434 sdmmc1_dectn: sdmmc1-dectn {
1435 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1436 };
1437
1438 sdmmc1_bus1: sdmmc1-bus1 {
1439 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1440 };
1441
1442 sdmmc1_bus4: sdmmc1-bus4 {
1443 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1444 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1445 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1446 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1447 };
1448
1449 sdmmc1_gpio: sdmmc1-gpio {
1450 rockchip,pins =
1451 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1452 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1453 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1454 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1455 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1456 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1457 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1458 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1459 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1460 };
1461 };
1462
1463 emmc {
1464 emmc_clk: emmc-clk {
1465 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1466 };
1467
1468 emmc_cmd: emmc-cmd {
1469 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1470 };
1471
1472 emmc_pwren: emmc-pwren {
1473 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1474 };
1475
1476 emmc_rstnout: emmc-rstnout {
1477 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1478 };
1479
1480 emmc_bus1: emmc-bus1 {
1481 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1482 };
1483
1484 emmc_bus4: emmc-bus4 {
1485 rockchip,pins =
1486 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1487 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1488 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1489 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1490 };
1491
1492 emmc_bus8: emmc-bus8 {
1493 rockchip,pins =
1494 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1495 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1496 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1497 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1498 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1499 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1500 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1501 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1502 };
1503 };
1504
1505 pwm0 {
1506 pwm0_pin: pwm0-pin {
1507 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1508 };
1509 };
1510
1511 pwm1 {
1512 pwm1_pin: pwm1-pin {
1513 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1514 };
1515 };
1516
1517 pwm2 {
1518 pwm2_pin: pwm2-pin {
1519 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1520 };
1521 };
1522
1523 pwmir {
1524 pwmir_pin: pwmir-pin {
1525 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1526 };
1527 };
1528
1529 gmac-1 {
1530 rgmiim1_pins: rgmiim1-pins {
1531 rockchip,pins =
1532 /* mac_txclk */
1533 <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1534 /* mac_rxclk */
1535 <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1536 /* mac_mdio */
1537 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1538 /* mac_txen */
1539 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1540 /* mac_clk */
1541 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1542 /* mac_rxdv */
1543 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1544 /* mac_mdc */
1545 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1546 /* mac_rxd1 */
1547 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1548 /* mac_rxd0 */
1549 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1550 /* mac_txd1 */
1551 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1552 /* mac_txd0 */
1553 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1554 /* mac_rxd3 */
1555 <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1556 /* mac_rxd2 */
1557 <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1558 /* mac_txd3 */
1559 <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1560 /* mac_txd2 */
1561 <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1562
1563 /* mac_txclk */
1564 <0 RK_PB0 1 &pcfg_pull_none>,
1565 /* mac_txen */
1566 <0 RK_PB4 1 &pcfg_pull_none>,
1567 /* mac_clk */
1568 <0 RK_PD0 1 &pcfg_pull_none>,
1569 /* mac_txd1 */
1570 <0 RK_PC0 1 &pcfg_pull_none>,
1571 /* mac_txd0 */
1572 <0 RK_PC1 1 &pcfg_pull_none>,
1573 /* mac_txd3 */
1574 <0 RK_PC7 1 &pcfg_pull_none>,
1575 /* mac_txd2 */
1576 <0 RK_PC6 1 &pcfg_pull_none>;
1577 };
1578
1579 rmiim1_pins: rmiim1-pins {
1580 rockchip,pins =
1581 /* mac_mdio */
1582 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1583 /* mac_txen */
1584 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1585 /* mac_clk */
1586 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1587 /* mac_rxer */
1588 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1589 /* mac_rxdv */
1590 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1591 /* mac_mdc */
1592 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1593 /* mac_rxd1 */
1594 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1595 /* mac_rxd0 */
1596 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1597 /* mac_txd1 */
1598 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1599 /* mac_txd0 */
1600 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1601
1602 /* mac_mdio */
1603 <0 RK_PB3 1 &pcfg_pull_none>,
1604 /* mac_txen */
1605 <0 RK_PB4 1 &pcfg_pull_none>,
1606 /* mac_clk */
1607 <0 RK_PD0 1 &pcfg_pull_none>,
1608 /* mac_mdc */
1609 <0 RK_PC3 1 &pcfg_pull_none>,
1610 /* mac_txd1 */
1611 <0 RK_PC0 1 &pcfg_pull_none>,
1612 /* mac_txd0 */
1613 <0 RK_PC1 1 &pcfg_pull_none>;
1614 };
1615 };
1616
1617 gmac2phy {
1618 fephyled_speed100: fephyled-speed100 {
1619 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1620 };
1621
1622 fephyled_speed10: fephyled-speed10 {
1623 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1624 };
1625
1626 fephyled_duplex: fephyled-duplex {
1627 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1628 };
1629
1630 fephyled_rxm0: fephyled-rxm0 {
1631 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1632 };
1633
1634 fephyled_txm0: fephyled-txm0 {
1635 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1636 };
1637
1638 fephyled_linkm0: fephyled-linkm0 {
1639 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1640 };
1641
1642 fephyled_rxm1: fephyled-rxm1 {
1643 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1644 };
1645
1646 fephyled_txm1: fephyled-txm1 {
1647 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1648 };
1649
1650 fephyled_linkm1: fephyled-linkm1 {
1651 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1652 };
1653 };
1654
1655 tsadc_pin {
1656 tsadc_int: tsadc-int {
1657 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1658 };
1659 tsadc_gpio: tsadc-gpio {
1660 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1661 };
1662 };
1663
1664 hdmi_pin {
1665 hdmi_cec: hdmi-cec {
1666 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1667 };
1668
1669 hdmi_hpd: hdmi-hpd {
1670 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1671 };
1672 };
1673
1674 cif-0 {
1675 dvp_d2d9_m0:dvp-d2d9-m0 {
1676 rockchip,pins =
1677 /* cif_d0 */
1678 <3 RK_PA4 2 &pcfg_pull_none>,
1679 /* cif_d1 */
1680 <3 RK_PA5 2 &pcfg_pull_none>,
1681 /* cif_d2 */
1682 <3 RK_PA6 2 &pcfg_pull_none>,
1683 /* cif_d3 */
1684 <3 RK_PA7 2 &pcfg_pull_none>,
1685 /* cif_d4 */
1686 <3 RK_PB0 2 &pcfg_pull_none>,
1687 /* cif_d5m0 */
1688 <3 RK_PB1 2 &pcfg_pull_none>,
1689 /* cif_d6m0 */
1690 <3 RK_PB2 2 &pcfg_pull_none>,
1691 /* cif_d7m0 */
1692 <3 RK_PB3 2 &pcfg_pull_none>,
1693 /* cif_href */
1694 <3 RK_PA1 2 &pcfg_pull_none>,
1695 /* cif_vsync */
1696 <3 RK_PA0 2 &pcfg_pull_none>,
1697 /* cif_clkoutm0 */
1698 <3 RK_PA3 2 &pcfg_pull_none>,
1699 /* cif_clkin */
1700 <3 RK_PA2 2 &pcfg_pull_none>;
1701 };
1702 };
1703
1704 cif-1 {
1705 dvp_d2d9_m1:dvp-d2d9-m1 {
1706 rockchip,pins =
1707 /* cif_d0 */
1708 <3 RK_PA4 2 &pcfg_pull_none>,
1709 /* cif_d1 */
1710 <3 RK_PA5 2 &pcfg_pull_none>,
1711 /* cif_d2 */
1712 <3 RK_PA6 2 &pcfg_pull_none>,
1713 /* cif_d3 */
1714 <3 RK_PA7 2 &pcfg_pull_none>,
1715 /* cif_d4 */
1716 <3 RK_PB0 2 &pcfg_pull_none>,
1717 /* cif_d5m1 */
1718 <2 RK_PC0 4 &pcfg_pull_none>,
1719 /* cif_d6m1 */
1720 <2 RK_PC1 4 &pcfg_pull_none>,
1721 /* cif_d7m1 */
1722 <2 RK_PC2 4 &pcfg_pull_none>,
1723 /* cif_href */
1724 <3 RK_PA1 2 &pcfg_pull_none>,
1725 /* cif_vsync */
1726 <3 RK_PA0 2 &pcfg_pull_none>,
1727 /* cif_clkoutm1 */
1728 <2 RK_PB7 4 &pcfg_pull_none>,
1729 /* cif_clkin */
1730 <3 RK_PA2 2 &pcfg_pull_none>;
1731 };
1732 };
1733 };
1734 };
ubuntu-bionic-kernel mirror