]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - arch/arm64/boot/dts/rockchip/rk3368.dtsi
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: sti: fix missing clk_disable_unprepare() on error in uni_player_start()
[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi
1 /*
2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
49
50 / {
51 compatible = "rockchip,rk3368";
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 aliases {
57 ethernet0 = &gmac;
58 i2c0 = &i2c0;
59 i2c1 = &i2c1;
60 i2c2 = &i2c2;
61 i2c3 = &i2c3;
62 i2c4 = &i2c4;
63 i2c5 = &i2c5;
64 serial0 = &uart0;
65 serial1 = &uart1;
66 serial2 = &uart2;
67 serial3 = &uart3;
68 serial4 = &uart4;
69 spi0 = &spi0;
70 spi1 = &spi1;
71 spi2 = &spi2;
72 };
73
74 cpus {
75 #address-cells = <0x2>;
76 #size-cells = <0x0>;
77
78 cpu-map {
79 cluster0 {
80 core0 {
81 cpu = <&cpu_b0>;
82 };
83 core1 {
84 cpu = <&cpu_b1>;
85 };
86 core2 {
87 cpu = <&cpu_b2>;
88 };
89 core3 {
90 cpu = <&cpu_b3>;
91 };
92 };
93
94 cluster1 {
95 core0 {
96 cpu = <&cpu_l0>;
97 };
98 core1 {
99 cpu = <&cpu_l1>;
100 };
101 core2 {
102 cpu = <&cpu_l2>;
103 };
104 core3 {
105 cpu = <&cpu_l3>;
106 };
107 };
108 };
109
110 idle-states {
111 entry-method = "psci";
112
113 cpu_sleep: cpu-sleep-0 {
114 compatible = "arm,idle-state";
115 arm,psci-suspend-param = <0x1010000>;
116 entry-latency-us = <0x3fffffff>;
117 exit-latency-us = <0x40000000>;
118 min-residency-us = <0xffffffff>;
119 };
120 };
121
122 cpu_l0: cpu@0 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a53", "arm,armv8";
125 reg = <0x0 0x0>;
126 cpu-idle-states = <&cpu_sleep>;
127 enable-method = "psci";
128
129 #cooling-cells = <2>; /* min followed by max */
130 };
131
132 cpu_l1: cpu@1 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a53", "arm,armv8";
135 reg = <0x0 0x1>;
136 cpu-idle-states = <&cpu_sleep>;
137 enable-method = "psci";
138 };
139
140 cpu_l2: cpu@2 {
141 device_type = "cpu";
142 compatible = "arm,cortex-a53", "arm,armv8";
143 reg = <0x0 0x2>;
144 cpu-idle-states = <&cpu_sleep>;
145 enable-method = "psci";
146 };
147
148 cpu_l3: cpu@3 {
149 device_type = "cpu";
150 compatible = "arm,cortex-a53", "arm,armv8";
151 reg = <0x0 0x3>;
152 cpu-idle-states = <&cpu_sleep>;
153 enable-method = "psci";
154 };
155
156 cpu_b0: cpu@100 {
157 device_type = "cpu";
158 compatible = "arm,cortex-a53", "arm,armv8";
159 reg = <0x0 0x100>;
160 cpu-idle-states = <&cpu_sleep>;
161 enable-method = "psci";
162
163 #cooling-cells = <2>; /* min followed by max */
164 };
165
166 cpu_b1: cpu@101 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a53", "arm,armv8";
169 reg = <0x0 0x101>;
170 cpu-idle-states = <&cpu_sleep>;
171 enable-method = "psci";
172 };
173
174 cpu_b2: cpu@102 {
175 device_type = "cpu";
176 compatible = "arm,cortex-a53", "arm,armv8";
177 reg = <0x0 0x102>;
178 cpu-idle-states = <&cpu_sleep>;
179 enable-method = "psci";
180 };
181
182 cpu_b3: cpu@103 {
183 device_type = "cpu";
184 compatible = "arm,cortex-a53", "arm,armv8";
185 reg = <0x0 0x103>;
186 cpu-idle-states = <&cpu_sleep>;
187 enable-method = "psci";
188 };
189 };
190
191 arm-pmu {
192 compatible = "arm,armv8-pmuv3";
193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
202 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
203 <&cpu_b2>, <&cpu_b3>;
204 };
205
206 psci {
207 compatible = "arm,psci-0.2";
208 method = "smc";
209 };
210
211 timer {
212 compatible = "arm,armv8-timer";
213 interrupts = <GIC_PPI 13
214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
215 <GIC_PPI 14
216 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
217 <GIC_PPI 11
218 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
219 <GIC_PPI 10
220 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
221 };
222
223 xin24m: oscillator {
224 compatible = "fixed-clock";
225 clock-frequency = <24000000>;
226 clock-output-names = "xin24m";
227 #clock-cells = <0>;
228 };
229
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
232 reg = <0x0 0xff0c0000 0x0 0x4000>;
233 clock-freq-min-max = <400000 150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 status = "disabled";
240 };
241
242 sdio0: dwmmc@ff0d0000 {
243 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
244 reg = <0x0 0xff0d0000 0x0 0x4000>;
245 clock-freq-min-max = <400000 150000000>;
246 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
247 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled";
252 };
253
254 emmc: dwmmc@ff0f0000 {
255 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
256 reg = <0x0 0xff0f0000 0x0 0x4000>;
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
259 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
263 status = "disabled";
264 };
265
266 saradc: saradc@ff100000 {
267 compatible = "rockchip,saradc";
268 reg = <0x0 0xff100000 0x0 0x100>;
269 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
270 #io-channel-cells = <1>;
271 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
272 clock-names = "saradc", "apb_pclk";
273 status = "disabled";
274 };
275
276 spi0: spi@ff110000 {
277 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
278 reg = <0x0 0xff110000 0x0 0x1000>;
279 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
280 clock-names = "spiclk", "apb_pclk";
281 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 status = "disabled";
287 };
288
289 spi1: spi@ff120000 {
290 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
291 reg = <0x0 0xff120000 0x0 0x1000>;
292 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
293 clock-names = "spiclk", "apb_pclk";
294 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
301
302 spi2: spi@ff130000 {
303 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
304 reg = <0x0 0xff130000 0x0 0x1000>;
305 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
306 clock-names = "spiclk", "apb_pclk";
307 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 i2c1: i2c@ff140000 {
316 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
317 reg = <0x0 0xff140000 0x0 0x1000>;
318 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 clock-names = "i2c";
322 clocks = <&cru PCLK_I2C1>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&i2c1_xfer>;
325 status = "disabled";
326 };
327
328 i2c3: i2c@ff150000 {
329 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
330 reg = <0x0 0xff150000 0x0 0x1000>;
331 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 clock-names = "i2c";
335 clocks = <&cru PCLK_I2C3>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c3_xfer>;
338 status = "disabled";
339 };
340
341 i2c4: i2c@ff160000 {
342 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
343 reg = <0x0 0xff160000 0x0 0x1000>;
344 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 clock-names = "i2c";
348 clocks = <&cru PCLK_I2C4>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&i2c4_xfer>;
351 status = "disabled";
352 };
353
354 i2c5: i2c@ff170000 {
355 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
356 reg = <0x0 0xff170000 0x0 0x1000>;
357 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 clock-names = "i2c";
361 clocks = <&cru PCLK_I2C5>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&i2c5_xfer>;
364 status = "disabled";
365 };
366
367 uart0: serial@ff180000 {
368 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
369 reg = <0x0 0xff180000 0x0 0x100>;
370 clock-frequency = <24000000>;
371 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
372 clock-names = "baudclk", "apb_pclk";
373 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
374 reg-shift = <2>;
375 reg-io-width = <4>;
376 status = "disabled";
377 };
378
379 uart1: serial@ff190000 {
380 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
381 reg = <0x0 0xff190000 0x0 0x100>;
382 clock-frequency = <24000000>;
383 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
384 clock-names = "baudclk", "apb_pclk";
385 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
386 reg-shift = <2>;
387 reg-io-width = <4>;
388 status = "disabled";
389 };
390
391 uart3: serial@ff1b0000 {
392 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
393 reg = <0x0 0xff1b0000 0x0 0x100>;
394 clock-frequency = <24000000>;
395 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
396 clock-names = "baudclk", "apb_pclk";
397 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
398 reg-shift = <2>;
399 reg-io-width = <4>;
400 status = "disabled";
401 };
402
403 uart4: serial@ff1c0000 {
404 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
405 reg = <0x0 0xff1c0000 0x0 0x100>;
406 clock-frequency = <24000000>;
407 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
408 clock-names = "baudclk", "apb_pclk";
409 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
410 reg-shift = <2>;
411 reg-io-width = <4>;
412 status = "disabled";
413 };
414
415 thermal-zones {
416 cpu {
417 polling-delay-passive = <100>; /* milliseconds */
418 polling-delay = <5000>; /* milliseconds */
419
420 thermal-sensors = <&tsadc 0>;
421
422 trips {
423 cpu_alert0: cpu_alert0 {
424 temperature = <75000>; /* millicelsius */
425 hysteresis = <2000>; /* millicelsius */
426 type = "passive";
427 };
428 cpu_alert1: cpu_alert1 {
429 temperature = <80000>; /* millicelsius */
430 hysteresis = <2000>; /* millicelsius */
431 type = "passive";
432 };
433 cpu_crit: cpu_crit {
434 temperature = <95000>; /* millicelsius */
435 hysteresis = <2000>; /* millicelsius */
436 type = "critical";
437 };
438 };
439
440 cooling-maps {
441 map0 {
442 trip = <&cpu_alert0>;
443 cooling-device =
444 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
445 };
446 map1 {
447 trip = <&cpu_alert1>;
448 cooling-device =
449 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
450 };
451 };
452 };
453
454 gpu {
455 polling-delay-passive = <100>; /* milliseconds */
456 polling-delay = <5000>; /* milliseconds */
457
458 thermal-sensors = <&tsadc 1>;
459
460 trips {
461 gpu_alert0: gpu_alert0 {
462 temperature = <80000>; /* millicelsius */
463 hysteresis = <2000>; /* millicelsius */
464 type = "passive";
465 };
466 gpu_crit: gpu_crit {
467 temperature = <115000>; /* millicelsius */
468 hysteresis = <2000>; /* millicelsius */
469 type = "critical";
470 };
471 };
472
473 cooling-maps {
474 map0 {
475 trip = <&gpu_alert0>;
476 cooling-device =
477 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
478 };
479 };
480 };
481 };
482
483 tsadc: tsadc@ff280000 {
484 compatible = "rockchip,rk3368-tsadc";
485 reg = <0x0 0xff280000 0x0 0x100>;
486 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
488 clock-names = "tsadc", "apb_pclk";
489 resets = <&cru SRST_TSADC>;
490 reset-names = "tsadc-apb";
491 pinctrl-names = "init", "default", "sleep";
492 pinctrl-0 = <&otp_gpio>;
493 pinctrl-1 = <&otp_out>;
494 pinctrl-2 = <&otp_gpio>;
495 #thermal-sensor-cells = <1>;
496 rockchip,hw-tshut-temp = <95000>;
497 status = "disabled";
498 };
499
500 gmac: ethernet@ff290000 {
501 compatible = "rockchip,rk3368-gmac";
502 reg = <0x0 0xff290000 0x0 0x10000>;
503 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
504 interrupt-names = "macirq";
505 rockchip,grf = <&grf>;
506 clocks = <&cru SCLK_MAC>,
507 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
508 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
509 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
510 clock-names = "stmmaceth",
511 "mac_clk_rx", "mac_clk_tx",
512 "clk_mac_ref", "clk_mac_refout",
513 "aclk_mac", "pclk_mac";
514 status = "disabled";
515 };
516
517 usb_host0_ehci: usb@ff500000 {
518 compatible = "generic-ehci";
519 reg = <0x0 0xff500000 0x0 0x100>;
520 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&cru HCLK_HOST0>;
522 clock-names = "usbhost";
523 status = "disabled";
524 };
525
526 usb_otg: usb@ff580000 {
527 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
528 "snps,dwc2";
529 reg = <0x0 0xff580000 0x0 0x40000>;
530 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&cru HCLK_OTG0>;
532 clock-names = "otg";
533 dr_mode = "otg";
534 g-np-tx-fifo-size = <16>;
535 g-rx-fifo-size = <275>;
536 g-tx-fifo-size = <256 128 128 64 64 32>;
537 g-use-dma;
538 status = "disabled";
539 };
540
541 i2c0: i2c@ff650000 {
542 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
543 reg = <0x0 0xff650000 0x0 0x1000>;
544 clocks = <&cru PCLK_I2C0>;
545 clock-names = "i2c";
546 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c0_xfer>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551 status = "disabled";
552 };
553
554 i2c2: i2c@ff660000 {
555 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
556 reg = <0x0 0xff660000 0x0 0x1000>;
557 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 clock-names = "i2c";
561 clocks = <&cru PCLK_I2C2>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&i2c2_xfer>;
564 status = "disabled";
565 };
566
567 pwm0: pwm@ff680000 {
568 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
569 reg = <0x0 0xff680000 0x0 0x10>;
570 #pwm-cells = <3>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&pwm0_pin>;
573 clocks = <&cru PCLK_PWM1>;
574 clock-names = "pwm";
575 status = "disabled";
576 };
577
578 pwm1: pwm@ff680010 {
579 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580 reg = <0x0 0xff680010 0x0 0x10>;
581 #pwm-cells = <3>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&pwm1_pin>;
584 clocks = <&cru PCLK_PWM1>;
585 clock-names = "pwm";
586 status = "disabled";
587 };
588
589 pwm2: pwm@ff680020 {
590 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
591 reg = <0x0 0xff680020 0x0 0x10>;
592 #pwm-cells = <3>;
593 clocks = <&cru PCLK_PWM1>;
594 clock-names = "pwm";
595 status = "disabled";
596 };
597
598 pwm3: pwm@ff680030 {
599 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
600 reg = <0x0 0xff680030 0x0 0x10>;
601 #pwm-cells = <3>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&pwm3_pin>;
604 clocks = <&cru PCLK_PWM1>;
605 clock-names = "pwm";
606 status = "disabled";
607 };
608
609 uart2: serial@ff690000 {
610 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
611 reg = <0x0 0xff690000 0x0 0x100>;
612 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
613 clock-names = "baudclk", "apb_pclk";
614 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&uart2_xfer>;
617 reg-shift = <2>;
618 reg-io-width = <4>;
619 status = "disabled";
620 };
621
622 mbox: mbox@ff6b0000 {
623 compatible = "rockchip,rk3368-mailbox";
624 reg = <0x0 0xff6b0000 0x0 0x1000>;
625 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cru PCLK_MAILBOX>;
630 clock-names = "pclk_mailbox";
631 #mbox-cells = <1>;
632 };
633
634 pmugrf: syscon@ff738000 {
635 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
636 reg = <0x0 0xff738000 0x0 0x1000>;
637
638 pmu_io_domains: io-domains {
639 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
640 status = "disabled";
641 };
642 };
643
644 cru: clock-controller@ff760000 {
645 compatible = "rockchip,rk3368-cru";
646 reg = <0x0 0xff760000 0x0 0x1000>;
647 rockchip,grf = <&grf>;
648 #clock-cells = <1>;
649 #reset-cells = <1>;
650 };
651
652 grf: syscon@ff770000 {
653 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
654 reg = <0x0 0xff770000 0x0 0x1000>;
655
656 io_domains: io-domains {
657 compatible = "rockchip,rk3368-io-voltage-domain";
658 status = "disabled";
659 };
660 };
661
662 wdt: watchdog@ff800000 {
663 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
664 reg = <0x0 0xff800000 0x0 0x100>;
665 clocks = <&cru PCLK_WDT>;
666 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
667 status = "disabled";
668 };
669
670 timer@ff810000 {
671 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
672 reg = <0x0 0xff810000 0x0 0x20>;
673 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
674 };
675
676 gic: interrupt-controller@ffb71000 {
677 compatible = "arm,gic-400";
678 interrupt-controller;
679 #interrupt-cells = <3>;
680 #address-cells = <0>;
681
682 reg = <0x0 0xffb71000 0x0 0x1000>,
683 <0x0 0xffb72000 0x0 0x2000>,
684 <0x0 0xffb74000 0x0 0x2000>,
685 <0x0 0xffb76000 0x0 0x2000>;
686 interrupts = <GIC_PPI 9
687 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
688 };
689
690 pinctrl: pinctrl {
691 compatible = "rockchip,rk3368-pinctrl";
692 rockchip,grf = <&grf>;
693 rockchip,pmu = <&pmugrf>;
694 #address-cells = <0x2>;
695 #size-cells = <0x2>;
696 ranges;
697
698 gpio0: gpio0@ff750000 {
699 compatible = "rockchip,gpio-bank";
700 reg = <0x0 0xff750000 0x0 0x100>;
701 clocks = <&cru PCLK_GPIO0>;
702 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
703
704 gpio-controller;
705 #gpio-cells = <0x2>;
706
707 interrupt-controller;
708 #interrupt-cells = <0x2>;
709 };
710
711 gpio1: gpio1@ff780000 {
712 compatible = "rockchip,gpio-bank";
713 reg = <0x0 0xff780000 0x0 0x100>;
714 clocks = <&cru PCLK_GPIO1>;
715 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
716
717 gpio-controller;
718 #gpio-cells = <0x2>;
719
720 interrupt-controller;
721 #interrupt-cells = <0x2>;
722 };
723
724 gpio2: gpio2@ff790000 {
725 compatible = "rockchip,gpio-bank";
726 reg = <0x0 0xff790000 0x0 0x100>;
727 clocks = <&cru PCLK_GPIO2>;
728 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
729
730 gpio-controller;
731 #gpio-cells = <0x2>;
732
733 interrupt-controller;
734 #interrupt-cells = <0x2>;
735 };
736
737 gpio3: gpio3@ff7a0000 {
738 compatible = "rockchip,gpio-bank";
739 reg = <0x0 0xff7a0000 0x0 0x100>;
740 clocks = <&cru PCLK_GPIO3>;
741 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
742
743 gpio-controller;
744 #gpio-cells = <0x2>;
745
746 interrupt-controller;
747 #interrupt-cells = <0x2>;
748 };
749
750 pcfg_pull_up: pcfg-pull-up {
751 bias-pull-up;
752 };
753
754 pcfg_pull_down: pcfg-pull-down {
755 bias-pull-down;
756 };
757
758 pcfg_pull_none: pcfg-pull-none {
759 bias-disable;
760 };
761
762 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
763 bias-disable;
764 drive-strength = <12>;
765 };
766
767 emmc {
768 emmc_clk: emmc-clk {
769 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
770 };
771
772 emmc_cmd: emmc-cmd {
773 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
774 };
775
776 emmc_pwr: emmc-pwr {
777 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
778 };
779
780 emmc_bus1: emmc-bus1 {
781 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
782 };
783
784 emmc_bus4: emmc-bus4 {
785 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
786 <1 19 RK_FUNC_2 &pcfg_pull_up>,
787 <1 20 RK_FUNC_2 &pcfg_pull_up>,
788 <1 21 RK_FUNC_2 &pcfg_pull_up>;
789 };
790
791 emmc_bus8: emmc-bus8 {
792 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
793 <1 19 RK_FUNC_2 &pcfg_pull_up>,
794 <1 20 RK_FUNC_2 &pcfg_pull_up>,
795 <1 21 RK_FUNC_2 &pcfg_pull_up>,
796 <1 22 RK_FUNC_2 &pcfg_pull_up>,
797 <1 23 RK_FUNC_2 &pcfg_pull_up>,
798 <1 24 RK_FUNC_2 &pcfg_pull_up>,
799 <1 25 RK_FUNC_2 &pcfg_pull_up>;
800 };
801 };
802
803 gmac {
804 rgmii_pins: rgmii-pins {
805 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
806 <3 24 RK_FUNC_1 &pcfg_pull_none>,
807 <3 19 RK_FUNC_1 &pcfg_pull_none>,
808 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
809 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
810 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
811 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
812 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
813 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
814 <3 15 RK_FUNC_1 &pcfg_pull_none>,
815 <3 16 RK_FUNC_1 &pcfg_pull_none>,
816 <3 17 RK_FUNC_1 &pcfg_pull_none>,
817 <3 18 RK_FUNC_1 &pcfg_pull_none>,
818 <3 25 RK_FUNC_1 &pcfg_pull_none>,
819 <3 20 RK_FUNC_1 &pcfg_pull_none>;
820 };
821
822 rmii_pins: rmii-pins {
823 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
824 <3 24 RK_FUNC_1 &pcfg_pull_none>,
825 <3 19 RK_FUNC_1 &pcfg_pull_none>,
826 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
827 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
828 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
829 <3 15 RK_FUNC_1 &pcfg_pull_none>,
830 <3 16 RK_FUNC_1 &pcfg_pull_none>,
831 <3 20 RK_FUNC_1 &pcfg_pull_none>,
832 <3 21 RK_FUNC_1 &pcfg_pull_none>;
833 };
834 };
835
836 i2c0 {
837 i2c0_xfer: i2c0-xfer {
838 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
839 <0 7 RK_FUNC_1 &pcfg_pull_none>;
840 };
841 };
842
843 i2c1 {
844 i2c1_xfer: i2c1-xfer {
845 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
846 <2 22 RK_FUNC_1 &pcfg_pull_none>;
847 };
848 };
849
850 i2c2 {
851 i2c2_xfer: i2c2-xfer {
852 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
853 <3 31 RK_FUNC_2 &pcfg_pull_none>;
854 };
855 };
856
857 i2c3 {
858 i2c3_xfer: i2c3-xfer {
859 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
860 <1 17 RK_FUNC_1 &pcfg_pull_none>;
861 };
862 };
863
864 i2c4 {
865 i2c4_xfer: i2c4-xfer {
866 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
867 <3 25 RK_FUNC_2 &pcfg_pull_none>;
868 };
869 };
870
871 i2c5 {
872 i2c5_xfer: i2c5-xfer {
873 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
874 <3 27 RK_FUNC_2 &pcfg_pull_none>;
875 };
876 };
877
878 pwm0 {
879 pwm0_pin: pwm0-pin {
880 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
881 };
882 };
883
884 pwm1 {
885 pwm1_pin: pwm1-pin {
886 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
887 };
888 };
889
890 pwm3 {
891 pwm3_pin: pwm3-pin {
892 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
893 };
894 };
895
896 sdio0 {
897 sdio0_bus1: sdio0-bus1 {
898 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
899 };
900
901 sdio0_bus4: sdio0-bus4 {
902 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
903 <2 29 RK_FUNC_1 &pcfg_pull_up>,
904 <2 30 RK_FUNC_1 &pcfg_pull_up>,
905 <2 31 RK_FUNC_1 &pcfg_pull_up>;
906 };
907
908 sdio0_cmd: sdio0-cmd {
909 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
910 };
911
912 sdio0_clk: sdio0-clk {
913 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
914 };
915
916 sdio0_cd: sdio0-cd {
917 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
918 };
919
920 sdio0_wp: sdio0-wp {
921 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
922 };
923
924 sdio0_pwr: sdio0-pwr {
925 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
926 };
927
928 sdio0_bkpwr: sdio0-bkpwr {
929 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
930 };
931
932 sdio0_int: sdio0-int {
933 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
934 };
935 };
936
937 sdmmc {
938 sdmmc_clk: sdmmc-clk {
939 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
940 };
941
942 sdmmc_cmd: sdmmc-cmd {
943 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
944 };
945
946 sdmmc_cd: sdmmc-cd {
947 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
948 };
949
950 sdmmc_bus1: sdmmc-bus1 {
951 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
952 };
953
954 sdmmc_bus4: sdmmc-bus4 {
955 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
956 <2 6 RK_FUNC_1 &pcfg_pull_up>,
957 <2 7 RK_FUNC_1 &pcfg_pull_up>,
958 <2 8 RK_FUNC_1 &pcfg_pull_up>;
959 };
960 };
961
962 spi0 {
963 spi0_clk: spi0-clk {
964 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
965 };
966 spi0_cs0: spi0-cs0 {
967 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
968 };
969 spi0_cs1: spi0-cs1 {
970 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
971 };
972 spi0_tx: spi0-tx {
973 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
974 };
975 spi0_rx: spi0-rx {
976 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
977 };
978 };
979
980 spi1 {
981 spi1_clk: spi1-clk {
982 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
983 };
984 spi1_cs0: spi1-cs0 {
985 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
986 };
987 spi1_cs1: spi1-cs1 {
988 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
989 };
990 spi1_rx: spi1-rx {
991 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
992 };
993 spi1_tx: spi1-tx {
994 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
995 };
996 };
997
998 spi2 {
999 spi2_clk: spi2-clk {
1000 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1001 };
1002 spi2_cs0: spi2-cs0 {
1003 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1004 };
1005 spi2_rx: spi2-rx {
1006 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1007 };
1008 spi2_tx: spi2-tx {
1009 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1010 };
1011 };
1012
1013 tsadc {
1014 otp_gpio: otp-gpio {
1015 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1016 };
1017
1018 otp_out: otp-out {
1019 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1020 };
1021 };
1022
1023 uart0 {
1024 uart0_xfer: uart0-xfer {
1025 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1026 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1027 };
1028
1029 uart0_cts: uart0-cts {
1030 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1031 };
1032
1033 uart0_rts: uart0-rts {
1034 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1035 };
1036 };
1037
1038 uart1 {
1039 uart1_xfer: uart1-xfer {
1040 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1041 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1042 };
1043
1044 uart1_cts: uart1-cts {
1045 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1046 };
1047
1048 uart1_rts: uart1-rts {
1049 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1050 };
1051 };
1052
1053 uart2 {
1054 uart2_xfer: uart2-xfer {
1055 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1056 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1057 };
1058 /* no rts / cts for uart2 */
1059 };
1060
1061 uart3 {
1062 uart3_xfer: uart3-xfer {
1063 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1064 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1065 };
1066
1067 uart3_cts: uart3-cts {
1068 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1069 };
1070
1071 uart3_rts: uart3-rts {
1072 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1073 };
1074 };
1075
1076 uart4 {
1077 uart4_xfer: uart4-xfer {
1078 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1079 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1080 };
1081
1082 uart4_cts: uart4-cts {
1083 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1084 };
1085
1086 uart4_rts: uart4-rts {
1087 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1088 };
1089 };
1090 };
1091 };
ubuntu-bionic-kernel mirror