2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld11";
16 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53", "arm,armv8";
37 clocks = <&sys_clk 33>;
38 enable-method = "psci";
39 operating-points-v2 = <&cluster0_opp>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 clocks = <&sys_clk 33>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
52 cluster0_opp: opp_table {
53 compatible = "operating-points-v2";
57 opp-hz = /bits/ 64 <245000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <250000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <490000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <500000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <653334000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <666667000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <980000000>;
82 clock-latency-ns = <300>;
87 compatible = "arm,psci-1.0";
93 compatible = "fixed-clock";
95 clock-frequency = <25000000>;
100 compatible = "arm,armv8-timer";
101 interrupts = <1 13 4>,
108 compatible = "simple-bus";
109 #address-cells = <1>;
111 ranges = <0 0 0 0xffffffff>;
113 serial0: serial@54006800 {
114 compatible = "socionext,uniphier-uart";
116 reg = <0x54006800 0x40>;
117 interrupts = <0 33 4>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart0>;
120 clocks = <&peri_clk 0>;
123 serial1: serial@54006900 {
124 compatible = "socionext,uniphier-uart";
126 reg = <0x54006900 0x40>;
127 interrupts = <0 35 4>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_uart1>;
130 clocks = <&peri_clk 1>;
133 serial2: serial@54006a00 {
134 compatible = "socionext,uniphier-uart";
136 reg = <0x54006a00 0x40>;
137 interrupts = <0 37 4>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_uart2>;
140 clocks = <&peri_clk 2>;
143 serial3: serial@54006b00 {
144 compatible = "socionext,uniphier-uart";
146 reg = <0x54006b00 0x40>;
147 interrupts = <0 177 4>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_uart3>;
150 clocks = <&peri_clk 3>;
154 compatible = "socionext,uniphier-ld11-adamv",
155 "simple-mfd", "syscon";
156 reg = <0x57920000 0x1000>;
159 compatible = "socionext,uniphier-ld11-adamv-reset";
165 compatible = "socionext,uniphier-fi2c";
167 reg = <0x58780000 0x80>;
168 #address-cells = <1>;
170 interrupts = <0 41 4>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_i2c0>;
173 clocks = <&peri_clk 4>;
174 clock-frequency = <100000>;
178 compatible = "socionext,uniphier-fi2c";
180 reg = <0x58781000 0x80>;
181 #address-cells = <1>;
183 interrupts = <0 42 4>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_i2c1>;
186 clocks = <&peri_clk 5>;
187 clock-frequency = <100000>;
191 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58782000 0x80>;
193 #address-cells = <1>;
195 interrupts = <0 43 4>;
196 clocks = <&peri_clk 6>;
197 clock-frequency = <400000>;
201 compatible = "socionext,uniphier-fi2c";
203 reg = <0x58783000 0x80>;
204 #address-cells = <1>;
206 interrupts = <0 44 4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_i2c3>;
209 clocks = <&peri_clk 7>;
210 clock-frequency = <100000>;
214 compatible = "socionext,uniphier-fi2c";
216 reg = <0x58784000 0x80>;
217 #address-cells = <1>;
219 interrupts = <0 45 4>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_i2c4>;
222 clocks = <&peri_clk 8>;
223 clock-frequency = <100000>;
227 compatible = "socionext,uniphier-fi2c";
228 reg = <0x58785000 0x80>;
229 #address-cells = <1>;
231 interrupts = <0 25 4>;
232 clocks = <&peri_clk 9>;
233 clock-frequency = <400000>;
236 system_bus: system-bus@58c00000 {
237 compatible = "socionext,uniphier-system-bus";
239 reg = <0x58c00000 0x400>;
240 #address-cells = <2>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_system_bus>;
247 compatible = "socionext,uniphier-smpctrl";
248 reg = <0x59801000 0x400>;
252 compatible = "socionext,uniphier-ld11-sdctrl",
253 "simple-mfd", "syscon";
254 reg = <0x59810000 0x400>;
257 compatible = "socionext,uniphier-ld11-sd-reset";
263 compatible = "socionext,uniphier-ld11-perictrl",
264 "simple-mfd", "syscon";
265 reg = <0x59820000 0x200>;
268 compatible = "socionext,uniphier-ld11-peri-clock";
273 compatible = "socionext,uniphier-ld11-peri-reset";
278 emmc: sdhc@5a000000 {
279 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
280 reg = <0x5a000000 0x400>;
281 interrupts = <0 78 4>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_emmc>;
284 clocks = <&sys_clk 4>;
288 cdns,phy-input-delay-legacy = <4>;
289 cdns,phy-input-delay-mmc-highspeed = <2>;
290 cdns,phy-input-delay-mmc-ddr = <3>;
291 cdns,phy-dll-delay-sdclk = <21>;
292 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
296 compatible = "socionext,uniphier-ehci", "generic-ehci";
298 reg = <0x5a800100 0x100>;
299 interrupts = <0 243 4>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_usb0>;
302 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
303 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
308 compatible = "socionext,uniphier-ehci", "generic-ehci";
310 reg = <0x5a810100 0x100>;
311 interrupts = <0 244 4>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_usb1>;
314 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
315 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
320 compatible = "socionext,uniphier-ehci", "generic-ehci";
322 reg = <0x5a820100 0x100>;
323 interrupts = <0 245 4>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usb2>;
326 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
327 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
332 compatible = "socionext,uniphier-ld11-mioctrl",
333 "simple-mfd", "syscon";
334 reg = <0x5b3e0000 0x800>;
337 compatible = "socionext,uniphier-ld11-mio-clock";
342 compatible = "socionext,uniphier-ld11-mio-reset";
344 resets = <&sys_rst 7>;
349 compatible = "socionext,uniphier-ld11-soc-glue",
350 "simple-mfd", "syscon";
351 reg = <0x5f800000 0x2000>;
354 compatible = "socionext,uniphier-ld11-pinctrl";
358 aidet: aidet@5fc20000 {
359 compatible = "socionext,uniphier-ld11-aidet";
360 reg = <0x5fc20000 0x200>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
365 gic: interrupt-controller@5fe00000 {
366 compatible = "arm,gic-v3";
367 reg = <0x5fe00000 0x10000>, /* GICD */
368 <0x5fe40000 0x80000>; /* GICR */
369 interrupt-controller;
370 #interrupt-cells = <3>;
371 interrupts = <1 9 4>;
375 compatible = "socionext,uniphier-ld11-sysctrl",
376 "simple-mfd", "syscon";
377 reg = <0x61840000 0x10000>;
380 compatible = "socionext,uniphier-ld11-clock";
385 compatible = "socionext,uniphier-ld11-reset";
390 compatible = "socionext,uniphier-wdt";
394 nand: nand@68000000 {
395 compatible = "socionext,uniphier-denali-nand-v5b";
397 reg-names = "nand_data", "denali_reg";
398 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
399 interrupts = <0 65 4>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_nand>;
402 clocks = <&sys_clk 2>;
407 #include "uniphier-pinctrl.dtsi"