2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld20";
16 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a72", "arm,armv8";
46 clocks = <&sys_clk 32>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
53 compatible = "arm,cortex-a72", "arm,armv8";
55 clocks = <&sys_clk 32>;
56 enable-method = "psci";
57 operating-points-v2 = <&cluster0_opp>;
62 compatible = "arm,cortex-a53", "arm,armv8";
64 clocks = <&sys_clk 33>;
65 enable-method = "psci";
66 operating-points-v2 = <&cluster1_opp>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 clocks = <&sys_clk 33>;
74 enable-method = "psci";
75 operating-points-v2 = <&cluster1_opp>;
79 cluster0_opp: opp_table0 {
80 compatible = "operating-points-v2";
84 opp-hz = /bits/ 64 <250000000>;
85 clock-latency-ns = <300>;
88 opp-hz = /bits/ 64 <275000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <500000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <550000000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <666667000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <733334000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <1000000000>;
109 clock-latency-ns = <300>;
112 opp-hz = /bits/ 64 <1100000000>;
113 clock-latency-ns = <300>;
117 cluster1_opp: opp_table1 {
118 compatible = "operating-points-v2";
122 opp-hz = /bits/ 64 <250000000>;
123 clock-latency-ns = <300>;
126 opp-hz = /bits/ 64 <275000000>;
127 clock-latency-ns = <300>;
130 opp-hz = /bits/ 64 <500000000>;
131 clock-latency-ns = <300>;
134 opp-hz = /bits/ 64 <550000000>;
135 clock-latency-ns = <300>;
138 opp-hz = /bits/ 64 <666667000>;
139 clock-latency-ns = <300>;
142 opp-hz = /bits/ 64 <733334000>;
143 clock-latency-ns = <300>;
146 opp-hz = /bits/ 64 <1000000000>;
147 clock-latency-ns = <300>;
150 opp-hz = /bits/ 64 <1100000000>;
151 clock-latency-ns = <300>;
156 compatible = "arm,psci-1.0";
162 compatible = "fixed-clock";
164 clock-frequency = <25000000>;
169 compatible = "arm,armv8-timer";
170 interrupts = <1 13 4>,
177 compatible = "simple-bus";
178 #address-cells = <1>;
180 ranges = <0 0 0 0xffffffff>;
182 serial0: serial@54006800 {
183 compatible = "socionext,uniphier-uart";
185 reg = <0x54006800 0x40>;
186 interrupts = <0 33 4>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_uart0>;
189 clocks = <&peri_clk 0>;
192 serial1: serial@54006900 {
193 compatible = "socionext,uniphier-uart";
195 reg = <0x54006900 0x40>;
196 interrupts = <0 35 4>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart1>;
199 clocks = <&peri_clk 1>;
202 serial2: serial@54006a00 {
203 compatible = "socionext,uniphier-uart";
205 reg = <0x54006a00 0x40>;
206 interrupts = <0 37 4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart2>;
209 clocks = <&peri_clk 2>;
212 serial3: serial@54006b00 {
213 compatible = "socionext,uniphier-uart";
215 reg = <0x54006b00 0x40>;
216 interrupts = <0 177 4>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_uart3>;
219 clocks = <&peri_clk 3>;
223 compatible = "socionext,uniphier-fi2c";
225 reg = <0x58780000 0x80>;
226 #address-cells = <1>;
228 interrupts = <0 41 4>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_i2c0>;
231 clocks = <&peri_clk 4>;
232 clock-frequency = <100000>;
236 compatible = "socionext,uniphier-fi2c";
238 reg = <0x58781000 0x80>;
239 #address-cells = <1>;
241 interrupts = <0 42 4>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c1>;
244 clocks = <&peri_clk 5>;
245 clock-frequency = <100000>;
249 compatible = "socionext,uniphier-fi2c";
250 reg = <0x58782000 0x80>;
251 #address-cells = <1>;
253 interrupts = <0 43 4>;
254 clocks = <&peri_clk 6>;
255 clock-frequency = <400000>;
259 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58783000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 44 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_i2c3>;
267 clocks = <&peri_clk 7>;
268 clock-frequency = <100000>;
272 compatible = "socionext,uniphier-fi2c";
274 reg = <0x58784000 0x80>;
275 #address-cells = <1>;
277 interrupts = <0 45 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c4>;
280 clocks = <&peri_clk 8>;
281 clock-frequency = <100000>;
285 compatible = "socionext,uniphier-fi2c";
286 reg = <0x58785000 0x80>;
287 #address-cells = <1>;
289 interrupts = <0 25 4>;
290 clocks = <&peri_clk 9>;
291 clock-frequency = <400000>;
294 system_bus: system-bus@58c00000 {
295 compatible = "socionext,uniphier-system-bus";
297 reg = <0x58c00000 0x400>;
298 #address-cells = <2>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_system_bus>;
305 compatible = "socionext,uniphier-smpctrl";
306 reg = <0x59801000 0x400>;
310 compatible = "socionext,uniphier-ld20-sdctrl",
311 "simple-mfd", "syscon";
312 reg = <0x59810000 0x800>;
315 compatible = "socionext,uniphier-ld20-sd-clock";
320 compatible = "socionext,uniphier-ld20-sd-reset";
326 compatible = "socionext,uniphier-ld20-perictrl",
327 "simple-mfd", "syscon";
328 reg = <0x59820000 0x200>;
331 compatible = "socionext,uniphier-ld20-peri-clock";
336 compatible = "socionext,uniphier-ld20-peri-reset";
341 emmc: sdhc@5a000000 {
342 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
343 reg = <0x5a000000 0x400>;
344 interrupts = <0 78 4>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_emmc>;
347 clocks = <&sys_clk 4>;
351 cdns,phy-input-delay-legacy = <4>;
352 cdns,phy-input-delay-mmc-highspeed = <2>;
353 cdns,phy-input-delay-mmc-ddr = <3>;
354 cdns,phy-dll-delay-sdclk = <21>;
355 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
359 compatible = "socionext,uniphier-ld20-soc-glue",
360 "simple-mfd", "syscon";
361 reg = <0x5f800000 0x2000>;
364 compatible = "socionext,uniphier-ld20-pinctrl";
368 gic: interrupt-controller@5fe00000 {
369 compatible = "arm,gic-v3";
370 reg = <0x5fe00000 0x10000>, /* GICD */
371 <0x5fe80000 0x80000>; /* GICR */
372 interrupt-controller;
373 #interrupt-cells = <3>;
374 interrupts = <1 9 4>;
378 compatible = "socionext,uniphier-ld20-sysctrl",
379 "simple-mfd", "syscon";
380 reg = <0x61840000 0x10000>;
383 compatible = "socionext,uniphier-ld20-clock";
388 compatible = "socionext,uniphier-ld20-reset";
395 /include/ "uniphier-pinctrl.dtsi"