2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld20";
16 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a72", "arm,armv8";
46 clocks = <&sys_clk 32>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
53 compatible = "arm,cortex-a72", "arm,armv8";
55 clocks = <&sys_clk 32>;
56 enable-method = "psci";
57 operating-points-v2 = <&cluster0_opp>;
62 compatible = "arm,cortex-a53", "arm,armv8";
64 clocks = <&sys_clk 33>;
65 enable-method = "psci";
66 operating-points-v2 = <&cluster1_opp>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 clocks = <&sys_clk 33>;
74 enable-method = "psci";
75 operating-points-v2 = <&cluster1_opp>;
79 cluster0_opp: opp_table0 {
80 compatible = "operating-points-v2";
84 opp-hz = /bits/ 64 <250000000>;
85 clock-latency-ns = <300>;
88 opp-hz = /bits/ 64 <275000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <500000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <550000000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <666667000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <733334000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <1000000000>;
109 clock-latency-ns = <300>;
112 opp-hz = /bits/ 64 <1100000000>;
113 clock-latency-ns = <300>;
117 cluster1_opp: opp_table1 {
118 compatible = "operating-points-v2";
122 opp-hz = /bits/ 64 <250000000>;
123 clock-latency-ns = <300>;
126 opp-hz = /bits/ 64 <275000000>;
127 clock-latency-ns = <300>;
130 opp-hz = /bits/ 64 <500000000>;
131 clock-latency-ns = <300>;
134 opp-hz = /bits/ 64 <550000000>;
135 clock-latency-ns = <300>;
138 opp-hz = /bits/ 64 <666667000>;
139 clock-latency-ns = <300>;
142 opp-hz = /bits/ 64 <733334000>;
143 clock-latency-ns = <300>;
146 opp-hz = /bits/ 64 <1000000000>;
147 clock-latency-ns = <300>;
150 opp-hz = /bits/ 64 <1100000000>;
151 clock-latency-ns = <300>;
156 compatible = "arm,psci-1.0";
162 compatible = "fixed-clock";
164 clock-frequency = <25000000>;
169 compatible = "arm,armv8-timer";
170 interrupts = <1 13 4>,
177 compatible = "simple-bus";
178 #address-cells = <1>;
180 ranges = <0 0 0 0xffffffff>;
182 serial0: serial@54006800 {
183 compatible = "socionext,uniphier-uart";
185 reg = <0x54006800 0x40>;
186 interrupts = <0 33 4>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_uart0>;
189 clocks = <&peri_clk 0>;
192 serial1: serial@54006900 {
193 compatible = "socionext,uniphier-uart";
195 reg = <0x54006900 0x40>;
196 interrupts = <0 35 4>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart1>;
199 clocks = <&peri_clk 1>;
202 serial2: serial@54006a00 {
203 compatible = "socionext,uniphier-uart";
205 reg = <0x54006a00 0x40>;
206 interrupts = <0 37 4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart2>;
209 clocks = <&peri_clk 2>;
212 serial3: serial@54006b00 {
213 compatible = "socionext,uniphier-uart";
215 reg = <0x54006b00 0x40>;
216 interrupts = <0 177 4>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_uart3>;
219 clocks = <&peri_clk 3>;
223 compatible = "socionext,uniphier-ld20-adamv",
224 "simple-mfd", "syscon";
225 reg = <0x57920000 0x1000>;
228 compatible = "socionext,uniphier-ld20-adamv-reset";
234 compatible = "socionext,uniphier-fi2c";
236 reg = <0x58780000 0x80>;
237 #address-cells = <1>;
239 interrupts = <0 41 4>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_i2c0>;
242 clocks = <&peri_clk 4>;
243 clock-frequency = <100000>;
247 compatible = "socionext,uniphier-fi2c";
249 reg = <0x58781000 0x80>;
250 #address-cells = <1>;
252 interrupts = <0 42 4>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_i2c1>;
255 clocks = <&peri_clk 5>;
256 clock-frequency = <100000>;
260 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58782000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 43 4>;
265 clocks = <&peri_clk 6>;
266 clock-frequency = <400000>;
270 compatible = "socionext,uniphier-fi2c";
272 reg = <0x58783000 0x80>;
273 #address-cells = <1>;
275 interrupts = <0 44 4>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_i2c3>;
278 clocks = <&peri_clk 7>;
279 clock-frequency = <100000>;
283 compatible = "socionext,uniphier-fi2c";
285 reg = <0x58784000 0x80>;
286 #address-cells = <1>;
288 interrupts = <0 45 4>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_i2c4>;
291 clocks = <&peri_clk 8>;
292 clock-frequency = <100000>;
296 compatible = "socionext,uniphier-fi2c";
297 reg = <0x58785000 0x80>;
298 #address-cells = <1>;
300 interrupts = <0 25 4>;
301 clocks = <&peri_clk 9>;
302 clock-frequency = <400000>;
305 system_bus: system-bus@58c00000 {
306 compatible = "socionext,uniphier-system-bus";
308 reg = <0x58c00000 0x400>;
309 #address-cells = <2>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_system_bus>;
316 compatible = "socionext,uniphier-smpctrl";
317 reg = <0x59801000 0x400>;
321 compatible = "socionext,uniphier-ld20-sdctrl",
322 "simple-mfd", "syscon";
323 reg = <0x59810000 0x400>;
326 compatible = "socionext,uniphier-ld20-sd-clock";
331 compatible = "socionext,uniphier-ld20-sd-reset";
337 compatible = "socionext,uniphier-ld20-perictrl",
338 "simple-mfd", "syscon";
339 reg = <0x59820000 0x200>;
342 compatible = "socionext,uniphier-ld20-peri-clock";
347 compatible = "socionext,uniphier-ld20-peri-reset";
352 emmc: sdhc@5a000000 {
353 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
354 reg = <0x5a000000 0x400>;
355 interrupts = <0 78 4>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_emmc>;
358 clocks = <&sys_clk 4>;
362 cdns,phy-input-delay-legacy = <4>;
363 cdns,phy-input-delay-mmc-highspeed = <2>;
364 cdns,phy-input-delay-mmc-ddr = <3>;
365 cdns,phy-dll-delay-sdclk = <21>;
366 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
370 compatible = "socionext,uniphier-ld20-soc-glue",
371 "simple-mfd", "syscon";
372 reg = <0x5f800000 0x2000>;
375 compatible = "socionext,uniphier-ld20-pinctrl";
379 aidet: aidet@5fc20000 {
380 compatible = "socionext,uniphier-ld20-aidet";
381 reg = <0x5fc20000 0x200>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
386 gic: interrupt-controller@5fe00000 {
387 compatible = "arm,gic-v3";
388 reg = <0x5fe00000 0x10000>, /* GICD */
389 <0x5fe80000 0x80000>; /* GICR */
390 interrupt-controller;
391 #interrupt-cells = <3>;
392 interrupts = <1 9 4>;
396 compatible = "socionext,uniphier-ld20-sysctrl",
397 "simple-mfd", "syscon";
398 reg = <0x61840000 0x10000>;
401 compatible = "socionext,uniphier-ld20-clock";
406 compatible = "socionext,uniphier-ld20-reset";
411 compatible = "socionext,uniphier-wdt";
415 nand: nand@68000000 {
416 compatible = "socionext,uniphier-denali-nand-v5b";
418 reg-names = "nand_data", "denali_reg";
419 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
420 interrupts = <0 65 4>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_nand>;
423 clocks = <&sys_clk 2>;
428 #include "uniphier-pinctrl.dtsi"