arch/arm64/boot/dts/synaptics/as370.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2018 Synaptics Incorporated
   4  *
   5  * Author: Jisheng Zhang <jszhang@kernel.org>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "syna,as370";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         psci {
  17                 compatible = "arm,psci-1.0";
  18                 method = "smc";
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         compatible = "arm,cortex-a53", "arm,armv8";
  27                         device_type = "cpu";
  28                         reg = <0x0>;
  29                         enable-method = "psci";
  30                         next-level-cache = <&l2>;
  31                         cpu-idle-states = <&CPU_SLEEP_0>;
  32                 };
  33
  34                 cpu1: cpu@1 {
  35                         compatible = "arm,cortex-a53", "arm,armv8";
  36                         device_type = "cpu";
  37                         reg = <0x1>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&l2>;
  40                         cpu-idle-states = <&CPU_SLEEP_0>;
  41                 };
  42
  43                 cpu2: cpu@2 {
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         device_type = "cpu";
  46                         reg = <0x2>;
  47                         enable-method = "psci";
  48                         next-level-cache = <&l2>;
  49                         cpu-idle-states = <&CPU_SLEEP_0>;
  50                 };
  51
  52                 cpu3: cpu@3 {
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         device_type = "cpu";
  55                         reg = <0x3>;
  56                         enable-method = "psci";
  57                         next-level-cache = <&l2>;
  58                         cpu-idle-states = <&CPU_SLEEP_0>;
  59                 };
  60
  61                 l2: cache {
  62                         compatible = "cache";
  63                 };
  64
  65                 idle-states {
  66                         entry-method = "psci";
  67                         CPU_SLEEP_0: cpu-sleep-0 {
  68                                 compatible = "arm,idle-state";
  69                                 local-timer-stop;
  70                                 arm,psci-suspend-param = <0x0010000>;
  71                                 entry-latency-us = <75>;
  72                                 exit-latency-us = <155>;
  73                                 min-residency-us = <1000>;
  74                         };
  75                 };
  76         };
  77
  78         osc: osc {
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 clock-frequency = <25000000>;
  82         };
  83
  84         pmu {
  85                 compatible = "arm,cortex-a53-pmu";
  86                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  88                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  89                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  90                 interrupt-affinity = <&cpu0>,
  91                                      <&cpu1>,
  92                                      <&cpu2>,
  93                                      <&cpu3>;
  94         };
  95
  96         timer {
  97                 compatible = "arm,armv8-timer";
  98                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 100                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 101                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 102         };
 103
 104         soc@f7000000 {
 105                 compatible = "simple-bus";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges = <0 0 0xf7000000 0x1000000>;
 109
 110                 gic: interrupt-controller@901000 {
 111                         compatible = "arm,gic-400";
 112                         #interrupt-cells = <3>;
 113                         interrupt-controller;
 114                         reg = <0x901000 0x1000>,
 115                               <0x902000 0x2000>,
 116                               <0x904000 0x2000>,
 117                               <0x906000 0x2000>;
 118                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 119                 };
 120
 121                 apb@e80000 {
 122                         compatible = "simple-bus";
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         ranges = <0 0xe80000 0x10000>;
 126
 127                         uart0: serial@c00 {
 128                                 compatible = "snps,dw-apb-uart";
 129                                 reg = <0xc00 0x100>;
 130                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 131                                 clocks = <&osc>;
 132                                 reg-shift = <2>;
 133                                 status = "disabled";
 134                         };
 135
 136                         gpio0: gpio@1800 {
 137                                 compatible = "snps,dw-apb-gpio";
 138                                 reg = <0x1800 0x400>;
 139                                 #address-cells = <1>;
 140                                 #size-cells = <0>;
 141
 142                                 porta: gpio-port@0 {
 143                                         compatible = "snps,dw-apb-gpio-port";
 144                                         gpio-controller;
 145                                         #gpio-cells = <2>;
 146                                         snps,nr-gpios = <32>;
 147                                         reg = <0>;
 148                                         interrupt-controller;
 149                                         #interrupt-cells = <2>;
 150                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 151                                 };
 152                         };
 153
 154                         gpio1: gpio@2000 {
 155                                 compatible = "snps,dw-apb-gpio";
 156                                 reg = <0x2000 0x400>;
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159
 160                                 portb: gpio-port@1 {
 161                                         compatible = "snps,dw-apb-gpio-port";
 162                                         gpio-controller;
 163                                         #gpio-cells = <2>;
 164                                         snps,nr-gpios = <32>;
 165                                         reg = <0>;
 166                                         interrupt-controller;
 167                                         #interrupt-cells = <2>;
 168                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 169                                 };
 170                         };
 171                 };
 172         };
 173 };