1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_ALTERNATIVE_H
3 #define __ASM_ALTERNATIVE_H
5 #include <asm/cpucaps.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/stddef.h>
13 #include <linux/stringify.h>
16 s32 orig_offset
; /* offset to original instruction */
17 s32 alt_offset
; /* offset to replacement instruction */
18 u16 cpufeature
; /* cpufeature bit set for replacement */
19 u8 orig_len
; /* size of original instruction(s) */
20 u8 alt_len
; /* size of new instruction(s), <= orig_len */
23 void __init
apply_alternatives_all(void);
24 void apply_alternatives(void *start
, size_t length
);
26 #define ALTINSTR_ENTRY(feature) \
27 " .word 661b - .\n" /* label */ \
28 " .word 663f - .\n" /* new instruction */ \
29 " .hword " __stringify(feature) "\n" /* feature bit */ \
30 " .byte 662b-661b\n" /* source len */ \
31 " .byte 664f-663f\n" /* replacement len */
34 * alternative assembly primitive:
36 * If any of these .org directive fail, it means that insn1 and insn2
37 * don't have the same length. This used to be written as
39 * .if ((664b-663b) != (662b-661b))
40 * .error "Alternatives instruction length mismatch"
43 * but most assemblers die if insn1 or insn2 have a .inst. This should
44 * be fixed in a binutils release posterior to 2.25.51.0.2 (anything
45 * containing commit 4e4d08cf7399b606 or c1baaddf8861).
47 #define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled) \
48 ".if "__stringify(cfg_enabled)" == 1\n" \
52 ".pushsection .altinstructions,\"a\"\n" \
53 ALTINSTR_ENTRY(feature) \
55 ".pushsection .altinstr_replacement, \"a\"\n" \
60 ".org . - (664b-663b) + (662b-661b)\n\t" \
61 ".org . - (662b-661b) + (664b-663b)\n" \
64 #define _ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg, ...) \
65 __ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg))
69 #include <asm/assembler.h>
71 .macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len
72 .word \orig_offset
- .
79 .macro alternative_insn insn1
, insn2
, cap
, enable
= 1
82 662: .pushsection
.altinstructions
, "a"
83 altinstruction_entry
661b
, 663f
, \cap
, 662b
-661b
, 664f
-663f
85 .pushsection
.altinstr_replacement
, "ax"
88 .org
. - (664b
-663b
) + (662b
-661b
)
89 .org
. - (662b
-661b
) + (664b
-663b
)
94 * Alternative sequences
96 * The code for the case where the capability is not present will be
97 * assembled and linked as normal. There are no restrictions on this
100 * The code for the case where the capability is present will be
101 * assembled into a special section to be used for dynamic patching.
102 * Code for that case must:
104 * 1. Be exactly the same length (in bytes) as the default code
107 * 2. Not contain a branch target that is used outside of the
108 * alternative sequence it is defined in (branches into an
109 * alternative sequence are not fixed up).
113 * Begin an alternative code sequence.
115 .macro alternative_if_not cap
116 .set
.Lasm_alt_mode
, 0
117 .pushsection
.altinstructions
, "a"
118 altinstruction_entry
661f
, 663f
, \cap
, 662f
-661f
, 664f
-663f
123 .macro alternative_if cap
124 .set
.Lasm_alt_mode
, 1
125 .pushsection
.altinstructions
, "a"
126 altinstruction_entry
663f
, 661f
, \cap
, 664f
-663f
, 662f
-661f
128 .pushsection
.altinstr_replacement
, "ax"
129 .align
2 /* So GAS knows label 661 is suitably aligned */
134 * Provide the other half of the alternative code sequence.
136 .macro alternative_else
138 .if .Lasm_alt_mode
==0
139 .pushsection
.altinstr_replacement
, "ax"
147 * Complete an alternative code sequence.
149 .macro alternative_endif
151 .if .Lasm_alt_mode
==0
154 .org
. - (664b
-663b
) + (662b
-661b
)
155 .org
. - (662b
-661b
) + (664b
-663b
)
159 * Provides a trivial alternative or default sequence consisting solely
160 * of NOPs. The number of NOPs is chosen automatically to match the
163 .macro alternative_else_nop_endif
165 nops (662b
-661b
) / AARCH64_INSN_SIZE
169 #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \
170 alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)
172 .macro user_alt
, label
, oldinstr
, newinstr
, cond
173 9999: alternative_insn
"\oldinstr", "\newinstr", \cond
174 _ASM_EXTABLE
9999b
, \label
178 * Generate the assembly for UAO alternatives with exception table entries.
179 * This is complicated as there is no post-increment or pair versions of the
180 * unprivileged instructions, and USER() only works for single instructions.
182 #ifdef CONFIG_ARM64_UAO
183 .macro uao_ldp l
, reg1
, reg2
, addr
, post_inc
184 alternative_if_not ARM64_HAS_UAO
185 8888: ldp
\reg
1, \reg
2, [\addr
], \post_inc
;
190 ldtr
\reg
2, [\addr
, #8];
191 add
\addr
, \addr
, \post_inc
;
194 _asm_extable
8888b
,\l
;
195 _asm_extable
8889b
,\l
;
198 .macro uao_stp l
, reg1
, reg2
, addr
, post_inc
199 alternative_if_not ARM64_HAS_UAO
200 8888: stp
\reg
1, \reg
2, [\addr
], \post_inc
;
205 sttr
\reg
2, [\addr
, #8];
206 add
\addr
, \addr
, \post_inc
;
209 _asm_extable
8888b
,\l
;
210 _asm_extable
8889b
,\l
;
213 .macro uao_user_alternative l
, inst
, alt_inst
, reg
, addr
, post_inc
214 alternative_if_not ARM64_HAS_UAO
215 8888: \inst
\reg
, [\addr
], \post_inc
;
218 \alt_inst
\reg
, [\addr
];
219 add
\addr
, \addr
, \post_inc
;
222 _asm_extable
8888b
,\l
;
225 .macro uao_ldp l
, reg1
, reg2
, addr
, post_inc
226 USER(\l
, ldp
\reg
1, \reg
2, [\addr
], \post_inc
)
228 .macro uao_stp l
, reg1
, reg2
, addr
, post_inc
229 USER(\l
, stp
\reg
1, \reg
2, [\addr
], \post_inc
)
231 .macro uao_user_alternative l
, inst
, alt_inst
, reg
, addr
, post_inc
232 USER(\l
, \inst
\reg
, [\addr
], \post_inc
)
236 #endif /* __ASSEMBLY__ */
239 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature));
241 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO));
242 * N.B. If CONFIG_FOO is specified, but not selected, the whole block
243 * will be omitted, including oldinstr.
245 #define ALTERNATIVE(oldinstr, newinstr, ...) \
246 _ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1)
248 #endif /* __ASM_ALTERNATIVE_H */