1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
9 #include <asm/cpucaps.h>
10 #include <asm/cputype.h>
11 #include <asm/hwcap.h>
12 #include <asm/sysreg.h>
14 #define MAX_CPU_FEATURES 64
15 #define cpu_feature(x) KERNEL_HWCAP_ ## x
19 #include <linux/bug.h>
20 #include <linux/jump_label.h>
21 #include <linux/kernel.h>
24 * CPU feature register tracking
26 * The safe value of a CPUID feature field is dependent on the implications
27 * of the values assigned to it by the architecture. Based on the relationship
28 * between the values, the features are classified into 3 types - LOWER_SAFE,
29 * HIGHER_SAFE and EXACT.
31 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
32 * for HIGHER_SAFE. It is expected that all CPUs have the same value for
33 * a field when EXACT is specified, failing which, the safe value specified
34 * in the table is chosen.
38 FTR_EXACT
, /* Use a predefined safe value */
39 FTR_LOWER_SAFE
, /* Smaller value is safe */
40 FTR_HIGHER_SAFE
,/* Bigger value is safe */
43 #define FTR_STRICT true /* SANITY check strict matching required */
44 #define FTR_NONSTRICT false /* SANITY check ignored */
46 #define FTR_SIGNED true /* Value should be treated as signed */
47 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
49 #define FTR_VISIBLE true /* Feature visible to the user space */
50 #define FTR_HIDDEN false /* Feature is hidden from the user */
52 #define FTR_VISIBLE_IF_IS_ENABLED(config) \
53 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
55 struct arm64_ftr_bits
{
56 bool sign
; /* Value is signed ? */
58 bool strict
; /* CPU Sanity check: strict matching required ? */
62 s64 safe_val
; /* safe value for FTR_EXACT features */
66 * @arm64_ftr_reg - Feature register
67 * @strict_mask Bits which should match across all CPUs for sanity.
68 * @sys_val Safe value across the CPUs (system view)
70 struct arm64_ftr_reg
{
76 const struct arm64_ftr_bits
*ftr_bits
;
79 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0
;
84 * We use arm64_cpu_capabilities to represent system features, errata work
85 * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
86 * ELF HWCAPs (which are exposed to user).
88 * To support systems with heterogeneous CPUs, we need to make sure that we
89 * detect the capabilities correctly on the system and take appropriate
90 * measures to ensure there are no incompatibilities.
92 * This comment tries to explain how we treat the capabilities.
93 * Each capability has the following list of attributes :
95 * 1) Scope of Detection : The system detects a given capability by
96 * performing some checks at runtime. This could be, e.g, checking the
97 * value of a field in CPU ID feature register or checking the cpu
98 * model. The capability provides a call back ( @matches() ) to
99 * perform the check. Scope defines how the checks should be performed.
100 * There are three cases:
102 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
103 * matches. This implies, we have to run the check on all the
104 * booting CPUs, until the system decides that state of the
105 * capability is finalised. (See section 2 below)
107 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
108 * matches. This implies, we run the check only once, when the
109 * system decides to finalise the state of the capability. If the
110 * capability relies on a field in one of the CPU ID feature
111 * registers, we use the sanitised value of the register from the
112 * CPU feature infrastructure to make the decision.
114 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
115 * feature. This category is for features that are "finalised"
116 * (or used) by the kernel very early even before the SMP cpus
119 * The process of detection is usually denoted by "update" capability
122 * 2) Finalise the state : The kernel should finalise the state of a
123 * capability at some point during its execution and take necessary
124 * actions if any. Usually, this is done, after all the boot-time
125 * enabled CPUs are brought up by the kernel, so that it can make
126 * better decision based on the available set of CPUs. However, there
127 * are some special cases, where the action is taken during the early
128 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with
129 * Virtualisation Host Extensions). The kernel usually disallows any
130 * changes to the state of a capability once it finalises the capability
131 * and takes any action, as it may be impossible to execute the actions
132 * safely. A CPU brought up after a capability is "finalised" is
133 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary
134 * CPUs are treated "late CPUs" for capabilities determined by the boot
137 * At the moment there are two passes of finalising the capabilities.
138 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via
139 * setup_boot_cpu_capabilities().
140 * b) Everything except (a) - Run via setup_system_capabilities().
142 * 3) Verification: When a CPU is brought online (e.g, by user or by the
143 * kernel), the kernel should make sure that it is safe to use the CPU,
144 * by verifying that the CPU is compliant with the state of the
145 * capabilities finalised already. This happens via :
147 * secondary_start_kernel()-> check_local_cpu_capabilities()
149 * As explained in (2) above, capabilities could be finalised at
150 * different points in the execution. Each newly booted CPU is verified
151 * against the capabilities that have been finalised by the time it
154 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
155 * except for the primary boot CPU.
157 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
158 * user after the kernel boot are verified against the capability.
160 * If there is a conflict, the kernel takes an action, based on the
161 * severity (e.g, a CPU could be prevented from booting or cause a
162 * kernel panic). The CPU is allowed to "affect" the state of the
163 * capability, if it has not been finalised already. See section 5
164 * for more details on conflicts.
166 * 4) Action: As mentioned in (2), the kernel can take an action for each
167 * detected capability, on all CPUs on the system. Appropriate actions
168 * include, turning on an architectural feature, modifying the control
169 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via
170 * alternatives. The kernel patching is batched and performed at later
171 * point. The actions are always initiated only after the capability
172 * is finalised. This is usally denoted by "enabling" the capability.
173 * The actions are initiated as follows :
174 * a) Action is triggered on all online CPUs, after the capability is
175 * finalised, invoked within the stop_machine() context from
176 * enable_cpu_capabilitie().
178 * b) Any late CPU, brought up after (1), the action is triggered via:
180 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
182 * 5) Conflicts: Based on the state of the capability on a late CPU vs.
183 * the system state, we could have the following combinations :
185 * x-----------------------------x
186 * | Type | System | Late CPU |
187 * |-----------------------------|
189 * |-----------------------------|
191 * x-----------------------------x
193 * Two separate flag bits are defined to indicate whether each kind of
194 * conflict can be allowed:
195 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
196 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
198 * Case (a) is not permitted for a capability that the system requires
199 * all CPUs to have in order for the capability to be enabled. This is
200 * typical for capabilities that represent enhanced functionality.
202 * Case (b) is not permitted for a capability that must be enabled
203 * during boot if any CPU in the system requires it in order to run
204 * safely. This is typical for erratum work arounds that cannot be
205 * enabled after the corresponding capability is finalised.
207 * In some non-typical cases either both (a) and (b), or neither,
208 * should be permitted. This can be described by including neither
209 * or both flags in the capability's type field.
214 * Decide how the capability is detected.
215 * On any local CPU vs System wide vs the primary boot CPU
217 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
218 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
220 * The capabilitiy is detected on the Boot CPU and is used by kernel
221 * during early boot. i.e, the capability should be "detected" and
222 * "enabled" as early as possibly on all booting CPUs.
224 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
225 #define ARM64_CPUCAP_SCOPE_MASK \
226 (ARM64_CPUCAP_SCOPE_SYSTEM | \
227 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
228 ARM64_CPUCAP_SCOPE_BOOT_CPU)
230 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
231 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
232 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
233 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
236 * Is it permitted for a late CPU to have this capability when system
237 * hasn't already enabled it ?
239 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
240 /* Is it safe for a late CPU to miss this capability when system has it */
241 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
244 * CPU errata workarounds that need to be enabled at boot time if one or
245 * more CPUs in the system requires it. When one of these capabilities
246 * has been enabled, it is safe to allow any CPU to boot that doesn't
247 * require the workaround. However, it is not safe if a "late" CPU
248 * requires a workaround and the system hasn't enabled it already.
250 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \
251 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
253 * CPU feature detected at boot time based on system-wide value of a
254 * feature. It is safe for a late CPU to have this feature even though
255 * the system hasn't enabled it, although the feature will not be used
256 * by Linux in this case. If the system has enabled this feature already,
257 * then every late CPU must have it.
259 #define ARM64_CPUCAP_SYSTEM_FEATURE \
260 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
262 * CPU feature detected at boot time based on feature of one or more CPUs.
263 * All possible conflicts for a late CPU are ignored.
265 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \
266 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
267 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \
268 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
271 * CPU feature detected at boot time, on one or more CPUs. A late CPU
272 * is not allowed to have the capability when the system doesn't have it.
273 * It is Ok for a late CPU to miss the feature.
275 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \
276 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
277 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
280 * CPU feature used early in the boot based on the boot CPU. All secondary
281 * CPUs must match the state of the capability as detected by the boot CPU.
283 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE ARM64_CPUCAP_SCOPE_BOOT_CPU
285 struct arm64_cpu_capabilities
{
289 bool (*matches
)(const struct arm64_cpu_capabilities
*caps
, int scope
);
291 * Take the appropriate actions to enable this capability for this CPU.
292 * For each successfully booted CPU, this method is called for each
293 * globally detected capability.
295 void (*cpu_enable
)(const struct arm64_cpu_capabilities
*cap
);
297 struct { /* To be used for erratum handling only */
298 struct midr_range midr_range
;
299 const struct arm64_midr_revidr
{
300 u32 midr_rv
; /* revision/variant */
302 } * const fixed_revs
;
305 const struct midr_range
*midr_range_list
;
306 struct { /* Feature register checking */
317 * An optional list of "matches/cpu_enable" pair for the same
318 * "capability" of the same "type" as described by the parent.
319 * Only matches(), cpu_enable() and fields relevant to these
320 * methods are significant in the list. The cpu_enable is
321 * invoked only if the corresponding entry "matches()".
322 * However, if a cpu_enable() method is associated
323 * with multiple matches(), care should be taken that either
324 * the match criteria are mutually exclusive, or that the
325 * method is robust against being called multiple times.
327 const struct arm64_cpu_capabilities
*match_list
;
330 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities
*cap
)
332 return cap
->type
& ARM64_CPUCAP_SCOPE_MASK
;
336 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities
*cap
)
338 return !!(cap
->type
& ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU
);
342 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities
*cap
)
344 return !!(cap
->type
& ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU
);
348 * Generic helper for handling capabilties with multiple (match,enable) pairs
349 * of call backs, sharing the same capability bit.
350 * Iterate over each entry to see if at least one matches.
353 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities
*entry
,
356 const struct arm64_cpu_capabilities
*caps
;
358 for (caps
= entry
->match_list
; caps
->matches
; caps
++)
359 if (caps
->matches(caps
, scope
))
366 * Take appropriate action for all matching entries in the shared capability
370 cpucap_multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities
*entry
)
372 const struct arm64_cpu_capabilities
*caps
;
374 for (caps
= entry
->match_list
; caps
->matches
; caps
++)
375 if (caps
->matches(caps
, SCOPE_LOCAL_CPU
) &&
377 caps
->cpu_enable(caps
);
380 extern DECLARE_BITMAP(cpu_hwcaps
, ARM64_NCAPS
);
381 extern struct static_key_false cpu_hwcap_keys
[ARM64_NCAPS
];
382 extern struct static_key_false arm64_const_caps_ready
;
384 /* ARM64 CAPS + alternative_cb */
385 #define ARM64_NPATCHABLE (ARM64_NCAPS + 1)
386 extern DECLARE_BITMAP(boot_capabilities
, ARM64_NPATCHABLE
);
388 #define for_each_available_cap(cap) \
389 for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS)
391 bool this_cpu_has_cap(unsigned int cap
);
392 void cpu_set_feature(unsigned int num
);
393 bool cpu_have_feature(unsigned int num
);
394 unsigned long cpu_get_elf_hwcap(void);
395 unsigned long cpu_get_elf_hwcap2(void);
397 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
398 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
400 /* System capability check for constant caps */
401 static __always_inline
bool __cpus_have_const_cap(int num
)
403 if (num
>= ARM64_NCAPS
)
405 return static_branch_unlikely(&cpu_hwcap_keys
[num
]);
408 static inline bool cpus_have_cap(unsigned int num
)
410 if (num
>= ARM64_NCAPS
)
412 return test_bit(num
, cpu_hwcaps
);
415 static __always_inline
bool cpus_have_const_cap(int num
)
417 if (static_branch_likely(&arm64_const_caps_ready
))
418 return __cpus_have_const_cap(num
);
420 return cpus_have_cap(num
);
423 static inline void cpus_set_cap(unsigned int num
)
425 if (num
>= ARM64_NCAPS
) {
426 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
429 __set_bit(num
, cpu_hwcaps
);
433 static inline int __attribute_const__
434 cpuid_feature_extract_signed_field_width(u64 features
, int field
, int width
)
436 return (s64
)(features
<< (64 - width
- field
)) >> (64 - width
);
439 static inline int __attribute_const__
440 cpuid_feature_extract_signed_field(u64 features
, int field
)
442 return cpuid_feature_extract_signed_field_width(features
, field
, 4);
445 static inline unsigned int __attribute_const__
446 cpuid_feature_extract_unsigned_field_width(u64 features
, int field
, int width
)
448 return (u64
)(features
<< (64 - width
- field
)) >> (64 - width
);
451 static inline unsigned int __attribute_const__
452 cpuid_feature_extract_unsigned_field(u64 features
, int field
)
454 return cpuid_feature_extract_unsigned_field_width(features
, field
, 4);
457 static inline u64
arm64_ftr_mask(const struct arm64_ftr_bits
*ftrp
)
459 return (u64
)GENMASK(ftrp
->shift
+ ftrp
->width
- 1, ftrp
->shift
);
462 static inline u64
arm64_ftr_reg_user_value(const struct arm64_ftr_reg
*reg
)
464 return (reg
->user_val
| (reg
->sys_val
& reg
->user_mask
));
467 static inline int __attribute_const__
468 cpuid_feature_extract_field_width(u64 features
, int field
, int width
, bool sign
)
471 cpuid_feature_extract_signed_field_width(features
, field
, width
) :
472 cpuid_feature_extract_unsigned_field_width(features
, field
, width
);
475 static inline int __attribute_const__
476 cpuid_feature_extract_field(u64 features
, int field
, bool sign
)
478 return cpuid_feature_extract_field_width(features
, field
, 4, sign
);
481 static inline s64
arm64_ftr_value(const struct arm64_ftr_bits
*ftrp
, u64 val
)
483 return (s64
)cpuid_feature_extract_field_width(val
, ftrp
->shift
, ftrp
->width
, ftrp
->sign
);
486 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0
)
488 return cpuid_feature_extract_unsigned_field(mmfr0
, ID_AA64MMFR0_BIGENDEL_SHIFT
) == 0x1 ||
489 cpuid_feature_extract_unsigned_field(mmfr0
, ID_AA64MMFR0_BIGENDEL0_SHIFT
) == 0x1;
492 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0
)
494 u32 val
= cpuid_feature_extract_unsigned_field(pfr0
, ID_AA64PFR0_EL0_SHIFT
);
496 return val
== ID_AA64PFR0_EL0_32BIT_64BIT
;
499 static inline bool id_aa64pfr0_sve(u64 pfr0
)
501 u32 val
= cpuid_feature_extract_unsigned_field(pfr0
, ID_AA64PFR0_SVE_SHIFT
);
506 void __init
setup_cpu_features(void);
507 void check_local_cpu_capabilities(void);
509 u64
read_sanitised_ftr_reg(u32 id
);
511 static inline bool cpu_supports_mixed_endian_el0(void)
513 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1
));
516 static inline bool system_supports_32bit_el0(void)
518 return cpus_have_const_cap(ARM64_HAS_32BIT_EL0
);
521 static inline bool system_supports_4kb_granule(void)
526 mmfr0
= read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1
);
527 val
= cpuid_feature_extract_unsigned_field(mmfr0
,
528 ID_AA64MMFR0_TGRAN4_SHIFT
);
530 return val
== ID_AA64MMFR0_TGRAN4_SUPPORTED
;
533 static inline bool system_supports_64kb_granule(void)
538 mmfr0
= read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1
);
539 val
= cpuid_feature_extract_unsigned_field(mmfr0
,
540 ID_AA64MMFR0_TGRAN64_SHIFT
);
542 return val
== ID_AA64MMFR0_TGRAN64_SUPPORTED
;
545 static inline bool system_supports_16kb_granule(void)
550 mmfr0
= read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1
);
551 val
= cpuid_feature_extract_unsigned_field(mmfr0
,
552 ID_AA64MMFR0_TGRAN16_SHIFT
);
554 return val
== ID_AA64MMFR0_TGRAN16_SUPPORTED
;
557 static inline bool system_supports_mixed_endian_el0(void)
559 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1
));
562 static inline bool system_supports_mixed_endian(void)
567 mmfr0
= read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1
);
568 val
= cpuid_feature_extract_unsigned_field(mmfr0
,
569 ID_AA64MMFR0_BIGENDEL_SHIFT
);
574 static inline bool system_supports_fpsimd(void)
576 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD
);
579 static inline bool system_uses_ttbr0_pan(void)
581 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN
) &&
582 !cpus_have_const_cap(ARM64_HAS_PAN
);
585 static inline bool system_supports_sve(void)
587 return IS_ENABLED(CONFIG_ARM64_SVE
) &&
588 cpus_have_const_cap(ARM64_SVE
);
591 static inline bool system_supports_cnp(void)
593 return IS_ENABLED(CONFIG_ARM64_CNP
) &&
594 cpus_have_const_cap(ARM64_HAS_CNP
);
597 static inline bool system_supports_address_auth(void)
599 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH
) &&
600 (cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH_ARCH
) ||
601 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF
));
604 static inline bool system_supports_generic_auth(void)
606 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH
) &&
607 (cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH_ARCH
) ||
608 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF
));
611 static inline bool system_uses_irq_prio_masking(void)
613 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI
) &&
614 cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING
);
617 #define ARM64_SSBD_UNKNOWN -1
618 #define ARM64_SSBD_FORCE_DISABLE 0
619 #define ARM64_SSBD_KERNEL 1
620 #define ARM64_SSBD_FORCE_ENABLE 2
621 #define ARM64_SSBD_MITIGATED 3
623 static inline int arm64_get_ssbd_state(void)
625 #ifdef CONFIG_ARM64_SSBD
626 extern int ssbd_state
;
629 return ARM64_SSBD_UNKNOWN
;
633 void arm64_set_ssbd_mitigation(bool state
);
635 extern int do_emulate_mrs(struct pt_regs
*regs
, u32 sys_reg
, u32 rt
);
637 static inline u32
id_aa64mmfr0_parange_to_phys_shift(int parange
)
648 * A future PE could use a value unknown to the kernel.
649 * However, by the "D10.1.4 Principles of the ID scheme
650 * for fields in ID registers", ARM DDI 0487C.a, any new
651 * value is guaranteed to be higher than what we know already.
652 * As a safe limit, we return the limit supported by the kernel.
654 default: return CONFIG_ARM64_PA_BITS
;
657 #endif /* __ASSEMBLY__ */