arch/arm64/include/asm/insn.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2013 Huawei Ltd.
   4  * Author: Jiang Liu <liuj97@gmail.com>
   5  *
   6  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
   7  */
   8 #ifndef __ASM_INSN_H
   9 #define __ASM_INSN_H
  10 #include <linux/build_bug.h>
  11 #include <linux/types.h>
  12
  13 /* A64 instructions are always 32 bits. */
  14 #define AARCH64_INSN_SIZE               4
  15
  16 #ifndef __ASSEMBLY__
  17 /*
  18  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
  19  * Section C3.1 "A64 instruction index by encoding":
  20  * AArch64 main encoding table
  21  *  Bit position
  22  *   28 27 26 25        Encoding Group
  23  *   0  0  -  -         Unallocated
  24  *   1  0  0  -         Data processing, immediate
  25  *   1  0  1  -         Branch, exception generation and system instructions
  26  *   -  1  -  0         Loads and stores
  27  *   -  1  0  1         Data processing - register
  28  *   0  1  1  1         Data processing - SIMD and floating point
  29  *   1  1  1  1         Data processing - SIMD and floating point
  30  * "-" means "don't care"
  31  */
  32 enum aarch64_insn_encoding_class {
  33         AARCH64_INSN_CLS_UNKNOWN,       /* UNALLOCATED */
  34         AARCH64_INSN_CLS_DP_IMM,        /* Data processing - immediate */
  35         AARCH64_INSN_CLS_DP_REG,        /* Data processing - register */
  36         AARCH64_INSN_CLS_DP_FPSIMD,     /* Data processing - SIMD and FP */
  37         AARCH64_INSN_CLS_LDST,          /* Loads and stores */
  38         AARCH64_INSN_CLS_BR_SYS,        /* Branch, exception generation and
  39                                          * system instructions */
  40 };
  41
  42 enum aarch64_insn_hint_op {
  43         AARCH64_INSN_HINT_NOP   = 0x0 << 5,
  44         AARCH64_INSN_HINT_YIELD = 0x1 << 5,
  45         AARCH64_INSN_HINT_WFE   = 0x2 << 5,
  46         AARCH64_INSN_HINT_WFI   = 0x3 << 5,
  47         AARCH64_INSN_HINT_SEV   = 0x4 << 5,
  48         AARCH64_INSN_HINT_SEVL  = 0x5 << 5,
  49 };
  50
  51 enum aarch64_insn_imm_type {
  52         AARCH64_INSN_IMM_ADR,
  53         AARCH64_INSN_IMM_26,
  54         AARCH64_INSN_IMM_19,
  55         AARCH64_INSN_IMM_16,
  56         AARCH64_INSN_IMM_14,
  57         AARCH64_INSN_IMM_12,
  58         AARCH64_INSN_IMM_9,
  59         AARCH64_INSN_IMM_7,
  60         AARCH64_INSN_IMM_6,
  61         AARCH64_INSN_IMM_S,
  62         AARCH64_INSN_IMM_R,
  63         AARCH64_INSN_IMM_N,
  64         AARCH64_INSN_IMM_MAX
  65 };
  66
  67 enum aarch64_insn_register_type {
  68         AARCH64_INSN_REGTYPE_RT,
  69         AARCH64_INSN_REGTYPE_RN,
  70         AARCH64_INSN_REGTYPE_RT2,
  71         AARCH64_INSN_REGTYPE_RM,
  72         AARCH64_INSN_REGTYPE_RD,
  73         AARCH64_INSN_REGTYPE_RA,
  74         AARCH64_INSN_REGTYPE_RS,
  75 };
  76
  77 enum aarch64_insn_register {
  78         AARCH64_INSN_REG_0  = 0,
  79         AARCH64_INSN_REG_1  = 1,
  80         AARCH64_INSN_REG_2  = 2,
  81         AARCH64_INSN_REG_3  = 3,
  82         AARCH64_INSN_REG_4  = 4,
  83         AARCH64_INSN_REG_5  = 5,
  84         AARCH64_INSN_REG_6  = 6,
  85         AARCH64_INSN_REG_7  = 7,
  86         AARCH64_INSN_REG_8  = 8,
  87         AARCH64_INSN_REG_9  = 9,
  88         AARCH64_INSN_REG_10 = 10,
  89         AARCH64_INSN_REG_11 = 11,
  90         AARCH64_INSN_REG_12 = 12,
  91         AARCH64_INSN_REG_13 = 13,
  92         AARCH64_INSN_REG_14 = 14,
  93         AARCH64_INSN_REG_15 = 15,
  94         AARCH64_INSN_REG_16 = 16,
  95         AARCH64_INSN_REG_17 = 17,
  96         AARCH64_INSN_REG_18 = 18,
  97         AARCH64_INSN_REG_19 = 19,
  98         AARCH64_INSN_REG_20 = 20,
  99         AARCH64_INSN_REG_21 = 21,
 100         AARCH64_INSN_REG_22 = 22,
 101         AARCH64_INSN_REG_23 = 23,
 102         AARCH64_INSN_REG_24 = 24,
 103         AARCH64_INSN_REG_25 = 25,
 104         AARCH64_INSN_REG_26 = 26,
 105         AARCH64_INSN_REG_27 = 27,
 106         AARCH64_INSN_REG_28 = 28,
 107         AARCH64_INSN_REG_29 = 29,
 108         AARCH64_INSN_REG_FP = 29, /* Frame pointer */
 109         AARCH64_INSN_REG_30 = 30,
 110         AARCH64_INSN_REG_LR = 30, /* Link register */
 111         AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
 112         AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
 113 };
 114
 115 enum aarch64_insn_special_register {
 116         AARCH64_INSN_SPCLREG_SPSR_EL1   = 0xC200,
 117         AARCH64_INSN_SPCLREG_ELR_EL1    = 0xC201,
 118         AARCH64_INSN_SPCLREG_SP_EL0     = 0xC208,
 119         AARCH64_INSN_SPCLREG_SPSEL      = 0xC210,
 120         AARCH64_INSN_SPCLREG_CURRENTEL  = 0xC212,
 121         AARCH64_INSN_SPCLREG_DAIF       = 0xDA11,
 122         AARCH64_INSN_SPCLREG_NZCV       = 0xDA10,
 123         AARCH64_INSN_SPCLREG_FPCR       = 0xDA20,
 124         AARCH64_INSN_SPCLREG_DSPSR_EL0  = 0xDA28,
 125         AARCH64_INSN_SPCLREG_DLR_EL0    = 0xDA29,
 126         AARCH64_INSN_SPCLREG_SPSR_EL2   = 0xE200,
 127         AARCH64_INSN_SPCLREG_ELR_EL2    = 0xE201,
 128         AARCH64_INSN_SPCLREG_SP_EL1     = 0xE208,
 129         AARCH64_INSN_SPCLREG_SPSR_INQ   = 0xE218,
 130         AARCH64_INSN_SPCLREG_SPSR_ABT   = 0xE219,
 131         AARCH64_INSN_SPCLREG_SPSR_UND   = 0xE21A,
 132         AARCH64_INSN_SPCLREG_SPSR_FIQ   = 0xE21B,
 133         AARCH64_INSN_SPCLREG_SPSR_EL3   = 0xF200,
 134         AARCH64_INSN_SPCLREG_ELR_EL3    = 0xF201,
 135         AARCH64_INSN_SPCLREG_SP_EL2     = 0xF210
 136 };
 137
 138 enum aarch64_insn_variant {
 139         AARCH64_INSN_VARIANT_32BIT,
 140         AARCH64_INSN_VARIANT_64BIT
 141 };
 142
 143 enum aarch64_insn_condition {
 144         AARCH64_INSN_COND_EQ = 0x0, /* == */
 145         AARCH64_INSN_COND_NE = 0x1, /* != */
 146         AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
 147         AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
 148         AARCH64_INSN_COND_MI = 0x4, /* < 0 */
 149         AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
 150         AARCH64_INSN_COND_VS = 0x6, /* overflow */
 151         AARCH64_INSN_COND_VC = 0x7, /* no overflow */
 152         AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
 153         AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
 154         AARCH64_INSN_COND_GE = 0xa, /* signed >= */
 155         AARCH64_INSN_COND_LT = 0xb, /* signed < */
 156         AARCH64_INSN_COND_GT = 0xc, /* signed > */
 157         AARCH64_INSN_COND_LE = 0xd, /* signed <= */
 158         AARCH64_INSN_COND_AL = 0xe, /* always */
 159 };
 160
 161 enum aarch64_insn_branch_type {
 162         AARCH64_INSN_BRANCH_NOLINK,
 163         AARCH64_INSN_BRANCH_LINK,
 164         AARCH64_INSN_BRANCH_RETURN,
 165         AARCH64_INSN_BRANCH_COMP_ZERO,
 166         AARCH64_INSN_BRANCH_COMP_NONZERO,
 167 };
 168
 169 enum aarch64_insn_size_type {
 170         AARCH64_INSN_SIZE_8,
 171         AARCH64_INSN_SIZE_16,
 172         AARCH64_INSN_SIZE_32,
 173         AARCH64_INSN_SIZE_64,
 174 };
 175
 176 enum aarch64_insn_ldst_type {
 177         AARCH64_INSN_LDST_LOAD_REG_OFFSET,
 178         AARCH64_INSN_LDST_STORE_REG_OFFSET,
 179         AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
 180         AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
 181         AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
 182         AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
 183         AARCH64_INSN_LDST_LOAD_EX,
 184         AARCH64_INSN_LDST_STORE_EX,
 185 };
 186
 187 enum aarch64_insn_adsb_type {
 188         AARCH64_INSN_ADSB_ADD,
 189         AARCH64_INSN_ADSB_SUB,
 190         AARCH64_INSN_ADSB_ADD_SETFLAGS,
 191         AARCH64_INSN_ADSB_SUB_SETFLAGS
 192 };
 193
 194 enum aarch64_insn_movewide_type {
 195         AARCH64_INSN_MOVEWIDE_ZERO,
 196         AARCH64_INSN_MOVEWIDE_KEEP,
 197         AARCH64_INSN_MOVEWIDE_INVERSE
 198 };
 199
 200 enum aarch64_insn_bitfield_type {
 201         AARCH64_INSN_BITFIELD_MOVE,
 202         AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
 203         AARCH64_INSN_BITFIELD_MOVE_SIGNED
 204 };
 205
 206 enum aarch64_insn_data1_type {
 207         AARCH64_INSN_DATA1_REVERSE_16,
 208         AARCH64_INSN_DATA1_REVERSE_32,
 209         AARCH64_INSN_DATA1_REVERSE_64,
 210 };
 211
 212 enum aarch64_insn_data2_type {
 213         AARCH64_INSN_DATA2_UDIV,
 214         AARCH64_INSN_DATA2_SDIV,
 215         AARCH64_INSN_DATA2_LSLV,
 216         AARCH64_INSN_DATA2_LSRV,
 217         AARCH64_INSN_DATA2_ASRV,
 218         AARCH64_INSN_DATA2_RORV,
 219 };
 220
 221 enum aarch64_insn_data3_type {
 222         AARCH64_INSN_DATA3_MADD,
 223         AARCH64_INSN_DATA3_MSUB,
 224 };
 225
 226 enum aarch64_insn_logic_type {
 227         AARCH64_INSN_LOGIC_AND,
 228         AARCH64_INSN_LOGIC_BIC,
 229         AARCH64_INSN_LOGIC_ORR,
 230         AARCH64_INSN_LOGIC_ORN,
 231         AARCH64_INSN_LOGIC_EOR,
 232         AARCH64_INSN_LOGIC_EON,
 233         AARCH64_INSN_LOGIC_AND_SETFLAGS,
 234         AARCH64_INSN_LOGIC_BIC_SETFLAGS
 235 };
 236
 237 enum aarch64_insn_prfm_type {
 238         AARCH64_INSN_PRFM_TYPE_PLD,
 239         AARCH64_INSN_PRFM_TYPE_PLI,
 240         AARCH64_INSN_PRFM_TYPE_PST,
 241 };
 242
 243 enum aarch64_insn_prfm_target {
 244         AARCH64_INSN_PRFM_TARGET_L1,
 245         AARCH64_INSN_PRFM_TARGET_L2,
 246         AARCH64_INSN_PRFM_TARGET_L3,
 247 };
 248
 249 enum aarch64_insn_prfm_policy {
 250         AARCH64_INSN_PRFM_POLICY_KEEP,
 251         AARCH64_INSN_PRFM_POLICY_STRM,
 252 };
 253
 254 enum aarch64_insn_adr_type {
 255         AARCH64_INSN_ADR_TYPE_ADRP,
 256         AARCH64_INSN_ADR_TYPE_ADR,
 257 };
 258
 259 #define __AARCH64_INSN_FUNCS(abbr, mask, val)                           \
 260 static __always_inline bool aarch64_insn_is_##abbr(u32 code)            \
 261 {                                                                       \
 262         BUILD_BUG_ON(~(mask) & (val));                                  \
 263         return (code & (mask)) == (val);                                \
 264 }                                                                       \
 265 static __always_inline u32 aarch64_insn_get_##abbr##_value(void)        \
 266 {                                                                       \
 267         return (val);                                                   \
 268 }
 269
 270 __AARCH64_INSN_FUNCS(adr,       0x9F000000, 0x10000000)
 271 __AARCH64_INSN_FUNCS(adrp,      0x9F000000, 0x90000000)
 272 __AARCH64_INSN_FUNCS(prfm,      0x3FC00000, 0x39800000)
 273 __AARCH64_INSN_FUNCS(prfm_lit,  0xFF000000, 0xD8000000)
 274 __AARCH64_INSN_FUNCS(str_reg,   0x3FE0EC00, 0x38206800)
 275 __AARCH64_INSN_FUNCS(ldadd,     0x3F20FC00, 0x38200000)
 276 __AARCH64_INSN_FUNCS(ldr_reg,   0x3FE0EC00, 0x38606800)
 277 __AARCH64_INSN_FUNCS(ldr_lit,   0xBF000000, 0x18000000)
 278 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
 279 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
 280 __AARCH64_INSN_FUNCS(load_ex,   0x3F400000, 0x08400000)
 281 __AARCH64_INSN_FUNCS(store_ex,  0x3F400000, 0x08000000)
 282 __AARCH64_INSN_FUNCS(stp_post,  0x7FC00000, 0x28800000)
 283 __AARCH64_INSN_FUNCS(ldp_post,  0x7FC00000, 0x28C00000)
 284 __AARCH64_INSN_FUNCS(stp_pre,   0x7FC00000, 0x29800000)
 285 __AARCH64_INSN_FUNCS(ldp_pre,   0x7FC00000, 0x29C00000)
 286 __AARCH64_INSN_FUNCS(add_imm,   0x7F000000, 0x11000000)
 287 __AARCH64_INSN_FUNCS(adds_imm,  0x7F000000, 0x31000000)
 288 __AARCH64_INSN_FUNCS(sub_imm,   0x7F000000, 0x51000000)
 289 __AARCH64_INSN_FUNCS(subs_imm,  0x7F000000, 0x71000000)
 290 __AARCH64_INSN_FUNCS(movn,      0x7F800000, 0x12800000)
 291 __AARCH64_INSN_FUNCS(sbfm,      0x7F800000, 0x13000000)
 292 __AARCH64_INSN_FUNCS(bfm,       0x7F800000, 0x33000000)
 293 __AARCH64_INSN_FUNCS(movz,      0x7F800000, 0x52800000)
 294 __AARCH64_INSN_FUNCS(ubfm,      0x7F800000, 0x53000000)
 295 __AARCH64_INSN_FUNCS(movk,      0x7F800000, 0x72800000)
 296 __AARCH64_INSN_FUNCS(add,       0x7F200000, 0x0B000000)
 297 __AARCH64_INSN_FUNCS(adds,      0x7F200000, 0x2B000000)
 298 __AARCH64_INSN_FUNCS(sub,       0x7F200000, 0x4B000000)
 299 __AARCH64_INSN_FUNCS(subs,      0x7F200000, 0x6B000000)
 300 __AARCH64_INSN_FUNCS(madd,      0x7FE08000, 0x1B000000)
 301 __AARCH64_INSN_FUNCS(msub,      0x7FE08000, 0x1B008000)
 302 __AARCH64_INSN_FUNCS(udiv,      0x7FE0FC00, 0x1AC00800)
 303 __AARCH64_INSN_FUNCS(sdiv,      0x7FE0FC00, 0x1AC00C00)
 304 __AARCH64_INSN_FUNCS(lslv,      0x7FE0FC00, 0x1AC02000)
 305 __AARCH64_INSN_FUNCS(lsrv,      0x7FE0FC00, 0x1AC02400)
 306 __AARCH64_INSN_FUNCS(asrv,      0x7FE0FC00, 0x1AC02800)
 307 __AARCH64_INSN_FUNCS(rorv,      0x7FE0FC00, 0x1AC02C00)
 308 __AARCH64_INSN_FUNCS(rev16,     0x7FFFFC00, 0x5AC00400)
 309 __AARCH64_INSN_FUNCS(rev32,     0x7FFFFC00, 0x5AC00800)
 310 __AARCH64_INSN_FUNCS(rev64,     0x7FFFFC00, 0x5AC00C00)
 311 __AARCH64_INSN_FUNCS(and,       0x7F200000, 0x0A000000)
 312 __AARCH64_INSN_FUNCS(bic,       0x7F200000, 0x0A200000)
 313 __AARCH64_INSN_FUNCS(orr,       0x7F200000, 0x2A000000)
 314 __AARCH64_INSN_FUNCS(orn,       0x7F200000, 0x2A200000)
 315 __AARCH64_INSN_FUNCS(eor,       0x7F200000, 0x4A000000)
 316 __AARCH64_INSN_FUNCS(eon,       0x7F200000, 0x4A200000)
 317 __AARCH64_INSN_FUNCS(ands,      0x7F200000, 0x6A000000)
 318 __AARCH64_INSN_FUNCS(bics,      0x7F200000, 0x6A200000)
 319 __AARCH64_INSN_FUNCS(and_imm,   0x7F800000, 0x12000000)
 320 __AARCH64_INSN_FUNCS(orr_imm,   0x7F800000, 0x32000000)
 321 __AARCH64_INSN_FUNCS(eor_imm,   0x7F800000, 0x52000000)
 322 __AARCH64_INSN_FUNCS(ands_imm,  0x7F800000, 0x72000000)
 323 __AARCH64_INSN_FUNCS(extr,      0x7FA00000, 0x13800000)
 324 __AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
 325 __AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
 326 __AARCH64_INSN_FUNCS(cbz,       0x7F000000, 0x34000000)
 327 __AARCH64_INSN_FUNCS(cbnz,      0x7F000000, 0x35000000)
 328 __AARCH64_INSN_FUNCS(tbz,       0x7F000000, 0x36000000)
 329 __AARCH64_INSN_FUNCS(tbnz,      0x7F000000, 0x37000000)
 330 __AARCH64_INSN_FUNCS(bcond,     0xFF000010, 0x54000000)
 331 __AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
 332 __AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
 333 __AARCH64_INSN_FUNCS(smc,       0xFFE0001F, 0xD4000003)
 334 __AARCH64_INSN_FUNCS(brk,       0xFFE0001F, 0xD4200000)
 335 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
 336 __AARCH64_INSN_FUNCS(hint,      0xFFFFF01F, 0xD503201F)
 337 __AARCH64_INSN_FUNCS(br,        0xFFFFFC1F, 0xD61F0000)
 338 __AARCH64_INSN_FUNCS(blr,       0xFFFFFC1F, 0xD63F0000)
 339 __AARCH64_INSN_FUNCS(ret,       0xFFFFFC1F, 0xD65F0000)
 340 __AARCH64_INSN_FUNCS(eret,      0xFFFFFFFF, 0xD69F03E0)
 341 __AARCH64_INSN_FUNCS(mrs,       0xFFF00000, 0xD5300000)
 342 __AARCH64_INSN_FUNCS(msr_imm,   0xFFF8F01F, 0xD500401F)
 343 __AARCH64_INSN_FUNCS(msr_reg,   0xFFF00000, 0xD5100000)
 344
 345 #undef  __AARCH64_INSN_FUNCS
 346
 347 bool aarch64_insn_is_nop(u32 insn);
 348 bool aarch64_insn_is_branch_imm(u32 insn);
 349
 350 static inline bool aarch64_insn_is_adr_adrp(u32 insn)
 351 {
 352         return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
 353 }
 354
 355 int aarch64_insn_read(void *addr, u32 *insnp);
 356 int aarch64_insn_write(void *addr, u32 insn);
 357 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
 358 bool aarch64_insn_uses_literal(u32 insn);
 359 bool aarch64_insn_is_branch(u32 insn);
 360 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
 361 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
 362                                   u32 insn, u64 imm);
 363 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
 364                                          u32 insn);
 365 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
 366                                 enum aarch64_insn_branch_type type);
 367 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
 368                                      enum aarch64_insn_register reg,
 369                                      enum aarch64_insn_variant variant,
 370                                      enum aarch64_insn_branch_type type);
 371 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 372                                      enum aarch64_insn_condition cond);
 373 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
 374 u32 aarch64_insn_gen_nop(void);
 375 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
 376                                 enum aarch64_insn_branch_type type);
 377 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
 378                                     enum aarch64_insn_register base,
 379                                     enum aarch64_insn_register offset,
 380                                     enum aarch64_insn_size_type size,
 381                                     enum aarch64_insn_ldst_type type);
 382 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
 383                                      enum aarch64_insn_register reg2,
 384                                      enum aarch64_insn_register base,
 385                                      int offset,
 386                                      enum aarch64_insn_variant variant,
 387                                      enum aarch64_insn_ldst_type type);
 388 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
 389                                    enum aarch64_insn_register base,
 390                                    enum aarch64_insn_register state,
 391                                    enum aarch64_insn_size_type size,
 392                                    enum aarch64_insn_ldst_type type);
 393 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
 394                            enum aarch64_insn_register address,
 395                            enum aarch64_insn_register value,
 396                            enum aarch64_insn_size_type size);
 397 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
 398                            enum aarch64_insn_register value,
 399                            enum aarch64_insn_size_type size);
 400 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
 401                                  enum aarch64_insn_register src,
 402                                  int imm, enum aarch64_insn_variant variant,
 403                                  enum aarch64_insn_adsb_type type);
 404 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
 405                          enum aarch64_insn_register reg,
 406                          enum aarch64_insn_adr_type type);
 407 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
 408                               enum aarch64_insn_register src,
 409                               int immr, int imms,
 410                               enum aarch64_insn_variant variant,
 411                               enum aarch64_insn_bitfield_type type);
 412 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
 413                               int imm, int shift,
 414                               enum aarch64_insn_variant variant,
 415                               enum aarch64_insn_movewide_type type);
 416 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
 417                                          enum aarch64_insn_register src,
 418                                          enum aarch64_insn_register reg,
 419                                          int shift,
 420                                          enum aarch64_insn_variant variant,
 421                                          enum aarch64_insn_adsb_type type);
 422 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
 423                            enum aarch64_insn_register src,
 424                            enum aarch64_insn_variant variant,
 425                            enum aarch64_insn_data1_type type);
 426 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
 427                            enum aarch64_insn_register src,
 428                            enum aarch64_insn_register reg,
 429                            enum aarch64_insn_variant variant,
 430                            enum aarch64_insn_data2_type type);
 431 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
 432                            enum aarch64_insn_register src,
 433                            enum aarch64_insn_register reg1,
 434                            enum aarch64_insn_register reg2,
 435                            enum aarch64_insn_variant variant,
 436                            enum aarch64_insn_data3_type type);
 437 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
 438                                          enum aarch64_insn_register src,
 439                                          enum aarch64_insn_register reg,
 440                                          int shift,
 441                                          enum aarch64_insn_variant variant,
 442                                          enum aarch64_insn_logic_type type);
 443 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
 444                                        enum aarch64_insn_variant variant,
 445                                        enum aarch64_insn_register Rn,
 446                                        enum aarch64_insn_register Rd,
 447                                        u64 imm);
 448 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
 449                           enum aarch64_insn_register Rm,
 450                           enum aarch64_insn_register Rn,
 451                           enum aarch64_insn_register Rd,
 452                           u8 lsb);
 453 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
 454                               enum aarch64_insn_prfm_type type,
 455                               enum aarch64_insn_prfm_target target,
 456                               enum aarch64_insn_prfm_policy policy);
 457 s32 aarch64_get_branch_offset(u32 insn);
 458 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
 459
 460 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
 461 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
 462
 463 s32 aarch64_insn_adrp_get_offset(u32 insn);
 464 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
 465
 466 bool aarch32_insn_is_wide(u32 insn);
 467
 468 #define A32_RN_OFFSET   16
 469 #define A32_RT_OFFSET   12
 470 #define A32_RT2_OFFSET   0
 471
 472 u32 aarch64_insn_extract_system_reg(u32 insn);
 473 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
 474 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
 475 u32 aarch32_insn_mcr_extract_crm(u32 insn);
 476
 477 typedef bool (pstate_check_t)(unsigned long);
 478 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
 479 #endif /* __ASSEMBLY__ */
 480
 481 #endif  /* __ASM_INSN_H */